On 6/7/2026 11:51 PM, Monk Chiang wrote:
From: Jim Wilson <[email protected]> The SiFive-7 series processors have a dual-pipeline architecture with load latency of 3 cycles. However, when a load instruction produces an address register that is used immediately by a subsequent load or store with zero offset, the address can be forwarded after 2 cycles instead of 3. This reduces pipeline stalls for common address calculation patterns like: ld a0, 0(a1) # Load pointer, 3-cycle latency ld a2, 0(a0) # Use as address with zero offset, bypass to 2 cycles Changes in v2: - Fix sifive-7-load-address-bypass test for rv32 targets. gcc/ * config/riscv/riscv-protos.h (riscv_zero_offset_address_bypass_p): New function. * config/riscv/riscv.cc (riscv_zero_offset_address_bypass_p): New function. * config/riscv/sifive-7.md: Add bypass definition. gcc/testsuite/ * gcc.target/riscv/sifive-7-load-address-bypass.c: New test.
And I've pushed this as well. Thanks! jeff
