> -----Original Message-----
> From: Wilco Dijkstra <[email protected]>
> Sent: 09 June 2026 13:22
> To: Tamar Christina <[email protected]>; Kyrylo Tkachov
> <[email protected]>; Alice Carlotti <[email protected]>; Alex Coplan
> <[email protected]>; Andrew Pinski
> <[email protected]>
> Cc: GCC Patches <[email protected]>
> Subject: Re: [PATCH v2] AArch64: Avoid zeroing movprfx on MOV/FMOV
>
> Hi Tamar,
>
> > Just to check, so this means that during streaming mode we generate an SVE
> 0
> > broadcast using mov right?
>
> Yes, it will generate the zero separately so if movi d0, 0 is not available,
> it will
> use
> an SVE move.
Thanks for checking!
>
> > But could you add a small comment on top of the patterns to say why we
> don't
> > model the zeroing versions?
>
> I've added:
>
> ;; Avoid patterns that use a zeroing movprfx like:
> ;;
> ;; movprfx z0.s, p0/z, z0.s
> ;; fmov z0.s, p0/m, #C
> ;;
> ;; This creates a false dependency on z0 which can result in stalls.
> ;; The zeroing will be done via a movi d0, 0 which is cheaper.
> ;;
>
> Cheers,
> Wilco
>
>
> v2: add comments, add 2 missing c++ test fixes.
>
> A zeroing movprfx with merging MOV/FMOV should be avoided since they
> result in a
> read of the destination register - this introduces extra dependencies
> eventhough
> the read has no useful effect. Remove such patterns so that the zero value is
> created via MOV d0, 0. Update various tests.
>
> Passes regress, OK for commit?
Perfect! Ok.
Thanks,
Tamar
>
> gcc:
>
> * config/aarch64/aarch64-sve.md: Remove zeroing movprfx of
> merging MOV
>
> gcc/testsuite:
>
> * gcc.target/aarch64/sve/acle/asm/dup_bf16.c: Update.
> * gcc.target/aarch64/sve/acle/asm/dup_f16.c: Update.
> * gcc.target/aarch64/sve/acle/asm/dup_f32.c: Update.
> * gcc.target/aarch64/sve/acle/asm/dup_f64.c: Update.
> * gcc.target/aarch64/sve/acle/asm/dup_s16.c: Update.
> * gcc.target/aarch64/sve/acle/asm/dup_s32.c: Update.
> * gcc.target/aarch64/sve/acle/asm/dup_s64.c: Update.
> * gcc.target/aarch64/sve/acle/asm/dup_s8.c: Update.
> * gcc.target/aarch64/sve/acle/asm/dup_u16.c: Update.
> * gcc.target/aarch64/sve/acle/asm/dup_u32.c: Update.
> * gcc.target/aarch64/sve/acle/asm/dup_u64.c: Update.
> * gcc.target/aarch64/sve/acle/asm/dup_u8.c: Update.
> * gcc.target/aarch64/sve/acle/asm/mul_s16.c: Update.
> * gcc.target/aarch64/sve/acle/asm/mul_s32.c: Update.
> * gcc.target/aarch64/sve/acle/asm/mul_s64.c: Update.
> * gcc.target/aarch64/sve/acle/asm/mul_s8.c: Update.
> * gcc.target/aarch64/sve/acle/asm/mul_u16.c: Update.
> * gcc.target/aarch64/sve/acle/asm/mul_u32.c: Update.
> * gcc.target/aarch64/sve/acle/asm/mul_u64.c: Update.
> * gcc.target/aarch64/sve/acle/asm/mul_u8.c: Update.
> * gcc.target/aarch64/sve/vcond_18.c: Update.
> * g++.target/aarch64/sve/dup_sel_5.C: Update.
> * g++.target/aarch64/sve/dup_sel_6.C: Update.
>
> ---
>
> diff --git a/gcc/config/aarch64/aarch64-sve.md
> b/gcc/config/aarch64/aarch64-sve.md
> index
> 9523b75441c47d80eb82f5020437a1372a156330..4d67ad0dc8753baab1a
> 69428ad4cb1f04736a583 100644
> --- a/gcc/config/aarch64/aarch64-sve.md
> +++ b/gcc/config/aarch64/aarch64-sve.md
> @@ -8601,6 +8601,14 @@ (define_expand
> "@vcond_mask_<mode><vpred>"
> ;; For the other instructions, using the element size is more natural,
> ;; so we do that for SEL as well.
> ;;
> +;; Avoid patterns that use a zeroing movprfx like:
> +;;
> +;; movprfx z0.s, p0/z, z0.s
> +;; fmov z0.s, p0/m, #C
> +;;
> +;; This creates a false dependency on z0 which can result in stalls.
> +;; The zeroing will be done via a movi d0, 0 which is cheaper.
> +;;
> (define_insn "*vcond_mask_<mode><vpred>"
> [(set (match_operand:SVE_ALL 0 "register_operand")
> (unspec:SVE_ALL
> @@ -8616,30 +8624,35 @@ (define_insn "*vcond_mask_<mode><vpred>"
> [ w , vss , 0 , Upa ; * ] mov\t%0.<Vetype>, %3/m,
> #%I1
> [ w , vss , Dz , Upa ; * ] mov\t%0.<Vetype>, %3/z,
> #%I1
> [ w , Ufc , 0 , Upa ; * ] fmov\t%0.<Vetype>, %3/m,
> #%1
> - [ ?w , Ufc , Dz , Upl ; yes ] movprfx\t%0.<Vetype>,
> %3/z,
> %0.<Vetype>\;fmov\t%0.<Vetype>, %3/m, #%1
> [ ?&w , vss , w , Upa ; yes ] movprfx\t%0,
> %2\;mov\t%0.<Vetype>,
> %3/m, #%I1
> [ ?&w , Ufc , w , Upa ; yes ] movprfx\t%0,
> %2\;fmov\t%0.<Vetype>, %3/m, #%1
> }
> )
>
> -;; Optimize selects between a duplicated scalar variable and another vector,
> -;; the latter of which can be a zero constant or a variable. Treat
> duplicates
> -;; of GPRs as being more expensive than duplicates of FPRs, since they
> -;; involve a cross-file move.
> +;; Optimize selects between a duplicated scalar variable and another vector.
> +;; Treat duplicates of GPRs as being more expensive than duplicates of FPRs
> +;; since they involve a cross-file move.
> +;;
> +;; Avoid patterns that use a zeroing movprfx like:
> +;;
> +;; movprfx z0.s, p0/z, z0.s
> +;; mov z0.s, p0/m, #C
> +;;
> +;; This creates a false dependency on z0 which can result in stalls.
> +;; The zeroing will be done via a movi d0, 0 which is cheaper.
> +;;
> (define_insn "@aarch64_sel_dup<mode>"
> [(set (match_operand:SVE_ALL 0 "register_operand")
> (unspec:SVE_ALL
> [(match_operand:<VPRED> 3 "register_operand")
> (vec_duplicate:SVE_ALL
> (match_operand:<VEL> 1 "register_operand"))
> - (match_operand:SVE_ALL 2 "aarch64_simd_reg_or_zero")]
> + (match_operand:SVE_ALL 2 "register_operand")]
> UNSPEC_SEL))]
> "TARGET_SVE"
> {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ]
> [ ?w , r , 0 , Upl ; * ] mov\t%0.<Vetype>, %3/m,
> %<vwcore>1
> [ w , w , 0 , Upl ; * ] mov\t%0.<Vetype>, %3/m,
> %<Vetype>1
> - [ ??w , r , Dz , Upl ; yes ] movprfx\t%0.<Vetype>, %3/z,
> %0.<Vetype>\;mov\t%0.<Vetype>, %3/m, %<vwcore>1
> - [ ?&w , w , Dz , Upl ; yes ] movprfx\t%0.<Vetype>, %3/z,
> %0.<Vetype>\;mov\t%0.<Vetype>, %3/m, %<Vetype>1
> [ ??&w , r , w , Upl ; yes ] movprfx\t%0,
> %2\;mov\t%0.<Vetype>,
> %3/m, %<vwcore>1
> [ ?&w , w , w , Upl ; yes ] movprfx\t%0,
> %2\;mov\t%0.<Vetype>,
> %3/m, %<Vetype>1
> }
> diff --git a/gcc/testsuite/g++.target/aarch64/sve/dup_sel_5.C
> b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_5.C
> index
> 2fb903a91510d0c49576614b48af549faedfd86b..21bbf781f1268877f1e6e
> a08474fd911894477f0 100644
> --- a/gcc/testsuite/g++.target/aarch64/sve/dup_sel_5.C
> +++ b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_5.C
> @@ -15,4 +15,4 @@ foo (int32_t val)
> asm volatile ("" :: "w" (x));
> }
>
> -/* { dg-final { scan-assembler {\tmovprfx\tz0\.s, p[0-7]/z,
> z0\.s\n\tmov\tz0\.s, p[0-7]/m, w[0-9]+\n} } } */
> +/* { dg-final { scan-assembler {\tmov\tz0\.s, p[0-7]/m, w[0-9]+\n} } } */
> diff --git a/gcc/testsuite/g++.target/aarch64/sve/dup_sel_6.C
> b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_6.C
> index
> f2b0181bb82d719fa42f4e7d9cdf37c9784690b8..7db426bd81d03f3d9ec6
> 76508e5dcc5a17e3c7a4 100644
> --- a/gcc/testsuite/g++.target/aarch64/sve/dup_sel_6.C
> +++ b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_6.C
> @@ -15,4 +15,4 @@ foo (float val)
> asm volatile ("" :: "w" (x));
> }
>
> -/* { dg-final { scan-assembler {\tmovprfx\tz0\.s, p[0-7]/z,
> z0\.s\n\tmov\tz0\.s, p[0-7]/m, s[0-9]+\n} } } */
> +/* { dg-final { scan-assembler {\tmov\tz[0-7]+\.s, p[0-7]/m, s[0-9]+\n} } }
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_bf16.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_bf16.c
> index
> db47d849c5fffd7a8954bbca688b8962d57b3e30..fd9a654f42a768b41163d
> 67a7bc845a325ea3ded 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_bf16.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_bf16.c
> @@ -23,7 +23,7 @@ TEST_UNIFORM_ZD (dup_h4_bf16_m, svbfloat16_t,
> __bf16,
>
> /*
> ** dup_h4_bf16_z:
> -** movprfx z0\.h, p0/z, z0\.h
> +** movi d0, #?0
> ** mov z0\.h, p0/m, h4
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c
> index
> 68e41ab15fd98374a5e2b2a0e910df61303b9380..2f276a117012528e5802
> 80ed5a87d76e92e8b48c 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c
> @@ -151,7 +151,7 @@ TEST_UNIFORM_Z (dup_513_f16_z, svfloat16_t,
> z0 = svdup_f16_z (p0, 513))
> /*
> ** dup_h4_f16_z:
> -** movprfx z0\.h, p0/z, z0\.h
> +** movi d0, #?0
> ** mov z0\.h, p0/m, h4
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c
> index
> 29f4e520cf92d06031a036789f631a6e5bd616f2..d5a8f6f4d6b74282634cd
> 8d252919b915378d5be 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c
> @@ -108,7 +108,7 @@ TEST_UNIFORM_ZD (dup_s4_f32_m, svfloat32_t,
> float,
>
> /*
> ** dup_1_f32_z:
> -** movprfx z0\.s, p0/z, z0\.s
> +** movi d0, #?0
> ** fmov z0\.s, p0/m, #1\.0(?:e\+0)?
> ** ret
> */
> @@ -127,7 +127,7 @@ TEST_UNIFORM_Z (dup_0_f32_z, svfloat32_t,
>
> /*
> ** dup_8_f32_z:
> -** movprfx z0\.s, p0/z, z0\.s
> +** movi d0, #?0
> ** fmov z0\.s, p0/m, #8\.0(?:e\+0)?
> ** ret
> */
> @@ -147,7 +147,7 @@ TEST_UNIFORM_Z (dup_513_f32_z, svfloat32_t,
>
> /*
> ** dup_s4_f32_z:
> -** movprfx z0\.s, p0/z, z0\.s
> +** movi d0, #?0
> ** mov z0\.s, p0/m, s4
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c
> index
> 6501b86fb89c88b61942e4dc3119175925359948..f4313864f3f708efd0da
> 99ccccd22decd2403877 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c
> @@ -108,7 +108,7 @@ TEST_UNIFORM_ZD (dup_d4_f64_m, svfloat64_t,
> double,
>
> /*
> ** dup_1_f64_z:
> -** movprfx z0\.d, p0/z, z0\.d
> +** movi d0, #?0
> ** fmov z0\.d, p0/m, #1\.0(?:e\+0)?
> ** ret
> */
> @@ -127,7 +127,7 @@ TEST_UNIFORM_Z (dup_0_f64_z, svfloat64_t,
>
> /*
> ** dup_8_f64_z:
> -** movprfx z0\.d, p0/z, z0\.d
> +** movi d0, #?0
> ** fmov z0\.d, p0/m, #8\.0(?:e\+0)?
> ** ret
> */
> @@ -147,7 +147,7 @@ TEST_UNIFORM_Z (dup_513_f64_z, svfloat64_t,
>
> /*
> ** dup_d4_f64_z:
> -** movprfx z0\.d, p0/z, z0\.d
> +** movi d0, #?0
> ** mov z0\.d, p0/m, d4
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c
> index
> 5bcd3b45751762c15bdc26f5820305eb68f2b8d2..66b45ef3277d972255d
> 3682603c6ab1f1ccd3601 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c
> @@ -950,7 +950,7 @@ TEST_UNIFORM_Z (dup_0_s16_z, svint16_t,
>
> /*
> ** dup_w0_s16_z:
> -** movprfx z0\.h, p0/z, z0\.h
> +** movi d0, #?0
> ** mov z0\.h, p0/m, w0
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c
> index
> b9cb1e5883d77d35e3c737e9447eb20e7c0adc0b..2337c370801b5a49563
> 370fbfb81f0da05b1315c 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c
> @@ -918,7 +918,7 @@ TEST_UNIFORM_Z (dup_0_s32_z, svint32_t,
>
> /*
> ** dup_w0_s32_z:
> -** movprfx z0\.s, p0/z, z0\.s
> +** movi d0, #?0
> ** mov z0\.s, p0/m, w0
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c
> index
> e63bcf225d7ddfe9bf583f5941eed000fcef6be6..de702273af85faa6adef0f8
> 58ca2138a71b73b24 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c
> @@ -918,7 +918,7 @@ TEST_UNIFORM_Z (dup_0_s64_z, svint64_t,
>
> /*
> ** dup_x0_s64_z:
> -** movprfx z0\.d, p0/z, z0\.d
> +** movi d0, #?0
> ** mov z0\.d, p0/m, x0
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c
> index
> 66c8c92e27cf95ce235efcc2cb450158ec521f51..c984eeb51c443a46e4edc0
> 7c942dde20b9e83cae 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c
> @@ -284,7 +284,7 @@ TEST_UNIFORM_Z (dup_0_s8_z, svint8_t,
>
> /*
> ** dup_w0_s8_z:
> -** movprfx z0\.b, p0/z, z0\.b
> +** movi d0, #?0
> ** mov z0\.b, p0/m, w0
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c
> index
> 284d0476a9d3c1faccf5d7609d5e6be6e4969a5c..0825a1503add16404393
> 0dfc07ea35e7048636c6 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c
> @@ -950,7 +950,7 @@ TEST_UNIFORM_Z (dup_0_u16_z, svuint16_t,
>
> /*
> ** dup_w0_u16_z:
> -** movprfx z0\.h, p0/z, z0\.h
> +** movi d0, #?0
> ** mov z0\.h, p0/m, w0
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c
> index
> 77f39cc267b55f3834a7a9d33172649120769fcd..3416ff2808efab29bacd44
> 303691b3d3261ad7bb 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c
> @@ -918,7 +918,7 @@ TEST_UNIFORM_Z (dup_0_u32_z, svuint32_t,
>
> /*
> ** dup_w0_u32_z:
> -** movprfx z0\.s, p0/z, z0\.s
> +** movi d0, #?0
> ** mov z0\.s, p0/m, w0
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c
> index
> 385b427f4972df360af812b97179834ccebddd43..f31648ce2eb738c32e890
> 36cb83cc34771e96d2d 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c
> @@ -918,7 +918,7 @@ TEST_UNIFORM_Z (dup_0_u64_z, svuint64_t,
>
> /*
> ** dup_x0_u64_z:
> -** movprfx z0\.d, p0/z, z0\.d
> +** movi d0, #?0
> ** mov z0\.d, p0/m, x0
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c
> index
> 8f2be55f23dcccff07dd6c078358839b1467610e..bebb62a01d264c6bc4038
> 1b822aaf758a148dad4 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c
> @@ -284,7 +284,7 @@ TEST_UNIFORM_Z (dup_0_u8_z, svuint8_t,
>
> /*
> ** dup_w0_u8_z:
> -** movprfx z0\.b, p0/z, z0\.b
> +** movi d0, #?0
> ** mov z0\.b, p0/m, w0
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c
> index
> 4148097cc63cb0bce6326e6bb4cae3d28364a407..fb680a90923003895e65
> 2aeaec8aa98a3ce3ed84 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c
> @@ -333,7 +333,7 @@ TEST_UNIFORM_Z (mul_1op1_s16_z_tied2,
> svint16_t,
>
> /*
> ** mul_1op1n_s16_z:
> -** movprfx z0\.h, p0/z, z0\.h
> +** movi d0, #?0
> ** mov z0\.h, p0/m, w0
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c
> index
> 2c53e3f14d64710fd663a76cb2a2721ea4e254c3..fac7fa9c2796beb0ce4dd1
> 53543f3d1a4f943777 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c
> @@ -343,7 +343,7 @@ TEST_UNIFORM_Z (mul_1op1_s32_z_tied2,
> svint32_t,
>
> /*
> ** mul_1op1n_s32_z:
> -** movprfx z0\.s, p0/z, z0\.s
> +** movi d0, #?0
> ** mov z0\.s, p0/m, w0
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c
> index
> 55342a13f8bd623103abbda13377f25ce6b9a8b8..a7ddf7efae8d8747af891
> 29e6e3b89225ba0e83d 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c
> @@ -342,7 +342,7 @@ TEST_UNIFORM_Z (mul_1op1_s64_z_tied2,
> svint64_t,
>
> /*
> ** mul_1op1n_s64_z:
> -** movprfx z0\.d, p0/z, z0\.d
> +** movi d0, #?0
> ** mov z0\.d, p0/m, x0
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c
> index
> 786a424eeead9f1eb767e57a9ef932effbda4288..e85ed420ddd1497c90f4f3
> 8164182bc3b9a3fee0 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c
> @@ -333,7 +333,7 @@ TEST_UNIFORM_Z (mul_1op1_s8_z_tied2, svint8_t,
>
> /*
> ** mul_1op1n_s8_z:
> -** movprfx z0\.b, p0/z, z0\.b
> +** movi d0, #?0
> ** mov z0\.b, p0/m, w0
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c
> index
> ed08635382d51cceb7e3f519b5398d09bd75eaae..6f193bccbb6bcb70bf963
> 4b1e75c89adbaa64dc9 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c
> @@ -314,7 +314,7 @@ TEST_UNIFORM_Z (mul_1op1_u16_z_tied2,
> svuint16_t,
>
> /*
> ** mul_1op1n_u16_z:
> -** movprfx z0\.h, p0/z, z0\.h
> +** movi d0, #?0
> ** mov z0\.h, p0/m, w0
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c
> index
> f82ac4269e8fd37e9c9455f6f1e0d028e7457c97..c1638ae1645e165ca9b00f
> 8b2d994d518c738e9b 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c
> @@ -314,7 +314,7 @@ TEST_UNIFORM_Z (mul_1op1_u32_z_tied2,
> svuint32_t,
>
> /*
> ** mul_1op1n_u32_z:
> -** movprfx z0\.s, p0/z, z0\.s
> +** movi d0, #?0
> ** mov z0\.s, p0/m, w0
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c
> index
> 9f1bfff5fd2fd0a4f9d09d962f8ad9dd81eb1e49..1161871483b6eea88fcb58
> d1cfd50c9e956fadef 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c
> @@ -335,7 +335,7 @@ TEST_UNIFORM_Z (mul_1op1_u64_z_tied2,
> svuint64_t,
>
> /*
> ** mul_1op1n_u64_z:
> -** movprfx z0\.d, p0/z, z0\.d
> +** movi d0, #?0
> ** mov z0\.d, p0/m, x0
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c
> b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c
> index
> b2c1edf5ff8245dc8ec08a11493571f7d01aabac..48593487f8c476b916f923
> 9fa181e29337ee2033 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c
> @@ -314,7 +314,7 @@ TEST_UNIFORM_Z (mul_1op1_u8_z_tied2,
> svuint8_t,
>
> /*
> ** mul_1op1n_u8_z:
> -** movprfx z0\.b, p0/z, z0\.b
> +** movi d0, #?0
> ** mov z0\.b, p0/m, w0
> ** ret
> */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c
> b/gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c
> index
> bd83e4c377d03002e746e3c449eeab4ee629fa07..40451b1fb56797a0a201
> 346372a897bd646c4c13 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c
> @@ -31,14 +31,14 @@ TEST_ALL (DEF_LOOP)
> /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-9]+/z, #-
> 16128\n} 1 } } */
> /* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-9]+, z[0-9]+\.h,
> z[0-9]+\.h\n} 2 } } */
>
> -/* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.s), (p[0-7])/z,
> \1\n\tfmov\t\1, \2/m, #2\.0(?:e[+]0)?\n} } } */
> -/* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.s), (p[0-7])/z,
> \1\n\tfmov\t\1, \2/m, #1\.25(?:e[+]0)?\n} } } */
> -/* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.s), (p[0-7])/z,
> \1\n\tfmov\t\1, \2/m, #-4\.0(?:e[+]0)?\n} } } */
> -/* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.s), (p[0-7])/z,
> \1\n\tfmov\t\1, \2/m, #-2\.5(?:e[+]0)?\n} } } */
> +/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m,
> #2\.0(?:e[+]0)?\n} } } */
> +/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m,
> #1\.25(?:e[+]0)?\n} } } */
> +/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m, #-
> 4\.0(?:e[+]0)?\n} } } */
> +/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m, #-
> 2\.5(?:e[+]0)?\n} } } */
> /* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-9]+, z[0-9]+\.s,
> z[0-9]+\.s\n} 2 } } */
>
> -/* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.d), (p[0-7])/z,
> \1\n\tfmov\t\1, \2/m, #2\.0(?:e[+]0)?\n} } } */
> -/* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.d), (p[0-7])/z,
> \1\n\tfmov\t\1, \2/m, #1\.25(?:e[+]0)?\n} } } */
> -/* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.d), (p[0-7])/z,
> \1\n\tfmov\t\1, \2/m, #-4\.0(?:e[+]0)?\n} } } */
> -/* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.d), (p[0-7])/z,
> \1\n\tfmov\t\1, \2/m, #-2\.5(?:e[+]0)?\n} } } */
> +/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m,
> #2\.0(?:e[+]0)?\n} } } */
> +/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m,
> #1\.25(?:e[+]0)?\n} } } */
> +/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m, #-
> 4\.0(?:e[+]0)?\n} } } */
> +/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m, #-
> 2\.5(?:e[+]0)?\n} } } */
> /* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-9]+, z[0-9]+\.d,
> z[0-9]+\.d\n} 2 } } */
