Fix vcond_18.c test.
Committed as obvious.
gcc/testsuite:
* gcc.target/aarch64/sve/vcond_18.c: Update.
---
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c
b/gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c
index
40451b1fb56797a0a201346372a897bd646c4c13..3fea50c17ea09b14d97e1834c0b8835d9e6a3883
100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c
@@ -37,8 +37,8 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m,
#-2\.5(?:e[+]0)?\n} } } */
/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-9]+, z[0-9]+\.s,
z[0-9]+\.s\n} 2 } } */
-/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m,
#2\.0(?:e[+]0)?\n} } } */
-/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m,
#1\.25(?:e[+]0)?\n} } } */
-/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m,
#-4\.0(?:e[+]0)?\n} } } */
-/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m,
#-2\.5(?:e[+]0)?\n} } } */
+/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.d, p[0-9]+/m,
#2\.0(?:e[+]0)?\n} } } */
+/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.d, p[0-9]+/m,
#1\.25(?:e[+]0)?\n} } } */
+/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.d, p[0-9]+/m,
#-4\.0(?:e[+]0)?\n} } } */
+/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.d, p[0-9]+/m,
#-2\.5(?:e[+]0)?\n} } } */
/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-9]+, z[0-9]+\.d,
z[0-9]+\.d\n} 2 } } */
