The FEAT_SVE_AES/FEAT_SVE_PMULL128 architecture relaxation changes the
requirement from FEAT_SVE2 to "one or more of FEAT_SVE2 and FEAT_SSVE_AES".
This means the existing SVE2 AES instructions (AESE, AESD, AESMC, AESIMC,
PMULLB, PMULLT and their .Q pair variants) become available in streaming
SVE mode when FEAT_SSVE_AES is enabled.
---
gcc/config/aarch64/aarch64-c.cc | 4 +++-
gcc/config/aarch64/aarch64-sve2.md | 8 ++++----
gcc/config/aarch64/aarch64.h | 13 +++++++++----
gcc/config/aarch64/iterators.md | 2 +-
4 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index e11cf95a08a..7b2a970bf0f 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -226,7 +226,8 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
&& (AARCH64_HAVE_ISA (SVE2) || TARGET_SME2),
"__ARM_FEATURE_SVE_B16B16", pfile);
aarch64_def_or_undef (AARCH64_HAVE_ISA (SVE2), "__ARM_FEATURE_SVE2", pfile);
- aarch64_def_or_undef (TARGET_SVE2_AES, "__ARM_FEATURE_SVE2_AES", pfile);
+ aarch64_def_or_undef (AARCH64_HAVE_ISA (SVE2) && AARCH64_HAVE_ISA (SVE_AES),
+ "__ARM_FEATURE_SVE2_AES", pfile);
aarch64_def_or_undef (AARCH64_HAVE_ISA (SVE_BITPERM)
&& AARCH64_HAVE_ISA (SVE2),
"__ARM_FEATURE_SVE2_BITPERM", pfile);
@@ -312,6 +313,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
"__ARM_FEATURE_SME_F16F16", pfile);
aarch64_def_or_undef (TARGET_SME_F64F64, "__ARM_FEATURE_SME_F64F64", pfile);
aarch64_def_or_undef (TARGET_SME2, "__ARM_FEATURE_SME2", pfile);
+
aarch64_def_or_undef (AARCH64_HAVE_ISA (SME2p1),
"__ARM_FEATURE_SME2p1", pfile);
aarch64_def_or_undef (TARGET_SME2p2, "__ARM_FEATURE_SME2p2", pfile);
diff --git a/gcc/config/aarch64/aarch64-sve2.md
b/gcc/config/aarch64/aarch64-sve2.md
index 1d428619c07..4bf9710519f 100644
--- a/gcc/config/aarch64/aarch64-sve2.md
+++ b/gcc/config/aarch64/aarch64-sve2.md
@@ -4715,7 +4715,7 @@ (define_insn "aarch64_sve2_aes<aes_op>"
(match_operand:VNx16QI 1 "register_operand" "%0")
(match_operand:VNx16QI 2 "register_operand" "w"))]
CRYPTO_AES))]
- "TARGET_SVE2_AES"
+ "TARGET_SVE_AES"
"aes<aes_op>\t%0.b, %0.b, %2.b"
[(set_attr "type" "crypto_aese")]
)
@@ -4726,7 +4726,7 @@ (define_insn "aarch64_sve2_aes<aesmc_op>"
(unspec:VNx16QI
[(match_operand:VNx16QI 1 "register_operand" "0")]
CRYPTO_AESMC))]
- "TARGET_SVE2_AES"
+ "TARGET_SVE_AES"
"aes<aesmc_op>\t%0.b, %0.b"
[(set_attr "type" "crypto_aesmc")]
)
@@ -4745,7 +4745,7 @@ (define_insn "*aarch64_sve2_aese_fused"
(match_operand:VNx16QI 2 "register_operand" "w"))]
UNSPEC_AESE)]
UNSPEC_AESMC))]
- "TARGET_SVE2_AES && aarch64_fusion_enabled_p (AARCH64_FUSE_AES_AESMC)"
+ "TARGET_SVE_AES && aarch64_fusion_enabled_p (AARCH64_FUSE_AES_AESMC)"
"aese\t%0.b, %0.b, %2.b\;aesmc\t%0.b, %0.b"
[(set_attr "type" "crypto_aese")
(set_attr "length" "8")]
@@ -4760,7 +4760,7 @@ (define_insn "*aarch64_sve2_aesd_fused"
(match_operand:VNx16QI 2 "register_operand" "w"))]
UNSPEC_AESD)]
UNSPEC_AESIMC))]
- "TARGET_SVE2_AES && aarch64_fusion_enabled_p (AARCH64_FUSE_AES_AESMC)"
+ "TARGET_SVE_AES && aarch64_fusion_enabled_p (AARCH64_FUSE_AES_AESMC)"
"aesd\t%0.b, %0.b, %2.b\;aesimc\t%0.b, %0.b"
[(set_attr "type" "crypto_aese")
(set_attr "length" "8")]
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index c3c61c6939c..83cbe46fed8 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -290,10 +290,15 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE
ATTRIBUTE_UNUSED
/* SVE2 instructions, enabled in non-streaming mode through +sve2. */
#define TARGET_SVE2 (AARCH64_HAVE_ISA (SVE2) || TARGET_STREAMING)
-/* SVE2 AES instructions, enabled through +sve2-aes. */
-#define TARGET_SVE2_AES (AARCH64_HAVE_ISA (SVE2) \
- && AARCH64_HAVE_ISA (SVE_AES) \
- && TARGET_NON_STREAMING)
+/*
+For:
+ - SVE2 AES instructions (enabled through +sve2-aes)
+ - SSVE AES instructions (enabled through +ssve-aes)
+*/
+#define TARGET_SVE_AES (AARCH64_HAVE_ISA (SVE_AES) \
+ && (AARCH64_HAVE_ISA (SVE2) || TARGET_STREAMING) \
+ && (AARCH64_HAVE_ISA (SSVE_AES) \
+ || TARGET_NON_STREAMING))
/* SVE BITPERM instructions, enabled through +sve-bitperm+sve2 for
non-streaming
and +ssve-bitperm for streaming. */
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 2d1522a348a..f65d85be1f5 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -741,7 +741,7 @@ (define_mode_iterator SVE_4HSI [VNx4HI VNx4SI])
;; SVE integer modes that can form the input to an SVE2 PMULL[BT] instruction.
(define_mode_iterator SVE2_PMULL_PAIR_I [VNx16QI VNx4SI
- (VNx2DI "TARGET_SVE2_AES")])
+ (VNx2DI "TARGET_SVE_AES")])
;; Modes involved in extending or truncating SVE data, for 8 elements per
;; 128-bit block.
--
2.43.0
