This patch adds support for the Zvzip (Vector Structured Data Reordering) extension v0.1 draft, per the RISC-V ISA manual PR #2529[1] and the riscv-rvv-intrinsic-doc PR #431[2].
Zvzip provides five instructions for interleaving and deinterleaving vector register elements: - vzip.vv: interleave elements from two sources (dest EMUL=2*LMUL) - vunzipe.v: extract even-indexed elements (src EMUL=2*LMUL) - vunzipo.v: extract odd-indexed elements (src EMUL=2*LMUL) - vpaire.vv: interleave even-indexed element pairs (same EMUL) - vpairo.vv: interleave odd-indexed element pairs (same EMUL) The extension depends on Zve32x. The implementation does not expose forms that would require EMUL greater than 8: vzip does not expose source LMUL=8 forms, and vunzip does not expose destination LMUL=8 forms. A custom zvzip_zip shape is introduced for vzip.vv, whose intrinsic API suffix names the destination type while the instance type is the source type. The masked vzip intrinsic uses the mask type derived from the source vector type, following the current rvv-intrinsic-doc PR #431[2]. [1] https://github.com/riscv/riscv-isa-manual/pull/2529 [2] https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/pull/431 gcc/ChangeLog: * config/riscv/gen-riscv-ext-opt.cc (DEFINE_RISCV_EXT): New def. * config/riscv/riscv-ext.def (ZVZIP): New extension. * config/riscv/riscv-ext.opt: Ditto. * config/riscv/riscv-vector-builtins-bases.cc (class vzip): New class. (class vunzipe): Ditto. (class vunzipo): Ditto. (class vpaire): Ditto. (class vpairo): Ditto. (vzip_obj, vunzipe_obj, vunzipo_obj, vpaire_obj, vpairo_obj): New static objects. (BASE): Register vzip, vunzipe, vunzipo, vpaire, vpairo. * config/riscv/riscv-vector-builtins-bases.h: Declare vzip, vunzipe, vunzipo, vpaire, vpairo bases. * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS): Set to ZVZIP_EXT and register them. * config/riscv/riscv-vector-builtins-shapes.cc (supports_vectype_p): New check. (struct zvzip_zip_def): New shape class. (SHAPE): Declare zvzip_zip. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (all_vv_ops): New operand info table. (all_vzip_vv_ops): Ditto. (get_builtin_partition): Add ZVZIP_EXT -> RVV_PARTITION_ZVZIP. * config/riscv/riscv-vector-builtins.h (enum required_ext): Add ZVZIP_EXT. (enum rvv_builtin_partition): Add RVV_PARTITION_ZVZIP. (required_ext_to_isa_name): Return "zvzip" for ZVZIP_EXT. (required_extensions_specified): Return TARGET_ZVZIP for ZVZIP_EXT. * config/riscv/riscv_vector.h (__riscv_intrinsic_zvzip): New definition. * config/riscv/vector-iterators.md (unspecv): New UNSPECs. (VLMULX2): New mode iterators. (VLMUL_EXT2): New mode attribute. * config/riscv/vector.md (@pred_vzip<mode>): New pattern. (@pred_vunzipe<mode>): Ditto. (@pred_vunzipo<mode>): Ditto. (@pred_vpaire<mode>): Ditto. (@pred_vpairo<mode>): Ditto. * doc/riscv-ext.texi: Document zvzip extension version 0.1. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/intrinsic-detection.c: Add Zvzip. * gcc.target/riscv/rvv/base/zvzip-bf16-require-zvfbfmin.c: Ditto. * gcc.target/riscv/rvv/base/zvzip-bf16.c: Ditto. * gcc.target/riscv/rvv/base/zvzip-intrinsic-asm.c: Ditto. * gcc.target/riscv/rvv/base/zvzip-lmul-boundary.c: Ditto. * gcc.target/riscv/rvv/base/zvzip-mask-type.c: Ditto. * gcc.target/riscv/rvv/base/zvzip-overloaded.c: Ditto. * gcc.target/riscv/rvv/base/zvzip-policy.c: Ditto. --- gcc/config/riscv/gen-riscv-ext-opt.cc | 11 +- gcc/config/riscv/riscv-ext.def | 13 ++ gcc/config/riscv/riscv-ext.opt | 5 + .../riscv/riscv-vector-builtins-bases.cc | 55 +++++++ .../riscv/riscv-vector-builtins-bases.h | 5 + .../riscv/riscv-vector-builtins-functions.def | 11 ++ .../riscv/riscv-vector-builtins-shapes.cc | 37 ++++- .../riscv/riscv-vector-builtins-shapes.h | 1 + gcc/config/riscv/riscv-vector-builtins.cc | 18 +++ gcc/config/riscv/riscv-vector-builtins.h | 6 + gcc/config/riscv/riscv_vector.h | 1 + gcc/config/riscv/vector-iterators.md | 61 ++++++++ gcc/config/riscv/vector.md | 107 ++++++++++++++ gcc/doc/riscv-ext.texi | 4 + .../riscv/rvv/base/intrinsic-detection.c | 9 +- .../rvv/base/zvzip-bf16-require-zvfbfmin.c | 10 ++ .../gcc.target/riscv/rvv/base/zvzip-bf16.c | 12 ++ .../riscv/rvv/base/zvzip-intrinsic-asm.c | 78 ++++++++++ .../riscv/rvv/base/zvzip-lmul-boundary.c | 30 ++++ .../riscv/rvv/base/zvzip-mask-type.c | 21 +++ .../riscv/rvv/base/zvzip-overloaded.c | 48 ++++++ .../gcc.target/riscv/rvv/base/zvzip-policy.c | 139 ++++++++++++++++++ 23 files changed, 689 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-bf16-require-zvfbfmin.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-bf16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-intrinsic-asm.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-lmul-boundary.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-mask-type.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-overloaded.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-policy.c diff --git a/gcc/config/riscv/gen-riscv-ext-opt.cc b/gcc/config/riscv/gen-riscv-ext-opt.cc index cc73bd7388a..d55113cd340 100644 --- a/gcc/config/riscv/gen-riscv-ext-opt.cc +++ b/gcc/config/riscv/gen-riscv-ext-opt.cc @@ -50,10 +50,19 @@ main () printf ("int %s\n\n", var.c_str ()); } + bool first_mask = true; #define DEFINE_RISCV_EXT(NAME, UPPERCASE_NAME, FULL_NAME, DESC, URL, DEP_EXTS, \ SUPPORTED_VERSIONS, FLAG_GROUP, BITMASK_GROUP_ID, \ BITMASK_BIT_POSITION, EXTRA_EXTENSION_FLAGS) \ - puts ("Mask(" #UPPERCASE_NAME ") Var(riscv_" #FLAG_GROUP "_subext)\n"); + do \ + { \ + if (!first_mask) \ + puts (""); \ + printf ("Mask(" #UPPERCASE_NAME ") Var(riscv_" #FLAG_GROUP \ + "_subext)\n"); \ + first_mask = false; \ + } \ + while (false); #include "riscv-ext.def" #undef DEFINE_RISCV_EXT diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def index b9ef0c5ea05..3244b6d090d 100644 --- a/gcc/config/riscv/riscv-ext.def +++ b/gcc/config/riscv/riscv-ext.def @@ -1156,6 +1156,19 @@ DEFINE_RISCV_EXT( /* BITMASK_BIT_POSITION*/ 62, /* EXTRA_EXTENSION_FLAGS */ 0) +DEFINE_RISCV_EXT( + /* NAME */ zvzip, + /* UPPERCASE_NAME */ ZVZIP, + /* FULL_NAME */ "Vector structured data reordering extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{0, 1}}), + /* FLAG_GROUP */ zv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + DEFINE_RISCV_EXT( /* NAME */ zvfbfmin, /* UPPERCASE_NAME */ ZVFBFMIN, diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt index 802c9eb4170..73817f77f17 100644 --- a/gcc/config/riscv/riscv-ext.opt +++ b/gcc/config/riscv/riscv-ext.opt @@ -91,6 +91,9 @@ int riscv_zm_subext TargetVariable int riscv_zt_subext +TargetVariable +int riscv_zv_subext + TargetVariable int riscv_zvb_subext @@ -264,6 +267,8 @@ Mask(ZVE64F) Var(riscv_zve_subext) Mask(ZVE64X) Var(riscv_zve_subext) +Mask(ZVZIP) Var(riscv_zv_subext) + Mask(ZVFBFMIN) Var(riscv_zvf_subext) Mask(ZVFOFP8MIN) Var(riscv_zvf_subext) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 0ae9b34fa2b..71f427bbd02 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1703,6 +1703,51 @@ public: } }; +class vzip : public function_base +{ +public: + rtx expand (function_expander &e) const override + { + return e.use_exact_insn (code_for_pred_vzip (e.vector_mode ())); + } +}; + +class vunzipe : public function_base +{ +public: + rtx expand (function_expander &e) const override + { + return e.use_exact_insn (code_for_pred_vunzipe (e.vector_mode ())); + } +}; + +class vunzipo : public function_base +{ +public: + rtx expand (function_expander &e) const override + { + return e.use_exact_insn (code_for_pred_vunzipo (e.vector_mode ())); + } +}; + +class vpaire : public function_base +{ +public: + rtx expand (function_expander &e) const override + { + return e.use_exact_insn (code_for_pred_vpaire (e.vector_mode ())); + } +}; + +class vpairo : public function_base +{ +public: + rtx expand (function_expander &e) const override + { + return e.use_exact_insn (code_for_pred_vpairo (e.vector_mode ())); + } +}; + class vcompress : public function_base { public: @@ -2698,6 +2743,11 @@ static CONSTEXPR const slideop<UNSPEC_VFSLIDE1UP> vfslide1up_obj; static CONSTEXPR const slideop<UNSPEC_VFSLIDE1DOWN> vfslide1down_obj; static CONSTEXPR const vrgather vrgather_obj; static CONSTEXPR const vrgatherei16 vrgatherei16_obj; +static CONSTEXPR const vzip vzip_obj; +static CONSTEXPR const vunzipe vunzipe_obj; +static CONSTEXPR const vunzipo vunzipo_obj; +static CONSTEXPR const vpaire vpaire_obj; +static CONSTEXPR const vpairo vpairo_obj; static CONSTEXPR const vcompress vcompress_obj; static CONSTEXPR const vundefined vundefined_obj; static CONSTEXPR const vreinterpret vreinterpret_obj; @@ -3028,6 +3078,11 @@ BASE (vfslide1up) BASE (vfslide1down) BASE (vrgather) BASE (vrgatherei16) +BASE (vzip) +BASE (vunzipe) +BASE (vunzipo) +BASE (vpaire) +BASE (vpairo) BASE (vcompress) BASE (vundefined) BASE (vreinterpret) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 9261d353e22..b9abaa670a5 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -266,6 +266,11 @@ extern const function_base *const vfslide1up; extern const function_base *const vfslide1down; extern const function_base *const vrgather; extern const function_base *const vrgatherei16; +extern const function_base *const vzip; +extern const function_base *const vunzipe; +extern const function_base *const vunzipo; +extern const function_base *const vpaire; +extern const function_base *const vpairo; extern const function_base *const vcompress; extern const function_base *const vundefined; extern const function_base *const vreinterpret; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index f64d42d1823..790e4f91d15 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -598,6 +598,17 @@ DEF_RVV_FUNCTION (vslide1down, alu, full_preds, iu_vvx_ops) DEF_RVV_FUNCTION (vrgather, alu, full_preds, all_gather_vvv_ops) DEF_RVV_FUNCTION (vrgather, alu, full_preds, all_gather_vvx_ops) +/* Zvzip v0.1 draft. */ +#undef REQUIRED_EXTENSIONS +#define REQUIRED_EXTENSIONS ZVZIP_EXT +DEF_RVV_FUNCTION (vzip, zvzip_zip, full_preds, all_vzip_vv_ops) +DEF_RVV_FUNCTION (vunzipe, alu, full_preds, all_v_vlmul_trunc_x2_ops) +DEF_RVV_FUNCTION (vunzipo, alu, full_preds, all_v_vlmul_trunc_x2_ops) +DEF_RVV_FUNCTION (vpaire, alu, full_preds, all_vv_ops) +DEF_RVV_FUNCTION (vpairo, alu, full_preds, all_vv_ops) +#undef REQUIRED_EXTENSIONS +#define REQUIRED_EXTENSIONS VECTOR_EXT + // 16.5. Vector Compress Instruction DEF_RVV_FUNCTION (vcompress, alu, none_tu_preds, all_vvm_ops) diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index a113bae56e1..5c8867c1278 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -97,7 +97,8 @@ supports_vectype_p (const function_group_info &group, unsigned int vec_type_idx) || *group.shape == shapes::fault_load || *group.shape == shapes::seg_loadstore || *group.shape == shapes::seg_indexed_loadstore - || *group.shape == shapes::seg_fault_load) + || *group.shape == shapes::seg_fault_load + || group.required_extensions == ZVZIP_EXT) return true; return false; } @@ -424,6 +425,39 @@ struct alu_def : public build_base } }; +/* zvzip_zip_def class. Handle vzip.vv, whose API suffix names the + destination type while its instance type is the source type. + + Masked vzip follows current rvv-intrinsic-doc PR #431; + the mask type is derived from the source vector type, not the 2xLMUL + return type. */ +struct zvzip_zip_def : public build_base +{ + char *get_name (function_builder &b, const function_instance &instance, + bool overloaded_p) const override + { + if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred)) + return nullptr; + + b.append_base_name (instance.base_name); + + if (!overloaded_p) + { + b.append_name (operand_suffixes[instance.op_info->op]); + vector_type_index ret_type_idx + = instance.op_info->ret.get_function_type_index (instance.type.index); + b.append_name (type_suffixes[ret_type_idx].vector); + } + + /* According to rvv-intrinsic-doc, it does not add "_m" suffix + for vop_m C++ overloaded API. */ + if (overloaded_p && instance.pred == PRED_TYPE_m) + return b.finish_name (); + b.append_name (predication_suffixes[instance.pred]); + return b.finish_name (); + } +}; + /* The base class for frm build. */ struct build_frm_base : public build_base { @@ -1400,6 +1434,7 @@ SHAPE(indexed_loadstore, indexed_loadstore) SHAPE(th_loadstore_width, th_loadstore_width) SHAPE(th_indexed_loadstore_width, th_indexed_loadstore_width) SHAPE(alu, alu) +SHAPE(zvzip_zip, zvzip_zip) SHAPE(alu_frm, alu_frm) SHAPE(widen_alu, widen_alu) SHAPE(widen_alu_frm, widen_alu_frm) diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.h b/gcc/config/riscv/riscv-vector-builtins-shapes.h index d9502d4c5b4..ddd21e99be0 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.h +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.h @@ -31,6 +31,7 @@ extern const function_shape *const indexed_loadstore; extern const function_shape *const th_loadstore_width; extern const function_shape *const th_indexed_loadstore_width; extern const function_shape *const alu; +extern const function_shape *const zvzip_zip; extern const function_shape *const alu_frm; extern const function_shape *const widen_alu; extern const function_shape *const widen_alu_frm; diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 0fcc60b5942..2c48a3fb6dc 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -1554,6 +1554,14 @@ static CONSTEXPR const rvv_op_info all_vvvm_ops rvv_arg_type_info (RVV_BASE_vector), /* Return type */ vvm_args /* Args */}; +/* A static operand information for vector_type func (vector_type, + * vector_type) function registration. */ +static CONSTEXPR const rvv_op_info all_vv_ops + = {all_ops, /* Types */ + OP_TYPE_vv, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + vv_args /* Args */}; + /* A static operand information for vector_type func (vector_type, vector_type, * mask_type) function registration. */ static CONSTEXPR const rvv_op_info all_vvm_ops @@ -1859,6 +1867,14 @@ static CONSTEXPR const rvv_op_info all_gatherei16_vvv_ops rvv_arg_type_info (RVV_BASE_vector), /* Return type */ gatherei16_vv_args /* Args */}; +/* A static operand information for x2-lmul vector_type func (vector_type, + * vector_type) function registration. */ +static CONSTEXPR const rvv_op_info all_vzip_vv_ops + = {vlmul_ext_x2_ops, /* Types */ + OP_TYPE_vv, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vlmul_ext_x2), /* Return type */ + vv_args /* Args */}; + /* A static operand information for vector_type func (vector_type) * function registration. */ static CONSTEXPR const rvv_op_info iu_v_ops @@ -3656,6 +3672,8 @@ get_builtin_partition (required_ext ext, const function_instance &instance) return RVV_PARTITION_ZVFBFWMA; case ZVFOFP8MIN_EXT: return RVV_PARTITION_ZVFOFP8MIN; + case ZVZIP_EXT: + return RVV_PARTITION_ZVZIP; case XSFVQMACCQOQ_EXT: return RVV_PARTITION_XSFVQMACCQOQ; case XSFVQMACCDOD_EXT: diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h index aa20cb82c48..b4382d30110 100644 --- a/gcc/config/riscv/riscv-vector-builtins.h +++ b/gcc/config/riscv/riscv-vector-builtins.h @@ -131,6 +131,7 @@ enum required_ext ZVFBFMIN_EXT, /* Zvfbfmin extension */ ZVFBFWMA_EXT, /* Zvfbfwma extension */ ZVFOFP8MIN_EXT, /* Zvfofp8min extension */ + ZVZIP_EXT, /* Zvzip extension */ XSFVQMACCQOQ_EXT, /* XSFVQMACCQOQ extension */ XSFVQMACCDOD_EXT, /* XSFVQMACCDOD extension */ XSFVFNRCLIPXFQF_EXT, /* XSFVFNRCLIPXFQF extension */ @@ -162,6 +163,7 @@ enum rvv_builtin_partition RVV_PARTITION_ZVFHMIN, RVV_PARTITION_ZVFH, RVV_PARTITION_ZVFOFP8MIN, + RVV_PARTITION_ZVZIP, RVV_PARTITION_XSFVQMACCQOQ, RVV_PARTITION_XSFVQMACCDOD, RVV_PARTITION_XSFVFNRCLIPXFQF, @@ -216,6 +218,8 @@ static inline const char * required_ext_to_isa_name (enum required_ext required) return "zvfbfwma"; case ZVFOFP8MIN_EXT: return "zvfofp8min"; + case ZVZIP_EXT: + return "zvzip"; case XSFVQMACCQOQ_EXT: return "xsfvqmaccqoq"; case XSFVQMACCDOD_EXT: @@ -273,6 +277,8 @@ static inline bool required_extensions_specified (enum required_ext required) return TARGET_ZVFBFWMA; case ZVFOFP8MIN_EXT: return TARGET_ZVFOFP8MIN; + case ZVZIP_EXT: + return TARGET_ZVZIP; case XSFVQMACCQOQ_EXT: return TARGET_XSFVQMACCQOQ; case XSFVQMACCDOD_EXT: diff --git a/gcc/config/riscv/riscv_vector.h b/gcc/config/riscv/riscv_vector.h index bda75833ef2..42a6763d463 100644 --- a/gcc/config/riscv/riscv_vector.h +++ b/gcc/config/riscv/riscv_vector.h @@ -40,6 +40,7 @@ #define __riscv_intrinsic_zvfbfwma 1 #define __riscv_intrinsic_zvfh 1 #define __riscv_intrinsic_zvfhmin 1 +#define __riscv_intrinsic_zvzip 1 #define __riscv_intrinsic_zvkb 1 #define __riscv_intrinsic_zvkg 1 #define __riscv_intrinsic_zvkned 1 diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 62a1eb3fbc0..35e56639dca 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -76,6 +76,11 @@ UNSPEC_VFSLIDE1DOWN UNSPEC_VRGATHER UNSPEC_VRGATHEREI16 + UNSPEC_VZIP + UNSPEC_VUNZIPE + UNSPEC_VUNZIPO + UNSPEC_VPAIRE + UNSPEC_VPAIRO UNSPEC_VCOMPRESS UNSPEC_VLEFF UNSPEC_MODIFY_VL @@ -681,6 +686,62 @@ (V512QI "riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= 1024") ]) +;; Source modes for Zvzip instructions whose destination/source operand has +;; 2x LMUL, without exposing forms that would require LMUL > 8. +(define_mode_iterator VLMULX2 [ + (RVVMF8QI "TARGET_VECTOR_ELEN_64") + RVVMF4QI RVVMF2QI RVVM1QI RVVM2QI RVVM4QI + + (RVVMF4HI "TARGET_VECTOR_ELEN_64") + RVVMF2HI RVVM1HI RVVM2HI RVVM4HI + + (RVVMF4BF "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_64") + (RVVMF2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM1BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM4BF "TARGET_VECTOR_ELEN_BF_16") + + (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_64") + (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") + (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") + (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") + (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") + + (RVVMF2SI "TARGET_VECTOR_ELEN_64") + RVVM1SI RVVM2SI RVVM4SI + + (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_VECTOR_ELEN_64") + (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") + (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") + (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") + + (RVVM1DI "TARGET_VECTOR_ELEN_64") + (RVVM2DI "TARGET_VECTOR_ELEN_64") + (RVVM4DI "TARGET_VECTOR_ELEN_64") + + (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") + (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") + (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") +]) + +(define_mode_attr VLMUL_EXT2 [ + (RVVMF8QI "RVVMF4QI") (RVVMF4QI "RVVMF2QI") (RVVMF2QI "RVVM1QI") (RVVM1QI "RVVM2QI") (RVVM2QI "RVVM4QI") (RVVM4QI "RVVM8QI") + + (RVVMF4HI "RVVMF2HI") (RVVMF2HI "RVVM1HI") (RVVM1HI "RVVM2HI") (RVVM2HI "RVVM4HI") (RVVM4HI "RVVM8HI") + + (RVVMF4BF "RVVMF2BF") (RVVMF2BF "RVVM1BF") (RVVM1BF "RVVM2BF") (RVVM2BF "RVVM4BF") (RVVM4BF "RVVM8BF") + + (RVVMF4HF "RVVMF2HF") (RVVMF2HF "RVVM1HF") (RVVM1HF "RVVM2HF") (RVVM2HF "RVVM4HF") (RVVM4HF "RVVM8HF") + + (RVVMF2SI "RVVM1SI") (RVVM1SI "RVVM2SI") (RVVM2SI "RVVM4SI") (RVVM4SI "RVVM8SI") + + (RVVMF2SF "RVVM1SF") (RVVM1SF "RVVM2SF") (RVVM2SF "RVVM4SF") (RVVM4SF "RVVM8SF") + + (RVVM1DI "RVVM2DI") (RVVM2DI "RVVM4DI") (RVVM4DI "RVVM8DI") + + (RVVM1DF "RVVM2DF") (RVVM2DF "RVVM4DF") (RVVM4DF "RVVM8DF") +]) + (define_mode_iterator VEI16 [ RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_VECTOR_ELEN_64") diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index fba631d670f..c8b71aeb625 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -8567,6 +8567,113 @@ [(set_attr "type" "vgather") (set_attr "mode" "<MODE>")]) +;; Zvzip v0.1 draft. +(define_insn "@pred_vzip<mode>" + [(set (match_operand:<VLMUL_EXT2> 0 "register_operand" "=&vr, &vr") + (if_then_else:<VLMUL_EXT2> + (unspec:<VM> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rvl, rvl") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (unspec:<VLMUL_EXT2> + [(match_operand:VLMULX2 3 "register_operand" " vr, vr") + (match_operand:VLMULX2 4 "register_operand" " vr, vr")] UNSPEC_VZIP) + (match_operand:<VLMUL_EXT2> 2 "vector_merge_operand" " vu, 0")))] + "TARGET_ZVZIP" + "vzip.vv\t%0,%3,%4%p1" + [(set_attr "type" "vgather") + (set_attr "mode" "<MODE>")]) + +(define_insn "@pred_vunzipe<mode>" + [(set (match_operand:VLMULX2 0 "register_operand" "=&vr, &vr") + (if_then_else:VLMULX2 + (unspec:<VM> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rvl, rvl") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (unspec:VLMULX2 + [(match_operand:<VLMUL_EXT2> 3 "register_operand" " vr, vr")] UNSPEC_VUNZIPE) + (match_operand:VLMULX2 2 "vector_merge_operand" " vu, 0")))] + "TARGET_ZVZIP" + "vunzipe.v\t%0,%3%p1" + [(set_attr "type" "vgather") + (set_attr "mode" "<MODE>") + (set_attr "vl_op_idx" "4") + (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])")) + (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) + (set_attr "avl_type_idx" "7")]) + +(define_insn "@pred_vunzipo<mode>" + [(set (match_operand:VLMULX2 0 "register_operand" "=&vr, &vr") + (if_then_else:VLMULX2 + (unspec:<VM> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rvl, rvl") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (unspec:VLMULX2 + [(match_operand:<VLMUL_EXT2> 3 "register_operand" " vr, vr")] UNSPEC_VUNZIPO) + (match_operand:VLMULX2 2 "vector_merge_operand" " vu, 0")))] + "TARGET_ZVZIP" + "vunzipo.v\t%0,%3%p1" + [(set_attr "type" "vgather") + (set_attr "mode" "<MODE>") + (set_attr "vl_op_idx" "4") + (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])")) + (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) + (set_attr "avl_type_idx" "7")]) + +(define_insn "@pred_vpaire<mode>" + [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr") + (if_then_else:V_VLS + (unspec:<VM> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rvl, rvl") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (unspec:V_VLS + [(match_operand:V_VLS 3 "register_operand" " vr, vr") + (match_operand:V_VLS 4 "register_operand" " vr, vr")] UNSPEC_VPAIRE) + (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))] + "TARGET_ZVZIP" + "vpaire.vv\t%0,%3,%4%p1" + [(set_attr "type" "vgather") + (set_attr "mode" "<MODE>")]) + +(define_insn "@pred_vpairo<mode>" + [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr") + (if_then_else:V_VLS + (unspec:<VM> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rvl, rvl") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (unspec:V_VLS + [(match_operand:V_VLS 3 "register_operand" " vr, vr") + (match_operand:V_VLS 4 "register_operand" " vr, vr")] UNSPEC_VPAIRO) + (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))] + "TARGET_ZVZIP" + "vpairo.vv\t%0,%3,%4%p1" + [(set_attr "type" "vgather") + (set_attr "mode" "<MODE>")]) + ;; vcompress (define_insn "@pred_compress<mode>" [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr") diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi index 728cde737a7..d007c134ac1 100644 --- a/gcc/doc/riscv-ext.texi +++ b/gcc/doc/riscv-ext.texi @@ -334,6 +334,10 @@ @tab 1.0 @tab Vector extensions for embedded processors +@item @samp{zvzip} +@tab 0.1 +@tab Vector structured data reordering extension + @item @samp{zvfbfmin} @tab 1.0 @tab Vector BF16 converts extension diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic-detection.c b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic-detection.c index d11cd26afa3..784eed0e1fe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic-detection.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic-detection.c @@ -11,9 +11,10 @@ || defined (__riscv_zve64x) \ || defined (__riscv_zvbc) || defined (__riscv_zvfbfmin) \ || defined (__riscv_zvfbfwma) || defined (__riscv_zvfh) \ - || defined (__riscv_zvfhmin) || defined (__riscv_zvkb) \ - || defined (__riscv_zvkg) || defined (__riscv_zvkned) \ - || defined (__riscv_zvknha) || defined (__riscv_zvknhb) \ + || defined (__riscv_zvfhmin) || defined (__riscv_zvzip) \ + || defined (__riscv_zvkb) || defined (__riscv_zvkg) \ + || defined (__riscv_zvkned) || defined (__riscv_zvknha) \ + || defined (__riscv_zvknhb) \ || defined (__riscv_zvksed) || defined (__riscv_zvksh) #error "unexpected vector ISA extension macro" #endif @@ -30,6 +31,7 @@ || !defined (__riscv_intrinsic_zvfbfwma) \ || !defined (__riscv_intrinsic_zvfh) \ || !defined (__riscv_intrinsic_zvfhmin) \ + || !defined (__riscv_intrinsic_zvzip) \ || !defined (__riscv_intrinsic_zvkb) \ || !defined (__riscv_intrinsic_zvkg) \ || !defined (__riscv_intrinsic_zvkn) \ @@ -66,6 +68,7 @@ || __riscv_intrinsic_zvfbfwma != 1 \ || __riscv_intrinsic_zvfh != 1 \ || __riscv_intrinsic_zvfhmin != 1 \ + || __riscv_intrinsic_zvzip != 1 \ || __riscv_intrinsic_zvkb != 1 \ || __riscv_intrinsic_zvkg != 1 \ || __riscv_intrinsic_zvkn != 1 \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-bf16-require-zvfbfmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-bf16-require-zvfbfmin.c new file mode 100644 index 00000000000..21f0d58433c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-bf16-require-zvfbfmin.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gcv_zvzip0p1 -mabi=lp64d -O2" } */ + +#include "riscv_vector.h" + +vbfloat16m2_t +test_vzip_vv_bf16m2 (vbfloat16m1_t a, vbfloat16m1_t b, size_t vl) +{ + return __riscv_vzip_vv_bf16m2 (a, b, vl); /* { dg-error {requires.*zvfbfmin} } */ +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-bf16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-bf16.c new file mode 100644 index 00000000000..e278895632d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-bf16.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gcv_zvzip0p1_zvfbfmin -mabi=lp64d -O2" } */ + +#include "riscv_vector.h" + +vbfloat16m2_t +test_vzip_vv_bf16m2 (vbfloat16m1_t a, vbfloat16m1_t b, size_t vl) +{ + return __riscv_vzip_vv_bf16m2 (a, b, vl); +} + +/* { dg-final { scan-assembler-times {vzip\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-intrinsic-asm.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-intrinsic-asm.c new file mode 100644 index 00000000000..c77194cc1a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-intrinsic-asm.c @@ -0,0 +1,78 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gcv_zvzip0p1 -mabi=lp64d -O2" } */ + +#include "riscv_vector.h" + +vint8m2_t +test_vzip_vv_i8m2 (vint8m1_t a, vint8m1_t b, size_t vl) +{ + return __riscv_vzip_vv_i8m2 (a, b, vl); +} + +/* This follows the current rvv-intrinsic-doc PR #431. */ +vint8m2_t +test_vzip_vv_i8m2_m (vbool8_t mask, vint8m1_t a, vint8m1_t b, size_t vl) +{ + return __riscv_vzip_vv_i8m2_m (mask, a, b, vl); +} + +vint8m1_t +test_vunzipe_v_i8m1 (vint8m2_t a, size_t vl) +{ + return __riscv_vunzipe_v_i8m1 (a, vl); +} + +vint8m1_t +test_vunzipe_v_i8m1_m (vbool8_t mask, vint8m2_t a, size_t vl) +{ + return __riscv_vunzipe_v_i8m1_m (mask, a, vl); +} + +vint8m1_t +test_vunzipo_v_i8m1 (vint8m2_t a, size_t vl) +{ + return __riscv_vunzipo_v_i8m1 (a, vl); +} + +vint8m1_t +test_vunzipo_v_i8m1_m (vbool8_t mask, vint8m2_t a, size_t vl) +{ + return __riscv_vunzipo_v_i8m1_m (mask, a, vl); +} + +vuint16m1_t +test_vpaire_vv_u16m1 (vuint16m1_t a, vuint16m1_t b, size_t vl) +{ + return __riscv_vpaire_vv_u16m1 (a, b, vl); +} + +vuint16m1_t +test_vpaire_vv_u16m1_m (vbool16_t mask, vuint16m1_t a, vuint16m1_t b, + size_t vl) +{ + return __riscv_vpaire_vv_u16m1_m (mask, a, b, vl); +} + +vuint16m1_t +test_vpairo_vv_u16m1 (vuint16m1_t a, vuint16m1_t b, size_t vl) +{ + return __riscv_vpairo_vv_u16m1 (a, b, vl); +} + +vuint16m1_t +test_vpairo_vv_u16m1_m (vbool16_t mask, vuint16m1_t a, vuint16m1_t b, + size_t vl) +{ + return __riscv_vpairo_vv_u16m1_m (mask, a, b, vl); +} + +/* { dg-final { scan-assembler-times {vzip\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {vunzipe\.v} 2 } } */ +/* { dg-final { scan-assembler-times {vunzipo\.v} 2 } } */ +/* { dg-final { scan-assembler-times {vpaire\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {vpairo\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {vzip\.vv[ \t]+v[0-9]+,[ \t]*v[0-9]+,[ \t]*v[0-9]+,[ \t]*v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {vunzipe\.v[ \t]+v[0-9]+,[ \t]*v[0-9]+,[ \t]*v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {vunzipo\.v[ \t]+v[0-9]+,[ \t]*v[0-9]+,[ \t]*v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {vpaire\.vv[ \t]+v[0-9]+,[ \t]*v[0-9]+,[ \t]*v[0-9]+,[ \t]*v0\.t} 1 } } */ +/* { dg-final { scan-assembler-times {vpairo\.vv[ \t]+v[0-9]+,[ \t]*v[0-9]+,[ \t]*v[0-9]+,[ \t]*v0\.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-lmul-boundary.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-lmul-boundary.c new file mode 100644 index 00000000000..94307c78896 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-lmul-boundary.c @@ -0,0 +1,30 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gcv_zvzip0p1 -mabi=lp64d -O2 -Werror=implicit-function-declaration" } */ + +#include "riscv_vector.h" + +void +test_vzip_lmul_boundary (vint8m8_t a, size_t vl) +{ + __riscv_vzip_vv_i8m16 (a, a, vl); /* { dg-error {implicit declaration} } */ + __riscv_vunzipe_v_i8m8 (a, vl); /* { dg-error {implicit declaration} } */ + __riscv_vunzipo_v_i8m8 (a, vl); /* { dg-error {implicit declaration} } */ +} + +vint8m8_t +test_vzip_lmul_boundary_ok (vint8m4_t a, size_t vl) +{ + return __riscv_vzip_vv_i8m8 (a, a, vl); +} + +vint8m4_t +test_vunzipe_lmul_boundary_ok (vint8m8_t a, size_t vl) +{ + return __riscv_vunzipe_v_i8m4 (a, vl); +} + +vint8m4_t +test_vunzipo_lmul_boundary_ok (vint8m8_t a, size_t vl) +{ + return __riscv_vunzipo_v_i8m4 (a, vl); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-mask-type.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-mask-type.c new file mode 100644 index 00000000000..9c65a7a5d7e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-mask-type.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gcv_zvzip0p1 -mabi=lp64d -O2" } */ + +#include "riscv_vector.h" + +/* This follows the current rvv-intrinsic-doc PR #431: + masked vzip uses the source vector mask type. */ + +vint8m2_t +test_vzip_mask_source_type (vbool8_t mask, vint8m1_t a, vint8m1_t b, + size_t vl) +{ + return __riscv_vzip_vv_i8m2_m (mask, a, b, vl); +} + +vint8m2_t +test_vzip_mask_return_type_rejected (vbool4_t mask, vint8m1_t a, + vint8m1_t b, size_t vl) +{ + return __riscv_vzip_vv_i8m2_m (mask, a, b, vl); /* { dg-error {incompatible type|invalid argument} } */ +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-overloaded.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-overloaded.c new file mode 100644 index 00000000000..622b46bba0c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-overloaded.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gcv_zvzip0p1 -mabi=lp64d -O2" } */ + +#include "riscv_vector.h" + +vint8m2_t +test_vzip_overloaded (vint8m1_t a, vint8m1_t b, size_t vl) +{ + return __riscv_vzip (a, b, vl); +} + +vint8m2_t +test_vzip_overloaded_m (vbool8_t mask, vint8m1_t a, vint8m1_t b, + size_t vl) +{ + return __riscv_vzip (mask, a, b, vl); +} + +vint8m1_t +test_vunzipe_overloaded (vint8m2_t a, size_t vl) +{ + return __riscv_vunzipe (a, vl); +} + +vint8m1_t +test_vunzipo_overloaded (vint8m2_t a, size_t vl) +{ + return __riscv_vunzipo (a, vl); +} + +vuint16m1_t +test_vpaire_overloaded (vuint16m1_t a, vuint16m1_t b, size_t vl) +{ + return __riscv_vpaire (a, b, vl); +} + +vuint16m1_t +test_vpairo_overloaded (vuint16m1_t a, vuint16m1_t b, size_t vl) +{ + return __riscv_vpairo (a, b, vl); +} + +/* { dg-final { scan-assembler-times {vzip\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {vunzipe\.v} 1 } } */ +/* { dg-final { scan-assembler-times {vunzipo\.v} 1 } } */ +/* { dg-final { scan-assembler-times {vpaire\.vv} 1 } } */ +/* { dg-final { scan-assembler-times {vpairo\.vv} 1 } } */ +/* { dg-final { scan-assembler-times {vzip\.vv[ \t]+v[0-9]+,[ \t]*v[0-9]+,[ \t]*v[0-9]+,[ \t]*v0\.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-policy.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-policy.c new file mode 100644 index 00000000000..6c18ae3b9a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvzip-policy.c @@ -0,0 +1,139 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gcv_zvzip0p1 -mabi=lp64d -O2" } */ + +#include "riscv_vector.h" + +vint8m2_t +test_vzip_tu (vint8m2_t merge, vint8m1_t a, vint8m1_t b, size_t vl) +{ + return __riscv_vzip_vv_i8m2_tu (merge, a, b, vl); +} + +vint8m2_t +test_vzip_tum (vbool8_t mask, vint8m2_t merge, vint8m1_t a, + vint8m1_t b, size_t vl) +{ + return __riscv_vzip_vv_i8m2_tum (mask, merge, a, b, vl); +} + +vint8m2_t +test_vzip_tumu (vbool8_t mask, vint8m2_t merge, vint8m1_t a, + vint8m1_t b, size_t vl) +{ + return __riscv_vzip_vv_i8m2_tumu (mask, merge, a, b, vl); +} + +vint8m2_t +test_vzip_mu (vbool8_t mask, vint8m2_t merge, vint8m1_t a, + vint8m1_t b, size_t vl) +{ + return __riscv_vzip_vv_i8m2_mu (mask, merge, a, b, vl); +} + +vint8m1_t +test_vunzipe_tu (vint8m1_t merge, vint8m2_t a, size_t vl) +{ + return __riscv_vunzipe_v_i8m1_tu (merge, a, vl); +} + +vint8m1_t +test_vunzipe_tum (vbool8_t mask, vint8m1_t merge, vint8m2_t a, + size_t vl) +{ + return __riscv_vunzipe_v_i8m1_tum (mask, merge, a, vl); +} + +vint8m1_t +test_vunzipe_tumu (vbool8_t mask, vint8m1_t merge, vint8m2_t a, + size_t vl) +{ + return __riscv_vunzipe_v_i8m1_tumu (mask, merge, a, vl); +} + +vint8m1_t +test_vunzipe_mu (vbool8_t mask, vint8m1_t merge, vint8m2_t a, size_t vl) +{ + return __riscv_vunzipe_v_i8m1_mu (mask, merge, a, vl); +} + +vint8m1_t +test_vunzipo_tu (vint8m1_t merge, vint8m2_t a, size_t vl) +{ + return __riscv_vunzipo_v_i8m1_tu (merge, a, vl); +} + +vint8m1_t +test_vunzipo_tum (vbool8_t mask, vint8m1_t merge, vint8m2_t a, + size_t vl) +{ + return __riscv_vunzipo_v_i8m1_tum (mask, merge, a, vl); +} + +vint8m1_t +test_vunzipo_tumu (vbool8_t mask, vint8m1_t merge, vint8m2_t a, + size_t vl) +{ + return __riscv_vunzipo_v_i8m1_tumu (mask, merge, a, vl); +} + +vint8m1_t +test_vunzipo_mu (vbool8_t mask, vint8m1_t merge, vint8m2_t a, size_t vl) +{ + return __riscv_vunzipo_v_i8m1_mu (mask, merge, a, vl); +} + +vuint16m1_t +test_vpaire_tu (vuint16m1_t merge, vuint16m1_t a, vuint16m1_t b, + size_t vl) +{ + return __riscv_vpaire_vv_u16m1_tu (merge, a, b, vl); +} + +vuint16m1_t +test_vpaire_tum (vbool16_t mask, vuint16m1_t merge, vuint16m1_t a, + vuint16m1_t b, size_t vl) +{ + return __riscv_vpaire_vv_u16m1_tum (mask, merge, a, b, vl); +} + +vuint16m1_t +test_vpaire_tumu (vbool16_t mask, vuint16m1_t merge, vuint16m1_t a, + vuint16m1_t b, size_t vl) +{ + return __riscv_vpaire_vv_u16m1_tumu (mask, merge, a, b, vl); +} + +vuint16m1_t +test_vpaire_mu (vbool16_t mask, vuint16m1_t merge, vuint16m1_t a, + vuint16m1_t b, size_t vl) +{ + return __riscv_vpaire_vv_u16m1_mu (mask, merge, a, b, vl); +} + +vuint16m1_t +test_vpairo_tu (vuint16m1_t merge, vuint16m1_t a, vuint16m1_t b, + size_t vl) +{ + return __riscv_vpairo_vv_u16m1_tu (merge, a, b, vl); +} + +vuint16m1_t +test_vpairo_tum (vbool16_t mask, vuint16m1_t merge, vuint16m1_t a, + vuint16m1_t b, size_t vl) +{ + return __riscv_vpairo_vv_u16m1_tum (mask, merge, a, b, vl); +} + +vuint16m1_t +test_vpairo_tumu (vbool16_t mask, vuint16m1_t merge, vuint16m1_t a, + vuint16m1_t b, size_t vl) +{ + return __riscv_vpairo_vv_u16m1_tumu (mask, merge, a, b, vl); +} + +vuint16m1_t +test_vpairo_mu (vbool16_t mask, vuint16m1_t merge, vuint16m1_t a, + vuint16m1_t b, size_t vl) +{ + return __riscv_vpairo_vv_u16m1_mu (mask, merge, a, b, vl); +} -- 2.43.0
