Hi Karl,
On Thu, Dec 11, 2025 at 01:31:23PM +0000, Karl Meakin wrote:
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-sme.md (@aarch64_mop4_): New insns.
> * config/aarch64/aarch64-sve-builtins-functions.h (class sme_mop4): New
> function base.
> * config/aarch64/aarch64-sve-builtins-sme.cc (svmop4a_za): New
> functions.
> (svmop4s_za): New functions.
> * config/aarch64/aarch64-sve-builtins-sme.h (svmop4a_za): New function
> base.
> (svmop4s_za): New function base.
> * config/aarch64/iterators.md (SVE_FULL_BI): New mode iterator.
> (SVE_FULL_BIx2): Likewise.
> (SVE_FULL_BHIx2): Likewise.
> (SVE_FULL_BHSDF): Likewise.
> (SVE_FULL_BHSDFx2): Likewise.
> (SME_MOP_HSDFx2): Likewise.
> (UNSPEC_SME_FMOP4A): New unspec.
> (UNSPEC_SME_FMOP4S): Likewise.
> (UNSPEC_SME_UMOP4A): Likewise.
> (UNSPEC_SME_UMOP4S): Likewise.
> (UNSPEC_SME_SMOP4A): Likewise.
> (UNSPEC_SME_SMOP4S): Likewise.
> (UNSPEC_SME_SUMOP4A): Likewise.
> (UNSPEC_SME_SUMOP4S): Likewise.
> (UNSPEC_SME_USMOP4A): Likewise.
> (UNSPEC_SME_USMOP4S): Likewise.
> (SME_FP_MOP4): New int iterator.
> (SME_FP8_MOP4): Likewise.
> (SME_INT_MOP4): Likewise.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/aarch64/sme/acle-asm/test_sme_acle.h
> (TEST_UNIFORM_ZA): Add new `fpm_t fpm0` argument.
> (TEST_DUAL_ZA): Likewise.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za16_bf16_bf16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za16_f16_f16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za16_mf8_mf8.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_bf16_bf16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f16_f16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f32_f32.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_mf8_mf8.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s16_s16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_s8.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_u8.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u16_u16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_s8.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_u8.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za64_f64_f64.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_s16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_u16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_s16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_u16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4s_za16_bf16_bf16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4s_za16_f16_f16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4s_za32_bf16_bf16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4s_za32_f16_f16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s16_s16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_s8.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_u8.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u16_u16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_s8.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_u8.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4s_za64_f64_f64.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_s16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_u16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_s16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_u16.c: New test.
> ---
> gcc/config/aarch64/aarch64-sme.md | 173 ++++++++++++++++++
> .../aarch64/aarch64-sve-builtins-functions.h | 46 +++++
> .../aarch64/aarch64-sve-builtins-sme.cc | 6 +
> gcc/config/aarch64/aarch64-sve-builtins-sme.h | 2 +
> gcc/config/aarch64/iterators.md | 50 +++++
> .../aarch64/sme/acle-asm/test_sme_acle.h | 4 +-
> .../sme2/acle-asm/mop4a_za16_bf16_bf16.c | 85 +++++++++
> .../sme2/acle-asm/mop4a_za16_f16_f16.c | 85 +++++++++
> .../sme2/acle-asm/mop4a_za16_mf8_mf8.c | 85 +++++++++
> .../sme2/acle-asm/mop4a_za32_bf16_bf16.c | 85 +++++++++
> .../sme2/acle-asm/mop4a_za32_f16_f16.c | 85 +++++++++
> .../sme2/acle-asm/mop4a_za32_f32_f32.c | 85 +++++++++
> .../sme2/acle-asm/mop4a_za32_mf8_mf8.c | 86 +++++++++
> .../sme2/acle-asm/mop4a_za32_s16_s16.c | 85 +++++++++
> .../aarch64/sme2/acle-asm/mop4a_za32_s8_s8.c | 85 +++++++++
> .../aarch64/sme2/acle-asm/mop4a_za32_s8_u8.c | 85 +++++++++
> .../sme2/acle-asm/mop4a_za32_u16_u16.c | 85 +++++++++
> .../aarch64/sme2/acle-asm/mop4a_za32_u8_s8.c | 85 +++++++++
> .../aarch64/sme2/acle-asm/mop4a_za32_u8_u8.c | 85 +++++++++
> .../sme2/acle-asm/mop4a_za64_f64_f64.c | 85 +++++++++
> .../sme2/acle-asm/mop4a_za64_s16_s16.c | 85 +++++++++
> .../sme2/acle-asm/mop4a_za64_s16_u16.c | 85 +++++++++
> .../sme2/acle-asm/mop4a_za64_u16_s16.c | 85 +++++++++
> .../sme2/acle-asm/mop4a_za64_u16_u16.c | 85 +++++++++
> .../sme2/acle-asm/mop4s_za16_bf16_bf16.c | 85 +++++++++
> .../sme2/acle-asm/mop4s_za16_f16_f16.c | 85 +++++++++
> .../sme2/acle-asm/mop4s_za32_bf16_bf16.c | 85 +++++++++
> .../sme2/acle-asm/mop4s_za32_f16_f16.c | 85 +++++++++
> .../sme2/acle-asm/mop4s_za32_s16_s16.c | 85 +++++++++
> .../aarch64/sme2/acle-asm/mop4s_za32_s8_s8.c | 85 +++++++++
> .../aarch64/sme2/acle-asm/mop4s_za32_s8_u8.c | 85 +++++++++
> .../sme2/acle-asm/mop4s_za32_u16_u16.c | 85 +++++++++
> .../aarch64/sme2/acle-asm/mop4s_za32_u8_s8.c | 85 +++++++++
> .../aarch64/sme2/acle-asm/mop4s_za32_u8_u8.c | 85 +++++++++
> .../sme2/acle-asm/mop4s_za64_f64_f64.c | 85 +++++++++
> .../sme2/acle-asm/mop4s_za64_s16_s16.c | 85 +++++++++
> .../sme2/acle-asm/mop4s_za64_s16_u16.c | 85 +++++++++
> .../sme2/acle-asm/mop4s_za64_u16_s16.c | 85 +++++++++
> .../sme2/acle-asm/mop4s_za64_u16_u16.c | 85 +++++++++
> 39 files changed, 3085 insertions(+), 2 deletions(-)
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_bf16_bf16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_f16_f16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_mf8_mf8.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_bf16_bf16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f16_f16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f32_f32.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_mf8_mf8.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s16_s16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_s8.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_u8.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u16_u16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_s8.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_u8.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_f64_f64.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_s16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_u16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_s16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_u16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za16_bf16_bf16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za16_f16_f16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_bf16_bf16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_f16_f16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s16_s16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_s8.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_u8.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u16_u16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_s8.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_u8.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_f64_f64.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_s16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_u16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_s16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_u16.c
First of all, a general comment: since you're splitting adding intrinsics
and RTL patterns into two patches, you're pretty much guaranteeing that
there's going to be an intermediate version of gcc (after the first
commit, but before the second) that will not compile. Imagine someone
doing a bisect for an unrelated matter and randomly landing between your
two commits; since gcc won't build for them, they will have to abort or
spend effort working around your patches. For this reason, I think you
will have to merge your 4/6 and 6/6 into one; this way, gcc can be built
after each of your individual commits.
>
> diff --git a/gcc/config/aarch64/aarch64-sme.md
> b/gcc/config/aarch64/aarch64-sme.md
> index 632ef1e4774..98a47e8f138 100644
> --- a/gcc/config/aarch64/aarch64-sme.md
> +++ b/gcc/config/aarch64/aarch64-sme.md
> @@ -1795,6 +1795,65 @@ (define_insn
> "@aarch64_sme_<optab><VNx4SI_ONLY:mode><VNx4SI_ONLY:mode>"
> "<optab>\tza%0.s, %1/m, %2/m, %3.s, %4.s"
> )
Please mention these new instructions in the ("[INT] Sum of outer
products") section header, together with the name of the extension that
adds them.
>
> +;; _za32_s16_s16
> +;; _za32_u16_u16
> +;; _za32_s8_s8
> +;; _za32_u8_u8
> +;; _za32_s8_u8
> +;; _za32_u8_s8
> +;; _za64_s16_s16 (only if __ARM_FEATURE_SME_I16I64 != 0)
> +;; _za64_u16_u16 (only if __ARM_FEATURE_SME_I16I64 != 0)
> +;; _za64_s16_u16 (only if __ARM_FEATURE_SME_I16I64 != 0)
> +;; _za64_u16_s16 (only if __ARM_FEATURE_SME_I16I64 != 0)
> +(define_insn
> "@aarch64_mop4_<optab><SME_ZA_SDI:mode><SVE_FULL_BHI:mode><SVE_FULL_BHI:mode>"
> + [(set (reg:SME_ZA_SDI ZA_REGNUM)
> + (unspec:SME_ZA_SDI
> + [(reg:SME_ZA_SDI ZA_REGNUM)
> + (reg:DI SME_STATE_REGNUM)
> + (match_operand:DI 0 "const_int_operand")
> + (match_operand:SVE_FULL_BHI 1 "register_operand" "Ux2")
In this and other files it is customary to use aligned_register_operand
for multi-vector operands; please change this throughout.
> + (match_operand:SVE_FULL_BHI 2 "register_operand" "Uz2")]
> + SME_INT_MOP4))]
> + "TARGET_SME_MOP4"
> + "<optab>\tza%0.<SME_ZA_SDI:Vetype>, %1.<SVE_FULL_BHI:Vetype>,
> %2.<SVE_FULL_BHI:Vetype>"
> +)
So if TARGET_SME_I16I64 holds, then we will also effectively generate
(invalid) _za64_[us]8_[us]8 combinations, right? We need to prevent that.
I would split this pattern into two, according to the mode used to access
ZA. I'm no expert in this area, but it looks like that's how it's done
for the smla/smls stuff (search for SME_INT_TERNARY_SLICE in this file).
> +(define_insn
> "@aarch64_mop4_<optab><SME_ZA_SDI:mode><SVE_FULL_BHI:mode><SVE_FULL_BHIx2:mode>"
> + [(set (reg:SME_ZA_SDI ZA_REGNUM)
> + (unspec:SME_ZA_SDI
> + [(reg:SME_ZA_SDI ZA_REGNUM)
> + (reg:DI SME_STATE_REGNUM)
> + (match_operand:DI 0 "const_int_operand")
> + (match_operand:SVE_FULL_BHI 1 "register_operand" "Ux2")
> + (match_operand:SVE_FULL_BHIx2 2 "register_operand" "Uz2")]
> + SME_INT_MOP4))]
> + "TARGET_SME_MOP4"
> + "<optab>\tza%0.<SME_ZA_SDI:Vetype>, %1.<SVE_FULL_BHI:Vetype>, %2"
> +)
Please add newlines to separate all these new patterns.
> +(define_insn
> "@aarch64_mop4_<optab><SME_ZA_SDI:mode><SVE_FULL_BHIx2:mode><SVE_FULL_BHI:mode>"
> + [(set (reg:SME_ZA_SDI ZA_REGNUM)
> + (unspec:SME_ZA_SDI
> + [(reg:SME_ZA_SDI ZA_REGNUM)
> + (reg:DI SME_STATE_REGNUM)
> + (match_operand:DI 0 "const_int_operand")
> + (match_operand:SVE_FULL_BHIx2 1 "register_operand" "Ux2")
> + (match_operand:SVE_FULL_BHI 2 "register_operand" "Uz2")]
> + SME_INT_MOP4))]
> + "TARGET_SME_MOP4"
> + "<optab>\tza%0.<SME_ZA_SDI:Vetype>, %1, %2.<SVE_FULL_BHI:Vetype>"
> +)
> +(define_insn
> "@aarch64_mop4_<optab><SME_ZA_SDI:mode><SVE_FULL_BHIx2:mode><SVE_FULL_BHIx2:mode>"
> + [(set (reg:SME_ZA_SDI ZA_REGNUM)
> + (unspec:SME_ZA_SDI
> + [(reg:SME_ZA_SDI ZA_REGNUM)
> + (reg:DI SME_STATE_REGNUM)
> + (match_operand:DI 0 "const_int_operand")
> + (match_operand:SVE_FULL_BHIx2 1 "register_operand" "Ux2")
> + (match_operand:SVE_FULL_BHIx2 2 "register_operand" "Uz2")]
> + SME_INT_MOP4))]
> + "TARGET_SME_MOP4"
> + "<optab>\tza%0.<SME_ZA_SDI:Vetype>, %1, %2"
> +)
It should be pretty straightforward to merge these 4 patterns into 1; you
only need to make sure you're handling assembly output correctly.
> +
> ;; -------------------------------------------------------------------------
> ;; ---- [FP] Dot product
> ;; -------------------------------------------------------------------------
> @@ -2137,6 +2196,10 @@ (define_insn
> "*aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx124:mode>"
> ;; - BFMOPS (SME_B16B16)
> ;; - FMOPA
> ;; - FMOPS
> +;; - BFMOP4A (SME_B16B16)
> +;; - BFMOP4S (SME_B16B16)
> +;; - FMOP4A
> +;; - FMOP4S
And SME_MOP4 (/ FP8) for all of these, right?
> ;; -------------------------------------------------------------------------
>
> (define_insn "@aarch64_sme_<optab><mode><mode>"
> @@ -2169,6 +2232,116 @@ (define_insn
> "@aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_HF:mode>"
> "<b><optab>\tza%0.<VNx4SI_ONLY:Vetype>, %1/m, %2/m,
> %3.<SVE_FULL_HF:Vetype>, %4.<SVE_FULL_HF:Vetype>"
> )
>
> +;; _za16_f16_f16 (only if __ARM_FEATURE_SME_F16F16 != 0)
> +;; _za16_bf16_bf16 (only if __ARM_FEATURE_SME_B16B16 != 0)
> +;; _za32_f32_f32
> +;; _za32_f16_f16
> +;; _za32_bf16_bf16
> +;; _za64_f64_f64 (only if __ARM_FEATURE_SME_F64F64 != 0)
> +(define_insn
> "@aarch64_mop4_<optab><SVE_FULL_HSDI:mode><SVE_FULL_BHSDF:mode><SVE_FULL_BHSDF:mode>"
> + [(set (reg:SVE_FULL_HSDI ZA_REGNUM)
> + (unspec:SVE_FULL_HSDI
> + [(reg:SVE_FULL_HSDI ZA_REGNUM)
> + (reg:DI SME_STATE_REGNUM)
> + (match_operand:DI 0 "const_int_operand")
> + (match_operand:SVE_FULL_BHSDF 1 "register_operand" "Ux2")
> + (match_operand:SVE_FULL_BHSDF 2 "register_operand" "Uz2")]
> + SME_FP_MOP4))]
> + "TARGET_SME_MOP4"
> + "<b><optab>\tza%0.<SVE_FULL_HSDI:Vetype>, %1.<SVE_FULL_BHSDF:Vetype>,
> %2.<SVE_FULL_BHSDF:Vetype>"
> +)
Same here, you're generating some invalid mode combinations using plain
SVE_FULL_HSDI, and the conditions are even more tricky. Again it looks
like the solution is to split the pattern into several (3 in this case).
Your goal is to make sure you only handle the 6 valid combinations that
you've listed in the comment above the pattern.
> +(define_insn
> "@aarch64_mop4_<optab><SVE_FULL_HSDI:mode><SVE_FULL_BHSDFx2:mode><SVE_FULL_BHSDFx2:mode>"
> + [(set (reg:SVE_FULL_HSDI ZA_REGNUM)
> + (unspec:SVE_FULL_HSDI
> + [(reg:SVE_FULL_HSDI ZA_REGNUM)
> + (reg:DI SME_STATE_REGNUM)
> + (match_operand:DI 0 "const_int_operand")
> + (match_operand:SVE_FULL_BHSDFx2 1 "register_operand" "Ux2")
> + (match_operand:SVE_FULL_BHSDFx2 2 "register_operand" "Uz2")]
> + SME_FP_MOP4))]
> + "TARGET_SME_MOP4"
> + "<b><optab>\tza%0.<SVE_FULL_HSDI:Vetype>, %1, %2"
> +)
> +(define_insn
> "@aarch64_mop4_<optab><SVE_FULL_HSDI:mode><SVE_FULL_BHSDFx2:mode><SVE_FULL_BHSDF:mode>"
> + [(set (reg:SVE_FULL_HSDI ZA_REGNUM)
> + (unspec:SVE_FULL_HSDI
> + [(reg:SVE_FULL_HSDI ZA_REGNUM)
> + (reg:DI SME_STATE_REGNUM)
> + (match_operand:DI 0 "const_int_operand")
> + (match_operand:SVE_FULL_BHSDFx2 1 "register_operand" "Ux2")
> + (match_operand:SVE_FULL_BHSDF 2 "register_operand" "Uz2")]
> + SME_FP_MOP4))]
> + "TARGET_SME_MOP4"
> + "<SVE_FULL_BHSDFx2:b><optab>\tza%0.<SVE_FULL_HSDI:Vetype>, %1,
> %2.<SVE_FULL_BHSDF:Vetype>"
> +)
> +(define_insn
> "@aarch64_mop4_<optab><SVE_FULL_HSDI:mode><SVE_FULL_BHSDF:mode><SVE_FULL_BHSDFx2:mode>"
> + [(set (reg:SVE_FULL_HSDI ZA_REGNUM)
> + (unspec:SVE_FULL_HSDI
> + [(reg:SVE_FULL_HSDI ZA_REGNUM)
> + (reg:DI SME_STATE_REGNUM)
> + (match_operand:DI 0 "const_int_operand")
> + (match_operand:SVE_FULL_BHSDF 1 "register_operand" "Ux2")
> + (match_operand:SVE_FULL_BHSDFx2 2 "register_operand" "Uz2")]
> + SME_FP_MOP4))]
> + "TARGET_SME_MOP4"
> + "<SVE_FULL_BHSDFx2:b><optab>\tza%0.<SVE_FULL_HSDI:Vetype>,
> %1.<SVE_FULL_BHSDF:Vetype>, %2"
> +)
Same argument about merging 4 patterns into one ...
> +
> +;; _za16_mf8_mf8_fpm (only if __ARM_FEATURE_SME_F8F16 != 0)
> +;; _za32_mf8_mf8_fpm (only if __ARM_FEATURE_SME_F8F32 != 0)
> +(define_insn
> "@aarch64_mop4_<optab><SME_ZA_MF8:mode><SVE_FULL_BI:mode><SVE_FULL_BI:mode>"
> + [(set (reg:SME_ZA_MF8 ZA_REGNUM)
> + (unspec:SME_ZA_MF8
> + [(reg:SME_ZA_MF8 ZA_REGNUM)
> + (reg:DI SME_STATE_REGNUM)
> + (match_operand:DI 0 "const_int_operand")
> + (match_operand:SVE_FULL_BI 1 "register_operand" "Ux2")
> + (match_operand:SVE_FULL_BI 2 "register_operand" "Uz2")
> + (reg:DI FPM_REGNUM)]
> + SME_FP8_MOP4))]
> + "TARGET_SME_MOP4"
> + "<optab>\tza%0.<SME_ZA_MF8:Vetype>, %1.b, %2.b"
> +)
> +(define_insn
> "@aarch64_mop4_<optab><SME_ZA_MF8:mode><SVE_FULL_BI:mode><SVE_FULL_BIx2:mode>"
> + [(set (reg:SME_ZA_MF8 ZA_REGNUM)
> + (unspec:SME_ZA_MF8
> + [(reg:SME_ZA_MF8 ZA_REGNUM)
> + (reg:DI SME_STATE_REGNUM)
> + (match_operand:DI 0 "const_int_operand")
> + (match_operand:SVE_FULL_BI 1 "register_operand" "Ux2")
> + (match_operand:SVE_FULL_BIx2 2 "register_operand" "Uz2")
> + (reg:DI FPM_REGNUM)]
> + SME_FP8_MOP4))]
> + "TARGET_SME_MOP4"
> + "<optab>\tza%0.<SME_ZA_MF8:Vetype>, %1.b, %2"
> +)
> +(define_insn
> "@aarch64_mop4_<optab><SME_ZA_MF8:mode><SVE_FULL_BIx2:mode><SVE_FULL_BI:mode>"
> + [(set (reg:SME_ZA_MF8 ZA_REGNUM)
> + (unspec:SME_ZA_MF8
> + [(reg:SME_ZA_MF8 ZA_REGNUM)
> + (reg:DI SME_STATE_REGNUM)
> + (match_operand:DI 0 "const_int_operand")
> + (match_operand:SVE_FULL_BIx2 1 "register_operand" "Ux2")
> + (match_operand:SVE_FULL_BI 2 "register_operand" "Uz2")
> + (reg:DI FPM_REGNUM)]
> + SME_FP8_MOP4))]
> + "TARGET_SME_MOP4"
> + "<optab>\tza%0.<SME_ZA_MF8:Vetype>, %1, %2.b"
> +)
> +(define_insn
> "@aarch64_mop4_<optab><SME_ZA_MF8:mode><SVE_FULL_BIx2:mode><SVE_FULL_BIx2:mode>"
> + [(set (reg:SME_ZA_MF8 ZA_REGNUM)
> + (unspec:SME_ZA_MF8
> + [(reg:SME_ZA_MF8 ZA_REGNUM)
> + (reg:DI SME_STATE_REGNUM)
> + (match_operand:DI 0 "const_int_operand")
> + (match_operand:SVE_FULL_BIx2 1 "register_operand" "Ux2")
> + (match_operand:SVE_FULL_BIx2 2 "register_operand" "Uz2")
> + (reg:DI FPM_REGNUM)]
> + SME_FP8_MOP4))]
> + "TARGET_SME_MOP4"
> + "<optab>\tza%0.<SME_ZA_MF8:Vetype>, %1, %2"
> +)
... and here, too.
> +
> ;; =========================================================================
> ;; == Table lookup
> ;; =========================================================================
> diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
> b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
> index c05946d4ec7..cee724588e9 100644
> --- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
> +++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
> @@ -482,6 +482,52 @@ public:
> }
> };
>
> +class sme_mop4 : public read_write_za<unspec_based_function_base>
> +{
> +private:
> + int m_unspec_for_suint;
> + int m_unspec_for_usint;
> +
> +public:
> + using parent = read_write_za<unspec_based_function_base>;
> +
> + constexpr sme_mop4 (int unspec_for_sint, int unspec_for_uint,
> + int unspec_for_fp, int unspec_for_suint,
> + int unspec_for_usint)
> + : parent (unspec_for_sint, unspec_for_uint,
> + unspec_for_fp, unspec_for_fp, 1),
> + m_unspec_for_suint (unspec_for_suint),
> + m_unspec_for_usint (unspec_for_usint)
> + {}
> +
> + rtx expand (function_expander &e) const override
> + {
> + machine_mode za_mode = e.vector_mode (0);
> + machine_mode v1_mode = e.tuple_mode (1);
> + machine_mode v2_mode = e.tuple_mode (1);
> +
> + if (e.mode_suffix_id == MODE_2x1)
> + v1_mode = targetm.array_mode (v1_mode, 2).require ();
> +
> + if (e.mode_suffix_id == MODE_1x2)
> + v2_mode = targetm.array_mode (v2_mode, 2).require ();
> +
> + if (e.mode_suffix_id == MODE_2x2)
> + {
> + v1_mode = targetm.array_mode (v1_mode, 2).require ();
> + v2_mode = targetm.array_mode (v2_mode, 2).require ();
> + }
Can you use a switch statement here? Or at the very least a series of
"else if"s rather than just "if"s.
> +
> + int unspec = (e.type_suffix (1).unsigned_p == e.type_suffix
> (2).unsigned_p)
> + ? unspec_for (e)
> + : (e.type_suffix (1).unsigned_p ? m_unspec_for_usint
> + : m_unspec_for_suint);
> +
> + insn_code icode = code_for_aarch64_mop4 (unspec, za_mode, v1_mode,
> v2_mode);
> + return e.use_exact_insn (icode);
> + }
> +};
> +
> using sme_2mode_function
> = sme_2mode_function_t<code_for_aarch64_sme, code_for_aarch64_sme_single>;
>
> diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
> b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
> index 4657e29ad64..627bfe80857 100644
> --- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
> +++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
> @@ -688,6 +688,12 @@ FUNCTION (svwrite_hor_za, svwrite_za_tile_impl,
> (UNSPEC_SME_WRITE_HOR))
> FUNCTION (svwrite_ver_za, svwrite_za_tile_impl, (UNSPEC_SME_WRITE_VER))
> FUNCTION (svwrite_zt, svwrite_zt_impl,)
> FUNCTION (svwrite_lane_zt, svwrite_lane_zt_impl,)
> +FUNCTION (svmop4a_za, sme_mop4,
> + (UNSPEC_SME_SMOP4A, UNSPEC_SME_UMOP4A, UNSPEC_SME_FMOP4A,
> + UNSPEC_SME_SUMOP4A, UNSPEC_SME_USMOP4A))
> +FUNCTION (svmop4s_za, sme_mop4,
> + (UNSPEC_SME_SMOP4S, UNSPEC_SME_UMOP4S, UNSPEC_SME_FMOP4S,
> + UNSPEC_SME_SUMOP4S, UNSPEC_SME_USMOP4S))
Please keep this in alphabetical order.
> FUNCTION (svzero_mask_za, svzero_mask_za_impl, )
> FUNCTION (svzero_za, svzero_za_impl, )
> FUNCTION (svzero_zt, svzero_zt_impl, )
> diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.h
> b/gcc/config/aarch64/aarch64-sve-builtins-sme.h
> index 4968f65442b..fd935086204 100644
> --- a/gcc/config/aarch64/aarch64-sve-builtins-sme.h
> +++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.h
> @@ -77,6 +77,8 @@ namespace aarch64_sve
> extern const function_base *const svwrite_hor_za;
> extern const function_base *const svwrite_ver_za;
> extern const function_base *const svwrite_zt;
> + extern const function_base *const svmop4a_za;
> + extern const function_base *const svmop4s_za;
Same here.
> extern const function_base *const svwrite_lane_zt;
> extern const function_base *const svundef_za;
> extern const function_base *const svvdot_lane_za;
> diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
> index ff5688529d3..8f1ef74e91a 100644
> --- a/gcc/config/aarch64/iterators.md
> +++ b/gcc/config/aarch64/iterators.md
> @@ -514,9 +514,18 @@ (define_mode_iterator SVE_CLAMP_F [(VNx8BF
> "TARGET_SSVE_B16B16")
> (VNx4SF "TARGET_SVE2p1_OR_SME2")
> (VNx2DF "TARGET_SVE2p1_OR_SME2")])
>
> +;; Fully-packed SVE integer vector modes that have 8-bit elements.
> +(define_mode_iterator SVE_FULL_BI [VNx16QI])
> +
> +;; Pairs of the above.
> +(define_mode_iterator SVE_FULL_BIx2 [VNx32QI])
> +
> ;; Fully-packed SVE integer vector modes that have 8-bit or 16-bit elements.
> (define_mode_iterator SVE_FULL_BHI [VNx16QI VNx8HI])
>
> +;; Fully-packed SVE integer vector modes that have 8-bit or 16-bit elements.
> +(define_mode_iterator SVE_FULL_BHIx2 [VNx32QI VNx16HI])
> +
> ;; Fully-packed SVE integer vector modes that have 8-bit, 16-bit or 32-bit
> ;; elements.
> (define_mode_iterator SVE_FULL_BHSI [VNx16QI VNx8HI VNx4SI])
> @@ -590,6 +599,12 @@ (define_mode_iterator SVE_MATMULF [(VNx4SF
> "TARGET_SVE_F32MM")
> ;; SVE floating-point vector modes that have 32-bit or 64-bit elements.
> (define_mode_iterator SVE_SDF [VNx2SF SVE_FULL_SDF])
>
> +;; f16, bf16, f32, f64
> +(define_mode_iterator SVE_FULL_BHSDF [VNx8BF VNx8HF VNx4SF VNx2DF])
> +
> +;; f16x2, bf16x2, f32x2, f64x2
> +(define_mode_iterator SVE_FULL_BHSDFx2 [VNx16BF VNx16HF VNx8SF VNx4DF])
> +
> ;; Fully-packed SVE vector modes that have 32-bit or smaller elements.
> (define_mode_iterator SVE_FULL_BHS [VNx16QI VNx8HI VNx4SI
> VNx8BF VNx8HF VNx4SF])
> @@ -743,6 +758,9 @@ (define_mode_iterator SVE_SFx24 [VNx8SF VNx16SF])
> (define_mode_iterator SME_ZA_I [VNx16QI VNx8HI VNx4SI VNx2DI VNx1TI])
> (define_mode_iterator SME_ZA_SDI [VNx4SI (VNx2DI "TARGET_SME_I16I64")])
>
> +(define_mode_iterator SME_ZA_MF8 [(VNx8HI "TARGET_SME_F8F16")
> + (VNx4SI "TARGET_SME_F8F32")])
> +
> (define_mode_iterator SME_ZA_BIx24 [VNx32QI VNx64QI])
>
> (define_mode_iterator SME_ZA_BHIx124 [VNx16QI VNx32QI VNx64QI
> @@ -777,6 +795,11 @@ (define_mode_iterator SME_MOP_HSDF [VNx4SF
> (VNx8HF "TARGET_STREAMING_SME_F16F16")
> (VNx8BF "TARGET_STREAMING_SME_B16B16")])
>
> +(define_mode_iterator SME_MOP_HSDFx2 [VNx8SF
> + (VNx4DF "TARGET_SME_F64F64")
> + (VNx16HF "TARGET_STREAMING_SME_F16F16")
> + (VNx16BF "TARGET_STREAMING_SME_B16B16")])
AFAICT this isn't used anywhere and should be removed.
> +
> ;; ------------------------------------------------------------------
> ;; Unspec enumerations for Advance SIMD. These could well go into
> ;; aarch64.md but for their use in int_iterators here.
> @@ -1260,6 +1283,16 @@ (define_c_enum "unspec"
> UNSPEC_SME_FMLS
> UNSPEC_SME_FMOPA
> UNSPEC_SME_FMOPS
> + UNSPEC_SME_FMOP4A
> + UNSPEC_SME_FMOP4S
> + UNSPEC_SME_UMOP4A
> + UNSPEC_SME_UMOP4S
> + UNSPEC_SME_SMOP4A
> + UNSPEC_SME_SMOP4S
> + UNSPEC_SME_SUMOP4A
> + UNSPEC_SME_SUMOP4S
> + UNSPEC_SME_USMOP4A
> + UNSPEC_SME_USMOP4S
> UNSPEC_SME_FSUB
> UNSPEC_SME_LD1_HOR
> UNSPEC_SME_LD1_VER
> @@ -3977,6 +4010,13 @@ (define_int_iterator SME2_INT_MOP [UNSPEC_SME_SMOPA
> UNSPEC_SME_SMOPS
>
> (define_int_iterator SME_FP_MOP [UNSPEC_SME_FMOPA UNSPEC_SME_FMOPS])
>
> +(define_int_iterator SME_FP_MOP4 [UNSPEC_SME_FMOP4A UNSPEC_SME_FMOP4S])
> +(define_int_iterator SME_FP8_MOP4 [UNSPEC_SME_FMOP4A])
> +(define_int_iterator SME_INT_MOP4 [UNSPEC_SME_UMOP4A UNSPEC_SME_UMOP4S
> + UNSPEC_SME_SMOP4A UNSPEC_SME_SMOP4S
> + UNSPEC_SME_SUMOP4A UNSPEC_SME_SUMOP4S
> + UNSPEC_SME_USMOP4A UNSPEC_SME_USMOP4S])
> +
> (define_int_iterator SME2_BMOP [UNSPEC_SME_BMOPA UNSPEC_SME_BMOPS])
>
> (define_int_iterator SME_BINARY_SLICE_SDI [UNSPEC_SME_ADD UNSPEC_SME_SUB])
> @@ -4153,6 +4193,16 @@ (define_int_attr optab [(UNSPEC_ANDF "and")
> (UNSPEC_SME_FMLS "fmls")
> (UNSPEC_SME_FMOPA "fmopa")
> (UNSPEC_SME_FMOPS "fmops")
> + (UNSPEC_SME_FMOP4A "fmop4a")
> + (UNSPEC_SME_FMOP4S "fmop4s")
> + (UNSPEC_SME_UMOP4A "umop4a")
> + (UNSPEC_SME_UMOP4S "umop4s")
> + (UNSPEC_SME_SMOP4A "smop4a")
> + (UNSPEC_SME_SMOP4S "smop4s")
> + (UNSPEC_SME_SUMOP4A "sumop4a")
> + (UNSPEC_SME_SUMOP4S "sumop4s")
> + (UNSPEC_SME_USMOP4A "usmop4a")
> + (UNSPEC_SME_USMOP4S "usmop4s")
Before the patch, this was alphabetized as well.
> (UNSPEC_SME_FSUB "fsub")
> (UNSPEC_SME_LD1_HOR "ld1_hor")
> (UNSPEC_SME_LD1_VER "ld1_ver")
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h
> b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h
> index aaadab2f773..df7c3a5d6fa 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h
> +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h
> @@ -46,7 +46,7 @@
>
> #define TEST_UNIFORM_ZA(NAME, TYPE, CODE1, CODE2) \
> PROTO (NAME, void, (TYPE z0, TYPE z1, svbool_t p0, \
> - svbool_t p1)) \
> + svbool_t p1, fpm_t fpm0)) \
> { \
> INVOKE (CODE1, CODE2); \
> }
> @@ -54,7 +54,7 @@
> #define TEST_DUAL_ZA(NAME, TYPE1, TYPE2, CODE1, CODE2) \
> PROTO (NAME, void, (TYPE1 z0, TYPE1 z1, TYPE1 z2, TYPE1 z3, \
> TYPE2 z4, TYPE2 z5, TYPE2 z6, TYPE2 z7, \
> - svbool_t p0, svbool_t p1)) \
> + svbool_t p0, svbool_t p1, fpm_t fpm0)) \
> { \
> INVOKE (CODE1, CODE2); \
> }
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_bf16_bf16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_bf16_bf16.c
> new file mode 100644
> index 00000000000..92f66b3c5ae
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_bf16_bf16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
Here and in the rest of the asm tests, please add the usual
/* { dg-do assemble { target aarch64_asm_sme-mop4_ok } } */
/* { dg-do compile { target { ! aarch64_asm_sme-mop4_ok } } } */
header for maximum coverage. Thereafter, I would encourage you to re-run
all of them with a known up-to-date version of gas to see what shakes out.
Thanks,
Artemiy
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-b16b16"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za16_bf16_bf16_0:
> +** ...
> +** bfmop4a za0\.h, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za16_bf16_bf16_0, svbfloat16_t,
> + svmop4a_1x1_za16_bf16_bf16 (0, z0, z1),
> + svmop4a_za16 (0, z0, z1));
> +
> +/*
> +** mop4a_1x1_za16_bf16_bf16_1:
> +** ...
> +** bfmop4a za1\.h, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za16_bf16_bf16_1, svbfloat16_t,
> + svmop4a_1x1_za16_bf16_bf16 (1, z0, z1),
> + svmop4a_za16 (1, z0, z1));
> +
> +/*
> +** mop4a_1x2_za16_bf16_bf16_0:
> +** ...
> +** bfmop4a za0\.h, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za16_bf16_bf16_0, svbfloat16_t, svbfloat16x2_t,
> + svmop4a_1x2_za16_bf16_bf16 (0, z0, z4),
> + svmop4a_za16 (0, z0, z4));
> +
> +/*
> +** mop4a_1x2_za16_bf16_bf16_1:
> +** ...
> +** bfmop4a za1\.h, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za16_bf16_bf16_1, svbfloat16_t, svbfloat16x2_t,
> + svmop4a_1x2_za16_bf16_bf16 (1, z0, z4),
> + svmop4a_za16 (1, z0, z4));
> +
> +/*
> +** mop4a_2x1_za16_bf16_bf16_0:
> +** ...
> +** bfmop4a za0\.h, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za16_bf16_bf16_0, svbfloat16x2_t, svbfloat16_t,
> + svmop4a_2x1_za16_bf16_bf16 (0, z0, z4),
> + svmop4a_za16 (0, z0, z4));
> +
> +/*
> +** mop4a_2x1_za16_bf16_bf16_1:
> +** ...
> +** bfmop4a za1\.h, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za16_bf16_bf16_1, svbfloat16x2_t, svbfloat16_t,
> + svmop4a_2x1_za16_bf16_bf16 (1, z0, z4),
> + svmop4a_za16 (1, z0, z4));
> +
> +/*
> +** mop4a_2x2_za16_bf16_bf16_0:
> +** ...
> +** bfmop4a za0\.h, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za16_bf16_bf16_0, svbfloat16x2_t,
> + svmop4a_2x2_za16_bf16_bf16 (0, z0, z1),
> + svmop4a_za16 (0, z0, z1));
> +
> +/*
> +** mop4a_2x2_za16_bf16_bf16_1:
> +** ...
> +** bfmop4a za1\.h, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za16_bf16_bf16_1, svbfloat16x2_t,
> + svmop4a_2x2_za16_bf16_bf16 (1, z0, z1),
> + svmop4a_za16 (1, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_f16_f16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_f16_f16.c
> new file mode 100644
> index 00000000000..d6bddc8d842
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_f16_f16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-f16f16"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za16_f16_f16_0:
> +** ...
> +** fmop4a za0\.h, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za16_f16_f16_0, svfloat16_t,
> + svmop4a_1x1_za16_f16_f16 (0, z0, z1),
> + svmop4a_za16 (0, z0, z1));
> +
> +/*
> +** mop4a_1x1_za16_f16_f16_1:
> +** ...
> +** fmop4a za1\.h, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za16_f16_f16_1, svfloat16_t,
> + svmop4a_1x1_za16_f16_f16 (1, z0, z1),
> + svmop4a_za16 (1, z0, z1));
> +
> +/*
> +** mop4a_1x2_za16_f16_f16_0:
> +** ...
> +** fmop4a za0\.h, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za16_f16_f16_0, svfloat16_t, svfloat16x2_t,
> + svmop4a_1x2_za16_f16_f16 (0, z0, z4),
> + svmop4a_za16 (0, z0, z4));
> +
> +/*
> +** mop4a_1x2_za16_f16_f16_1:
> +** ...
> +** fmop4a za1\.h, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za16_f16_f16_1, svfloat16_t, svfloat16x2_t,
> + svmop4a_1x2_za16_f16_f16 (1, z0, z4),
> + svmop4a_za16 (1, z0, z4));
> +
> +/*
> +** mop4a_2x1_za16_f16_f16_0:
> +** ...
> +** fmop4a za0\.h, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za16_f16_f16_0, svfloat16x2_t, svfloat16_t,
> + svmop4a_2x1_za16_f16_f16 (0, z0, z4),
> + svmop4a_za16 (0, z0, z4));
> +
> +/*
> +** mop4a_2x1_za16_f16_f16_1:
> +** ...
> +** fmop4a za1\.h, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za16_f16_f16_1, svfloat16x2_t, svfloat16_t,
> + svmop4a_2x1_za16_f16_f16 (1, z0, z4),
> + svmop4a_za16 (1, z0, z4));
> +
> +/*
> +** mop4a_2x2_za16_f16_f16_0:
> +** ...
> +** fmop4a za0\.h, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za16_f16_f16_0, svfloat16x2_t,
> + svmop4a_2x2_za16_f16_f16 (0, z0, z1),
> + svmop4a_za16 (0, z0, z1));
> +
> +/*
> +** mop4a_2x2_za16_f16_f16_1:
> +** ...
> +** fmop4a za1\.h, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za16_f16_f16_1, svfloat16x2_t,
> + svmop4a_2x2_za16_f16_f16 (1, z0, z1),
> + svmop4a_za16 (1, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_mf8_mf8.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_mf8_mf8.c
> new file mode 100644
> index 00000000000..9f838e25fd1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za16_mf8_mf8.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-f8f16"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za16_mf8_mf8_0:
> +** ...
> +** fmop4a za0\.h, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za16_mf8_mf8_0, svmfloat8_t,
> + svmop4a_1x1_za16_mf8_mf8_fpm (0, z0, z1, fpm0),
> + svmop4a_za16_fpm (0, z0, z1, fpm0));
> +
> +/*
> +** mop4a_1x1_za16_mf8_mf8_1:
> +** ...
> +** fmop4a za1\.h, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za16_mf8_mf8_1, svmfloat8_t,
> + svmop4a_1x1_za16_mf8_mf8_fpm (1, z0, z1, fpm0),
> + svmop4a_za16_fpm (1, z0, z1, fpm0));
> +
> +/*
> +** mop4a_1x2_za16_mf8_mf8_0:
> +** ...
> +** fmop4a za0\.h, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za16_mf8_mf8_0, svmfloat8_t, svmfloat8x2_t,
> + svmop4a_1x2_za16_mf8_mf8_fpm (0, z0, z4, fpm0),
> + svmop4a_za16_fpm (0, z0, z4, fpm0));
> +
> +/*
> +** mop4a_1x2_za16_mf8_mf8_1:
> +** ...
> +** fmop4a za1\.h, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za16_mf8_mf8_1, svmfloat8_t, svmfloat8x2_t,
> + svmop4a_1x2_za16_mf8_mf8_fpm (1, z0, z4, fpm0),
> + svmop4a_za16_fpm (1, z0, z4, fpm0));
> +
> +/*
> +** mop4a_2x1_za16_mf8_mf8_0:
> +** ...
> +** fmop4a za0\.h, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za16_mf8_mf8_0, svmfloat8x2_t, svmfloat8_t,
> + svmop4a_2x1_za16_mf8_mf8_fpm (0, z0, z4, fpm0),
> + svmop4a_za16_fpm (0, z0, z4, fpm0));
> +
> +/*
> +** mop4a_2x1_za16_mf8_mf8_1:
> +** ...
> +** fmop4a za1\.h, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za16_mf8_mf8_1, svmfloat8x2_t, svmfloat8_t,
> + svmop4a_2x1_za16_mf8_mf8_fpm (1, z0, z4, fpm0),
> + svmop4a_za16_fpm (1, z0, z4, fpm0));
> +
> +/*
> +** mop4a_2x2_za16_mf8_mf8_0:
> +** ...
> +** fmop4a za0\.h, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za16_mf8_mf8_0, svmfloat8x2_t,
> + svmop4a_2x2_za16_mf8_mf8_fpm (0, z0, z1, fpm0),
> + svmop4a_za16_fpm (0, z0, z1, fpm0));
> +
> +/*
> +** mop4a_2x2_za16_mf8_mf8_1:
> +** ...
> +** fmop4a za1\.h, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za16_mf8_mf8_1, svmfloat8x2_t,
> + svmop4a_2x2_za16_mf8_mf8_fpm (1, z0, z1, fpm0),
> + svmop4a_za16_fpm (1, z0, z1, fpm0));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_bf16_bf16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_bf16_bf16.c
> new file mode 100644
> index 00000000000..a632bd7eae1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_bf16_bf16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-b16b16"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za32_bf16_bf16_0:
> +** ...
> +** bfmop4a za0\.s, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za32_bf16_bf16_0, svbfloat16_t,
> + svmop4a_1x1_za32_bf16_bf16 (0, z0, z1),
> + svmop4a_za32 (0, z0, z1));
> +
> +/*
> +** mop4a_1x1_za32_bf16_bf16_3:
> +** ...
> +** bfmop4a za3\.s, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za32_bf16_bf16_3, svbfloat16_t,
> + svmop4a_1x1_za32_bf16_bf16 (3, z0, z1),
> + svmop4a_za32 (3, z0, z1));
> +
> +/*
> +** mop4a_1x2_za32_bf16_bf16_0:
> +** ...
> +** bfmop4a za0\.s, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_bf16_bf16_0, svbfloat16_t, svbfloat16x2_t,
> + svmop4a_1x2_za32_bf16_bf16 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_1x2_za32_bf16_bf16_3:
> +** ...
> +** bfmop4a za3\.s, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_bf16_bf16_3, svbfloat16_t, svbfloat16x2_t,
> + svmop4a_1x2_za32_bf16_bf16 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_bf16_bf16_0:
> +** ...
> +** bfmop4a za0\.s, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_bf16_bf16_0, svbfloat16x2_t, svbfloat16_t,
> + svmop4a_2x1_za32_bf16_bf16 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_bf16_bf16_3:
> +** ...
> +** bfmop4a za3\.s, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_bf16_bf16_3, svbfloat16x2_t, svbfloat16_t,
> + svmop4a_2x1_za32_bf16_bf16 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x2_za32_bf16_bf16_0:
> +** ...
> +** bfmop4a za0\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za32_bf16_bf16_0, svbfloat16x2_t,
> + svmop4a_2x2_za32_bf16_bf16 (0, z0, z1),
> + svmop4a_za32 (0, z0, z1));
> +
> +/*
> +** mop4a_2x2_za32_bf16_bf16_3:
> +** ...
> +** bfmop4a za3\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za32_bf16_bf16_3, svbfloat16x2_t,
> + svmop4a_2x2_za32_bf16_bf16 (3, z0, z1),
> + svmop4a_za32 (3, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f16_f16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f16_f16.c
> new file mode 100644
> index 00000000000..bf5300243bb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f16_f16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-f16f16"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za32_f16_f16_0:
> +** ...
> +** fmop4a za0\.s, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za32_f16_f16_0, svfloat16_t,
> + svmop4a_1x1_za32_f16_f16 (0, z0, z1),
> + svmop4a_za32 (0, z0, z1));
> +
> +/*
> +** mop4a_1x1_za32_f16_f16_3:
> +** ...
> +** fmop4a za3\.s, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za32_f16_f16_3, svfloat16_t,
> + svmop4a_1x1_za32_f16_f16 (3, z0, z1),
> + svmop4a_za32 (3, z0, z1));
> +
> +/*
> +** mop4a_1x2_za32_f16_f16_0:
> +** ...
> +** fmop4a za0\.s, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_f16_f16_0, svfloat16_t, svfloat16x2_t,
> + svmop4a_1x2_za32_f16_f16 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_1x2_za32_f16_f16_3:
> +** ...
> +** fmop4a za3\.s, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_f16_f16_3, svfloat16_t, svfloat16x2_t,
> + svmop4a_1x2_za32_f16_f16 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_f16_f16_0:
> +** ...
> +** fmop4a za0\.s, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_f16_f16_0, svfloat16x2_t, svfloat16_t,
> + svmop4a_2x1_za32_f16_f16 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_f16_f16_3:
> +** ...
> +** fmop4a za3\.s, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_f16_f16_3, svfloat16x2_t, svfloat16_t,
> + svmop4a_2x1_za32_f16_f16 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x2_za32_f16_f16_0:
> +** ...
> +** fmop4a za0\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za32_f16_f16_0, svfloat16x2_t,
> + svmop4a_2x2_za32_f16_f16 (0, z0, z1),
> + svmop4a_za32 (0, z0, z1));
> +
> +/*
> +** mop4a_2x2_za32_f16_f16_3:
> +** ...
> +** fmop4a za3\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za32_f16_f16_3, svfloat16x2_t,
> + svmop4a_2x2_za32_f16_f16 (3, z0, z1),
> + svmop4a_za32 (3, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f32_f32.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f32_f32.c
> new file mode 100644
> index 00000000000..6d422721e68
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_f32_f32.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za32_f32_f32_0:
> +** ...
> +** fmop4a za0\.s, z0\.s, z30\.s
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za32_f32_f32_0, svfloat32_t,
> + svmop4a_1x1_za32_f32_f32 (0, z0, z1),
> + svmop4a_za32 (0, z0, z1));
> +
> +/*
> +** mop4a_1x1_za32_f32_f32_3:
> +** ...
> +** fmop4a za3\.s, z0\.s, z30\.s
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za32_f32_f32_3, svfloat32_t,
> + svmop4a_1x1_za32_f32_f32 (3, z0, z1),
> + svmop4a_za32 (3, z0, z1));
> +
> +/*
> +** mop4a_1x2_za32_f32_f32_0:
> +** ...
> +** fmop4a za0\.s, z0\.s, {z30\.s - z31\.s}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_f32_f32_0, svfloat32_t, svfloat32x2_t,
> + svmop4a_1x2_za32_f32_f32 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_1x2_za32_f32_f32_3:
> +** ...
> +** fmop4a za3\.s, z0\.s, {z30\.s - z31\.s}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_f32_f32_3, svfloat32_t, svfloat32x2_t,
> + svmop4a_1x2_za32_f32_f32 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_f32_f32_0:
> +** ...
> +** fmop4a za0\.s, {z0\.s - z1\.s}, z30\.s
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_f32_f32_0, svfloat32x2_t, svfloat32_t,
> + svmop4a_2x1_za32_f32_f32 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_f32_f32_3:
> +** ...
> +** fmop4a za3\.s, {z0\.s - z1\.s}, z30\.s
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_f32_f32_3, svfloat32x2_t, svfloat32_t,
> + svmop4a_2x1_za32_f32_f32 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x2_za32_f32_f32_0:
> +** ...
> +** fmop4a za0\.s, {z0\.s - z1\.s}, {z30\.s - z31\.s}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za32_f32_f32_0, svfloat32x2_t,
> + svmop4a_2x2_za32_f32_f32 (0, z0, z1),
> + svmop4a_za32 (0, z0, z1));
> +
> +/*
> +** mop4a_2x2_za32_f32_f32_3:
> +** ...
> +** fmop4a za3\.s, {z0\.s - z1\.s}, {z30\.s - z31\.s}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za32_f32_f32_3, svfloat32x2_t,
> + svmop4a_2x2_za32_f32_f32 (3, z0, z1),
> + svmop4a_za32 (3, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_mf8_mf8.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_mf8_mf8.c
> new file mode 100644
> index 00000000000..c2d0e2cbd65
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_mf8_mf8.c
> @@ -0,0 +1,86 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-f8f32"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za32_mf8_mf8_0:
> +** ...
> +** fmop4a za0\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za32_mf8_mf8_0, svmfloat8_t,
> + svmop4a_1x1_za32_mf8_mf8_fpm (0, z0, z1, fpm0),
> + svmop4a_za32_fpm (0, z0, z1, fpm0));
> +
> +/*
> +** mop4a_1x1_za32_mf8_mf8_3:
> +** ...
> +** fmop4a za3\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za32_mf8_mf8_3, svmfloat8_t,
> + svmop4a_1x1_za32_mf8_mf8_fpm (3, z0, z1, fpm0),
> + svmop4a_za32_fpm (3, z0, z1, fpm0));
> +
> +/*
> +** mop4a_1x2_za32_mf8_mf8_0:
> +** ...
> +** fmop4a za0\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_mf8_mf8_0, svmfloat8_t, svmfloat8x2_t,
> + svmop4a_1x2_za32_mf8_mf8_fpm (0, z0, z4, fpm0),
> + svmop4a_za32_fpm (0, z0, z4, fpm0));
> +
> +/*
> +** mop4a_1x2_za32_mf8_mf8_3:
> +** ...
> +** fmop4a za3\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_mf8_mf8_3, svmfloat8_t, svmfloat8x2_t,
> + svmop4a_1x2_za32_mf8_mf8_fpm (3, z0, z4, fpm0),
> + svmop4a_za32_fpm (3, z0, z4, fpm0));
> +
> +/*
> +** mop4a_2x1_za32_mf8_mf8_0:
> +** ...
> +** fmop4a za0\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_mf8_mf8_0, svmfloat8x2_t, svmfloat8_t,
> + svmop4a_2x1_za32_mf8_mf8_fpm (0, z0, z4, fpm0),
> + svmop4a_za32_fpm (0, z0, z4, fpm0));
> +
> +/*
> +** mop4a_2x1_za32_mf8_mf8_3:
> +** ...
> +** fmop4a za3\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_mf8_mf8_3, svmfloat8x2_t, svmfloat8_t,
> + svmop4a_2x1_za32_mf8_mf8_fpm (3, z0, z4, fpm0),
> + svmop4a_za32_fpm (3, z0, z4, fpm0));
> +
> +/*
> +** mop4a_2x2_za32_mf8_mf8_0:
> +** ...
> +** fmop4a za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za32_mf8_mf8_0, svmfloat8x2_t,
> + svmop4a_2x2_za32_mf8_mf8_fpm (0, z0, z1, fpm0),
> + svmop4a_za32_fpm (0, z0, z1, fpm0));
> +
> +/*
> +** mop4a_2x2_za32_mf8_mf8_3:
> +** ...
> +** fmop4a za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za32_mf8_mf8_3, svmfloat8x2_t,
> + svmop4a_2x2_za32_mf8_mf8_fpm (3, z0, z1, fpm0),
> + svmop4a_za32_fpm (3, z0, z1, fpm0));
> +
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s16_s16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s16_s16.c
> new file mode 100644
> index 00000000000..d75be023510
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s16_s16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za32_s16_s16_0:
> +** ...
> +** smop4a za0\.s, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za32_s16_s16_0, svint16_t,
> + svmop4a_1x1_za32_s16_s16 (0, z0, z1),
> + svmop4a_za32 (0, z0, z1));
> +
> +/*
> +** mop4a_1x1_za32_s16_s16_3:
> +** ...
> +** smop4a za3\.s, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za32_s16_s16_3, svint16_t,
> + svmop4a_1x1_za32_s16_s16 (3, z0, z1),
> + svmop4a_za32 (3, z0, z1));
> +
> +/*
> +** mop4a_1x2_za32_s16_s16_0:
> +** ...
> +** smop4a za0\.s, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_s16_s16_0, svint16_t, svint16x2_t,
> + svmop4a_1x2_za32_s16_s16 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_1x2_za32_s16_s16_3:
> +** ...
> +** smop4a za3\.s, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_s16_s16_3, svint16_t, svint16x2_t,
> + svmop4a_1x2_za32_s16_s16 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_s16_s16_0:
> +** ...
> +** smop4a za0\.s, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_s16_s16_0, svint16x2_t, svint16_t,
> + svmop4a_2x1_za32_s16_s16 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_s16_s16_3:
> +** ...
> +** smop4a za3\.s, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_s16_s16_3, svint16x2_t, svint16_t,
> + svmop4a_2x1_za32_s16_s16 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x2_za32_s16_s16_0:
> +** ...
> +** smop4a za0\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za32_s16_s16_0, svint16x2_t,
> + svmop4a_2x2_za32_s16_s16 (0, z0, z1),
> + svmop4a_za32 (0, z0, z1));
> +
> +/*
> +** mop4a_2x2_za32_s16_s16_3:
> +** ...
> +** smop4a za3\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za32_s16_s16_3, svint16x2_t,
> + svmop4a_2x2_za32_s16_s16 (3, z0, z1),
> + svmop4a_za32 (3, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_s8.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_s8.c
> new file mode 100644
> index 00000000000..7963b71e6ca
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_s8.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za32_s8_s8_0:
> +** ...
> +** smop4a za0\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za32_s8_s8_0, svint8_t,
> + svmop4a_1x1_za32_s8_s8 (0, z0, z1),
> + svmop4a_za32 (0, z0, z1));
> +
> +/*
> +** mop4a_1x1_za32_s8_s8_3:
> +** ...
> +** smop4a za3\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za32_s8_s8_3, svint8_t,
> + svmop4a_1x1_za32_s8_s8 (3, z0, z1),
> + svmop4a_za32 (3, z0, z1));
> +
> +/*
> +** mop4a_1x2_za32_s8_s8_0:
> +** ...
> +** smop4a za0\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_s8_s8_0, svint8_t, svint8x2_t,
> + svmop4a_1x2_za32_s8_s8 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_1x2_za32_s8_s8_3:
> +** ...
> +** smop4a za3\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_s8_s8_3, svint8_t, svint8x2_t,
> + svmop4a_1x2_za32_s8_s8 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_s8_s8_0:
> +** ...
> +** smop4a za0\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_s8_s8_0, svint8x2_t, svint8_t,
> + svmop4a_2x1_za32_s8_s8 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_s8_s8_3:
> +** ...
> +** smop4a za3\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_s8_s8_3, svint8x2_t, svint8_t,
> + svmop4a_2x1_za32_s8_s8 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x2_za32_s8_s8_0:
> +** ...
> +** smop4a za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za32_s8_s8_0, svint8x2_t,
> + svmop4a_2x2_za32_s8_s8 (0, z0, z1),
> + svmop4a_za32 (0, z0, z1));
> +
> +/*
> +** mop4a_2x2_za32_s8_s8_3:
> +** ...
> +** smop4a za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za32_s8_s8_3, svint8x2_t,
> + svmop4a_2x2_za32_s8_s8 (3, z0, z1),
> + svmop4a_za32 (3, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_u8.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_u8.c
> new file mode 100644
> index 00000000000..0313d6be245
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_s8_u8.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za32_s8_u8_0:
> +** ...
> +** sumop4a za0\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x1_za32_s8_u8_0, svint8_t, svuint8_t,
> + svmop4a_1x1_za32_s8_u8 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_1x1_za32_s8_u8_3:
> +** ...
> +** sumop4a za3\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x1_za32_s8_u8_3, svint8_t, svuint8_t,
> + svmop4a_1x1_za32_s8_u8 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_1x2_za32_s8_u8_0:
> +** ...
> +** sumop4a za0\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_s8_u8_0, svint8_t, svuint8x2_t,
> + svmop4a_1x2_za32_s8_u8 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_1x2_za32_s8_u8_3:
> +** ...
> +** sumop4a za3\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_s8_u8_3, svint8_t, svuint8x2_t,
> + svmop4a_1x2_za32_s8_u8 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_s8_u8_0:
> +** ...
> +** sumop4a za0\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_s8_u8_0, svint8x2_t, svuint8_t,
> + svmop4a_2x1_za32_s8_u8 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_s8_u8_3:
> +** ...
> +** sumop4a za3\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_s8_u8_3, svint8x2_t, svuint8_t,
> + svmop4a_2x1_za32_s8_u8 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x2_za32_s8_u8_0:
> +** ...
> +** sumop4a za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x2_za32_s8_u8_0, svint8x2_t, svuint8x2_t,
> + svmop4a_2x2_za32_s8_u8 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_2x2_za32_s8_u8_3:
> +** ...
> +** sumop4a za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x2_za32_s8_u8_3, svint8x2_t, svuint8x2_t,
> + svmop4a_2x2_za32_s8_u8 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u16_u16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u16_u16.c
> new file mode 100644
> index 00000000000..93caf879336
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u16_u16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za32_u16_u16_0:
> +** ...
> +** umop4a za0\.s, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za32_u16_u16_0, svuint16_t,
> + svmop4a_1x1_za32_u16_u16 (0, z0, z1),
> + svmop4a_za32 (0, z0, z1));
> +
> +/*
> +** mop4a_1x1_za32_u16_u16_3:
> +** ...
> +** umop4a za3\.s, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za32_u16_u16_3, svuint16_t,
> + svmop4a_1x1_za32_u16_u16 (3, z0, z1),
> + svmop4a_za32 (3, z0, z1));
> +
> +/*
> +** mop4a_1x2_za32_u16_u16_0:
> +** ...
> +** umop4a za0\.s, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_u16_u16_0, svuint16_t, svuint16x2_t,
> + svmop4a_1x2_za32_u16_u16 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_1x2_za32_u16_u16_3:
> +** ...
> +** umop4a za3\.s, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_u16_u16_3, svuint16_t, svuint16x2_t,
> + svmop4a_1x2_za32_u16_u16 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_u16_u16_0:
> +** ...
> +** umop4a za0\.s, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_u16_u16_0, svuint16x2_t, svuint16_t,
> + svmop4a_2x1_za32_u16_u16 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_u16_u16_3:
> +** ...
> +** umop4a za3\.s, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_u16_u16_3, svuint16x2_t, svuint16_t,
> + svmop4a_2x1_za32_u16_u16 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x2_za32_u16_u16_0:
> +** ...
> +** umop4a za0\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za32_u16_u16_0, svuint16x2_t,
> + svmop4a_2x2_za32_u16_u16 (0, z0, z1),
> + svmop4a_za32 (0, z0, z1));
> +
> +/*
> +** mop4a_2x2_za32_u16_u16_3:
> +** ...
> +** umop4a za3\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za32_u16_u16_3, svuint16x2_t,
> + svmop4a_2x2_za32_u16_u16 (3, z0, z1),
> + svmop4a_za32 (3, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_s8.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_s8.c
> new file mode 100644
> index 00000000000..ea243532701
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_s8.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za32_u8_s8_0:
> +** ...
> +** usmop4a za0\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x1_za32_u8_s8_0, svuint8_t, svint8_t,
> + svmop4a_1x1_za32_u8_s8 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_1x1_za32_u8_s8_3:
> +** ...
> +** usmop4a za3\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x1_za32_u8_s8_3, svuint8_t, svint8_t,
> + svmop4a_1x1_za32_u8_s8 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_1x2_za32_u8_s8_0:
> +** ...
> +** usmop4a za0\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_u8_s8_0, svuint8_t, svint8x2_t,
> + svmop4a_1x2_za32_u8_s8 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_1x2_za32_u8_s8_3:
> +** ...
> +** usmop4a za3\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_u8_s8_3, svuint8_t, svint8x2_t,
> + svmop4a_1x2_za32_u8_s8 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_u8_s8_0:
> +** ...
> +** usmop4a za0\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_u8_s8_0, svuint8x2_t, svint8_t,
> + svmop4a_2x1_za32_u8_s8 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_u8_s8_3:
> +** ...
> +** usmop4a za3\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_u8_s8_3, svuint8x2_t, svint8_t,
> + svmop4a_2x1_za32_u8_s8 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x2_za32_u8_s8_0:
> +** ...
> +** usmop4a za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x2_za32_u8_s8_0, svuint8x2_t, svint8x2_t,
> + svmop4a_2x2_za32_u8_s8 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_2x2_za32_u8_s8_3:
> +** ...
> +** usmop4a za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x2_za32_u8_s8_3, svuint8x2_t, svint8x2_t,
> + svmop4a_2x2_za32_u8_s8 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_u8.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_u8.c
> new file mode 100644
> index 00000000000..cbe3e2c56f9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za32_u8_u8.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za32_u8_u8_0:
> +** ...
> +** umop4a za0\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za32_u8_u8_0, svuint8_t,
> + svmop4a_1x1_za32_u8_u8 (0, z0, z1),
> + svmop4a_za32 (0, z0, z1));
> +
> +/*
> +** mop4a_1x1_za32_u8_u8_3:
> +** ...
> +** umop4a za3\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za32_u8_u8_3, svuint8_t,
> + svmop4a_1x1_za32_u8_u8 (3, z0, z1),
> + svmop4a_za32 (3, z0, z1));
> +
> +/*
> +** mop4a_1x2_za32_u8_u8_0:
> +** ...
> +** umop4a za0\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_u8_u8_0, svuint8_t, svuint8x2_t,
> + svmop4a_1x2_za32_u8_u8 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_1x2_za32_u8_u8_3:
> +** ...
> +** umop4a za3\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za32_u8_u8_3, svuint8_t, svuint8x2_t,
> + svmop4a_1x2_za32_u8_u8 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_u8_u8_0:
> +** ...
> +** umop4a za0\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_u8_u8_0, svuint8x2_t, svuint8_t,
> + svmop4a_2x1_za32_u8_u8 (0, z0, z4),
> + svmop4a_za32 (0, z0, z4));
> +
> +/*
> +** mop4a_2x1_za32_u8_u8_3:
> +** ...
> +** umop4a za3\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za32_u8_u8_3, svuint8x2_t, svuint8_t,
> + svmop4a_2x1_za32_u8_u8 (3, z0, z4),
> + svmop4a_za32 (3, z0, z4));
> +
> +/*
> +** mop4a_2x2_za32_u8_u8_0:
> +** ...
> +** umop4a za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za32_u8_u8_0, svuint8x2_t,
> + svmop4a_2x2_za32_u8_u8 (0, z0, z1),
> + svmop4a_za32 (0, z0, z1));
> +
> +/*
> +** mop4a_2x2_za32_u8_u8_3:
> +** ...
> +** umop4a za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za32_u8_u8_3, svuint8x2_t,
> + svmop4a_2x2_za32_u8_u8 (3, z0, z1),
> + svmop4a_za32 (3, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_f64_f64.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_f64_f64.c
> new file mode 100644
> index 00000000000..9ea4c735a8e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_f64_f64.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-f64f64"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za64_f64_f64_0:
> +** ...
> +** fmop4a za0\.d, z0\.d, z30\.d
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za64_f64_f64_0, svfloat64_t,
> + svmop4a_1x1_za64_f64_f64 (0, z0, z1),
> + svmop4a_za64 (0, z0, z1));
> +
> +/*
> +** mop4a_1x1_za64_f64_f64_7:
> +** ...
> +** fmop4a za7\.d, z0\.d, z30\.d
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za64_f64_f64_7, svfloat64_t,
> + svmop4a_1x1_za64_f64_f64 (7, z0, z1),
> + svmop4a_za64 (7, z0, z1));
> +
> +/*
> +** mop4a_1x2_za64_f64_f64_0:
> +** ...
> +** fmop4a za0\.d, z0\.d, {z30\.d - z31\.d}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za64_f64_f64_0, svfloat64_t, svfloat64x2_t,
> + svmop4a_1x2_za64_f64_f64 (0, z0, z4),
> + svmop4a_za64 (0, z0, z4));
> +
> +/*
> +** mop4a_1x2_za64_f64_f64_7:
> +** ...
> +** fmop4a za7\.d, z0\.d, {z30\.d - z31\.d}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za64_f64_f64_7, svfloat64_t, svfloat64x2_t,
> + svmop4a_1x2_za64_f64_f64 (7, z0, z4),
> + svmop4a_za64 (7, z0, z4));
> +
> +/*
> +** mop4a_2x1_za64_f64_f64_0:
> +** ...
> +** fmop4a za0\.d, {z0\.d - z1\.d}, z30\.d
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za64_f64_f64_0, svfloat64x2_t, svfloat64_t,
> + svmop4a_2x1_za64_f64_f64 (0, z0, z4),
> + svmop4a_za64 (0, z0, z4));
> +
> +/*
> +** mop4a_2x1_za64_f64_f64_7:
> +** ...
> +** fmop4a za7\.d, {z0\.d - z1\.d}, z30\.d
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za64_f64_f64_7, svfloat64x2_t, svfloat64_t,
> + svmop4a_2x1_za64_f64_f64 (7, z0, z4),
> + svmop4a_za64 (7, z0, z4));
> +
> +/*
> +** mop4a_2x2_za64_f64_f64_0:
> +** ...
> +** fmop4a za0\.d, {z0\.d - z1\.d}, {z30\.d - z31\.d}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za64_f64_f64_0, svfloat64x2_t,
> + svmop4a_2x2_za64_f64_f64 (0, z0, z1),
> + svmop4a_za64 (0, z0, z1));
> +
> +/*
> +** mop4a_2x2_za64_f64_f64_7:
> +** ...
> +** fmop4a za7\.d, {z0\.d - z1\.d}, {z30\.d - z31\.d}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za64_f64_f64_7, svfloat64x2_t,
> + svmop4a_2x2_za64_f64_f64 (7, z0, z1),
> + svmop4a_za64 (7, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_s16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_s16.c
> new file mode 100644
> index 00000000000..82713f37853
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_s16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za64_s16_s16_0:
> +** ...
> +** smop4a za0\.d, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za64_s16_s16_0, svint16_t,
> + svmop4a_1x1_za64_s16_s16 (0, z0, z1),
> + svmop4a_za64 (0, z0, z1));
> +
> +/*
> +** mop4a_1x1_za64_s16_s16_7:
> +** ...
> +** smop4a za7\.d, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za64_s16_s16_7, svint16_t,
> + svmop4a_1x1_za64_s16_s16 (7, z0, z1),
> + svmop4a_za64 (7, z0, z1));
> +
> +/*
> +** mop4a_1x2_za64_s16_s16_0:
> +** ...
> +** smop4a za0\.d, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za64_s16_s16_0, svint16_t, svint16x2_t,
> + svmop4a_1x2_za64_s16_s16 (0, z0, z4),
> + svmop4a_za64 (0, z0, z4));
> +
> +/*
> +** mop4a_1x2_za64_s16_s16_7:
> +** ...
> +** smop4a za7\.d, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za64_s16_s16_7, svint16_t, svint16x2_t,
> + svmop4a_1x2_za64_s16_s16 (7, z0, z4),
> + svmop4a_za64 (7, z0, z4));
> +
> +/*
> +** mop4a_2x1_za64_s16_s16_0:
> +** ...
> +** smop4a za0\.d, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za64_s16_s16_0, svint16x2_t, svint16_t,
> + svmop4a_2x1_za64_s16_s16 (0, z0, z4),
> + svmop4a_za64 (0, z0, z4));
> +
> +/*
> +** mop4a_2x1_za64_s16_s16_7:
> +** ...
> +** smop4a za7\.d, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za64_s16_s16_7, svint16x2_t, svint16_t,
> + svmop4a_2x1_za64_s16_s16 (7, z0, z4),
> + svmop4a_za64 (7, z0, z4));
> +
> +/*
> +** mop4a_2x2_za64_s16_s16_0:
> +** ...
> +** smop4a za0\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za64_s16_s16_0, svint16x2_t,
> + svmop4a_2x2_za64_s16_s16 (0, z0, z1),
> + svmop4a_za64 (0, z0, z1));
> +
> +/*
> +** mop4a_2x2_za64_s16_s16_7:
> +** ...
> +** smop4a za7\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za64_s16_s16_7, svint16x2_t,
> + svmop4a_2x2_za64_s16_s16 (7, z0, z1),
> + svmop4a_za64 (7, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_u16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_u16.c
> new file mode 100644
> index 00000000000..8d0c65c8d5a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_s16_u16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za64_s16_u16_0:
> +** ...
> +** sumop4a za0\.d, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x1_za64_s16_u16_0, svint16_t, svuint16_t,
> + svmop4a_1x1_za64_s16_u16 (0, z0, z4),
> + svmop4a_za64 (0, z0, z4));
> +
> +/*
> +** mop4a_1x1_za64_s16_u16_7:
> +** ...
> +** sumop4a za7\.d, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x1_za64_s16_u16_7, svint16_t, svuint16_t,
> + svmop4a_1x1_za64_s16_u16 (7, z0, z4),
> + svmop4a_za64 (7, z0, z4));
> +
> +/*
> +** mop4a_1x2_za64_s16_u16_0:
> +** ...
> +** sumop4a za0\.d, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za64_s16_u16_0, svint16_t, svuint16x2_t,
> + svmop4a_1x2_za64_s16_u16 (0, z0, z4),
> + svmop4a_za64 (0, z0, z4));
> +
> +/*
> +** mop4a_1x2_za64_s16_u16_7:
> +** ...
> +** sumop4a za7\.d, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za64_s16_u16_7, svint16_t, svuint16x2_t,
> + svmop4a_1x2_za64_s16_u16 (7, z0, z4),
> + svmop4a_za64 (7, z0, z4));
> +
> +/*
> +** mop4a_2x1_za64_s16_u16_0:
> +** ...
> +** sumop4a za0\.d, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za64_s16_u16_0, svint16x2_t, svuint16_t,
> + svmop4a_2x1_za64_s16_u16 (0, z0, z4),
> + svmop4a_za64 (0, z0, z4));
> +
> +/*
> +** mop4a_2x1_za64_s16_u16_7:
> +** ...
> +** sumop4a za7\.d, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za64_s16_u16_7, svint16x2_t, svuint16_t,
> + svmop4a_2x1_za64_s16_u16 (7, z0, z4),
> + svmop4a_za64 (7, z0, z4));
> +
> +/*
> +** mop4a_2x2_za64_s16_u16_0:
> +** ...
> +** sumop4a za0\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x2_za64_s16_u16_0, svint16x2_t, svuint16x2_t,
> + svmop4a_2x2_za64_s16_u16 (0, z0, z4),
> + svmop4a_za64 (0, z0, z4));
> +
> +/*
> +** mop4a_2x2_za64_s16_u16_7:
> +** ...
> +** sumop4a za7\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x2_za64_s16_u16_7, svint16x2_t, svuint16x2_t,
> + svmop4a_2x2_za64_s16_u16 (7, z0, z4),
> + svmop4a_za64 (7, z0, z4));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_s16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_s16.c
> new file mode 100644
> index 00000000000..20b83ed83dc
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_s16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za64_u16_s16_0:
> +** ...
> +** usmop4a za0\.d, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x1_za64_u16_s16_0, svuint16_t, svint16_t,
> + svmop4a_1x1_za64_u16_s16 (0, z0, z4),
> + svmop4a_za64 (0, z0, z4));
> +
> +/*
> +** mop4a_1x1_za64_u16_s16_7:
> +** ...
> +** usmop4a za7\.d, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x1_za64_u16_s16_7, svuint16_t, svint16_t,
> + svmop4a_1x1_za64_u16_s16 (7, z0, z4),
> + svmop4a_za64 (7, z0, z4));
> +
> +/*
> +** mop4a_1x2_za64_u16_s16_0:
> +** ...
> +** usmop4a za0\.d, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za64_u16_s16_0, svuint16_t, svint16x2_t,
> + svmop4a_1x2_za64_u16_s16 (0, z0, z4),
> + svmop4a_za64 (0, z0, z4));
> +
> +/*
> +** mop4a_1x2_za64_u16_s16_7:
> +** ...
> +** usmop4a za7\.d, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za64_u16_s16_7, svuint16_t, svint16x2_t,
> + svmop4a_1x2_za64_u16_s16 (7, z0, z4),
> + svmop4a_za64 (7, z0, z4));
> +
> +/*
> +** mop4a_2x1_za64_u16_s16_0:
> +** ...
> +** usmop4a za0\.d, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za64_u16_s16_0, svuint16x2_t, svint16_t,
> + svmop4a_2x1_za64_u16_s16 (0, z0, z4),
> + svmop4a_za64 (0, z0, z4));
> +
> +/*
> +** mop4a_2x1_za64_u16_s16_7:
> +** ...
> +** usmop4a za7\.d, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za64_u16_s16_7, svuint16x2_t, svint16_t,
> + svmop4a_2x1_za64_u16_s16 (7, z0, z4),
> + svmop4a_za64 (7, z0, z4));
> +
> +/*
> +** mop4a_2x2_za64_u16_s16_0:
> +** ...
> +** usmop4a za0\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x2_za64_u16_s16_0, svuint16x2_t, svint16x2_t,
> + svmop4a_2x2_za64_u16_s16 (0, z0, z4),
> + svmop4a_za64 (0, z0, z4));
> +
> +/*
> +** mop4a_2x2_za64_u16_s16_7:
> +** ...
> +** usmop4a za7\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x2_za64_u16_s16_7, svuint16x2_t, svint16x2_t,
> + svmop4a_2x2_za64_u16_s16 (7, z0, z4),
> + svmop4a_za64 (7, z0, z4));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_u16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_u16.c
> new file mode 100644
> index 00000000000..5cee0fade96
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4a_za64_u16_u16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4a_1x1_za64_u16_u16_0:
> +** ...
> +** umop4a za0\.d, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za64_u16_u16_0, svuint16_t,
> + svmop4a_1x1_za64_u16_u16 (0, z0, z1),
> + svmop4a_za64 (0, z0, z1));
> +
> +/*
> +** mop4a_1x1_za64_u16_u16_7:
> +** ...
> +** umop4a za7\.d, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_1x1_za64_u16_u16_7, svuint16_t,
> + svmop4a_1x1_za64_u16_u16 (7, z0, z1),
> + svmop4a_za64 (7, z0, z1));
> +
> +/*
> +** mop4a_1x2_za64_u16_u16_0:
> +** ...
> +** umop4a za0\.d, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za64_u16_u16_0, svuint16_t, svuint16x2_t,
> + svmop4a_1x2_za64_u16_u16 (0, z0, z4),
> + svmop4a_za64 (0, z0, z4));
> +
> +/*
> +** mop4a_1x2_za64_u16_u16_7:
> +** ...
> +** umop4a za7\.d, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_1x2_za64_u16_u16_7, svuint16_t, svuint16x2_t,
> + svmop4a_1x2_za64_u16_u16 (7, z0, z4),
> + svmop4a_za64 (7, z0, z4));
> +
> +/*
> +** mop4a_2x1_za64_u16_u16_0:
> +** ...
> +** umop4a za0\.d, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za64_u16_u16_0, svuint16x2_t, svuint16_t,
> + svmop4a_2x1_za64_u16_u16 (0, z0, z4),
> + svmop4a_za64 (0, z0, z4));
> +
> +/*
> +** mop4a_2x1_za64_u16_u16_7:
> +** ...
> +** umop4a za7\.d, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4a_2x1_za64_u16_u16_7, svuint16x2_t, svuint16_t,
> + svmop4a_2x1_za64_u16_u16 (7, z0, z4),
> + svmop4a_za64 (7, z0, z4));
> +
> +/*
> +** mop4a_2x2_za64_u16_u16_0:
> +** ...
> +** umop4a za0\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za64_u16_u16_0, svuint16x2_t,
> + svmop4a_2x2_za64_u16_u16 (0, z0, z1),
> + svmop4a_za64 (0, z0, z1));
> +
> +/*
> +** mop4a_2x2_za64_u16_u16_7:
> +** ...
> +** umop4a za7\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4a_2x2_za64_u16_u16_7, svuint16x2_t,
> + svmop4a_2x2_za64_u16_u16 (7, z0, z1),
> + svmop4a_za64 (7, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za16_bf16_bf16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za16_bf16_bf16.c
> new file mode 100644
> index 00000000000..980b650cc3a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za16_bf16_bf16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-b16b16"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4s_1x1_za16_bf16_bf16_0:
> +** ...
> +** bfmop4s za0\.h, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za16_bf16_bf16_0, svbfloat16_t,
> + svmop4s_1x1_za16_bf16_bf16 (0, z0, z1),
> + svmop4s_za16 (0, z0, z1));
> +
> +/*
> +** mop4s_1x1_za16_bf16_bf16_1:
> +** ...
> +** bfmop4s za1\.h, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za16_bf16_bf16_1, svbfloat16_t,
> + svmop4s_1x1_za16_bf16_bf16 (1, z0, z1),
> + svmop4s_za16 (1, z0, z1));
> +
> +/*
> +** mop4s_1x2_za16_bf16_bf16_0:
> +** ...
> +** bfmop4s za0\.h, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za16_bf16_bf16_0, svbfloat16_t, svbfloat16x2_t,
> + svmop4s_1x2_za16_bf16_bf16 (0, z0, z4),
> + svmop4s_za16 (0, z0, z4));
> +
> +/*
> +** mop4s_1x2_za16_bf16_bf16_1:
> +** ...
> +** bfmop4s za1\.h, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za16_bf16_bf16_1, svbfloat16_t, svbfloat16x2_t,
> + svmop4s_1x2_za16_bf16_bf16 (1, z0, z4),
> + svmop4s_za16 (1, z0, z4));
> +
> +/*
> +** mop4s_2x1_za16_bf16_bf16_0:
> +** ...
> +** bfmop4s za0\.h, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za16_bf16_bf16_0, svbfloat16x2_t, svbfloat16_t,
> + svmop4s_2x1_za16_bf16_bf16 (0, z0, z4),
> + svmop4s_za16 (0, z0, z4));
> +
> +/*
> +** mop4s_2x1_za16_bf16_bf16_1:
> +** ...
> +** bfmop4s za1\.h, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za16_bf16_bf16_1, svbfloat16x2_t, svbfloat16_t,
> + svmop4s_2x1_za16_bf16_bf16 (1, z0, z4),
> + svmop4s_za16 (1, z0, z4));
> +
> +/*
> +** mop4s_2x2_za16_bf16_bf16_0:
> +** ...
> +** bfmop4s za0\.h, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za16_bf16_bf16_0, svbfloat16x2_t,
> + svmop4s_2x2_za16_bf16_bf16 (0, z0, z1),
> + svmop4s_za16 (0, z0, z1));
> +
> +/*
> +** mop4s_2x2_za16_bf16_bf16_1:
> +** ...
> +** bfmop4s za1\.h, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za16_bf16_bf16_1, svbfloat16x2_t,
> + svmop4s_2x2_za16_bf16_bf16 (1, z0, z1),
> + svmop4s_za16 (1, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za16_f16_f16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za16_f16_f16.c
> new file mode 100644
> index 00000000000..234f3898066
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za16_f16_f16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-f16f16"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4s_1x1_za16_f16_f16_0:
> +** ...
> +** fmop4s za0\.h, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za16_f16_f16_0, svfloat16_t,
> + svmop4s_1x1_za16_f16_f16 (0, z0, z1),
> + svmop4s_za16 (0, z0, z1));
> +
> +/*
> +** mop4s_1x1_za16_f16_f16_1:
> +** ...
> +** fmop4s za1\.h, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za16_f16_f16_1, svfloat16_t,
> + svmop4s_1x1_za16_f16_f16 (1, z0, z1),
> + svmop4s_za16 (1, z0, z1));
> +
> +/*
> +** mop4s_1x2_za16_f16_f16_0:
> +** ...
> +** fmop4s za0\.h, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za16_f16_f16_0, svfloat16_t, svfloat16x2_t,
> + svmop4s_1x2_za16_f16_f16 (0, z0, z4),
> + svmop4s_za16 (0, z0, z4));
> +
> +/*
> +** mop4s_1x2_za16_f16_f16_1:
> +** ...
> +** fmop4s za1\.h, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za16_f16_f16_1, svfloat16_t, svfloat16x2_t,
> + svmop4s_1x2_za16_f16_f16 (1, z0, z4),
> + svmop4s_za16 (1, z0, z4));
> +
> +/*
> +** mop4s_2x1_za16_f16_f16_0:
> +** ...
> +** fmop4s za0\.h, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za16_f16_f16_0, svfloat16x2_t, svfloat16_t,
> + svmop4s_2x1_za16_f16_f16 (0, z0, z4),
> + svmop4s_za16 (0, z0, z4));
> +
> +/*
> +** mop4s_2x1_za16_f16_f16_1:
> +** ...
> +** fmop4s za1\.h, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za16_f16_f16_1, svfloat16x2_t, svfloat16_t,
> + svmop4s_2x1_za16_f16_f16 (1, z0, z4),
> + svmop4s_za16 (1, z0, z4));
> +
> +/*
> +** mop4s_2x2_za16_f16_f16_0:
> +** ...
> +** fmop4s za0\.h, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za16_f16_f16_0, svfloat16x2_t,
> + svmop4s_2x2_za16_f16_f16 (0, z0, z1),
> + svmop4s_za16 (0, z0, z1));
> +
> +/*
> +** mop4s_2x2_za16_f16_f16_1:
> +** ...
> +** fmop4s za1\.h, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za16_f16_f16_1, svfloat16x2_t,
> + svmop4s_2x2_za16_f16_f16 (1, z0, z1),
> + svmop4s_za16 (1, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_bf16_bf16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_bf16_bf16.c
> new file mode 100644
> index 00000000000..346033a8ec2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_bf16_bf16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-b16b16"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4s_1x1_za32_bf16_bf16_0:
> +** ...
> +** bfmop4s za0\.s, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za32_bf16_bf16_0, svbfloat16_t,
> + svmop4s_1x1_za32_bf16_bf16 (0, z0, z1),
> + svmop4s_za32 (0, z0, z1));
> +
> +/*
> +** mop4s_1x1_za32_bf16_bf16_3:
> +** ...
> +** bfmop4s za3\.s, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za32_bf16_bf16_3, svbfloat16_t,
> + svmop4s_1x1_za32_bf16_bf16 (3, z0, z1),
> + svmop4s_za32 (3, z0, z1));
> +
> +/*
> +** mop4s_1x2_za32_bf16_bf16_0:
> +** ...
> +** bfmop4s za0\.s, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za32_bf16_bf16_0, svbfloat16_t, svbfloat16x2_t,
> + svmop4s_1x2_za32_bf16_bf16 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_1x2_za32_bf16_bf16_3:
> +** ...
> +** bfmop4s za3\.s, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za32_bf16_bf16_3, svbfloat16_t, svbfloat16x2_t,
> + svmop4s_1x2_za32_bf16_bf16 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_2x1_za32_bf16_bf16_0:
> +** ...
> +** bfmop4s za0\.s, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za32_bf16_bf16_0, svbfloat16x2_t, svbfloat16_t,
> + svmop4s_2x1_za32_bf16_bf16 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_2x1_za32_bf16_bf16_3:
> +** ...
> +** bfmop4s za3\.s, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za32_bf16_bf16_3, svbfloat16x2_t, svbfloat16_t,
> + svmop4s_2x1_za32_bf16_bf16 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_2x2_za32_bf16_bf16_0:
> +** ...
> +** bfmop4s za0\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za32_bf16_bf16_0, svbfloat16x2_t,
> + svmop4s_2x2_za32_bf16_bf16 (0, z0, z1),
> + svmop4s_za32 (0, z0, z1));
> +
> +/*
> +** mop4s_2x2_za32_bf16_bf16_3:
> +** ...
> +** bfmop4s za3\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za32_bf16_bf16_3, svbfloat16x2_t,
> + svmop4s_2x2_za32_bf16_bf16 (3, z0, z1),
> + svmop4s_za32 (3, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_f16_f16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_f16_f16.c
> new file mode 100644
> index 00000000000..aa8178b3d0f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_f16_f16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-f16f16"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4s_1x1_za32_f16_f16_0:
> +** ...
> +** fmop4s za0\.s, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za32_f16_f16_0, svfloat16_t,
> + svmop4s_1x1_za32_f16_f16 (0, z0, z1),
> + svmop4s_za32 (0, z0, z1));
> +
> +/*
> +** mop4s_1x1_za32_f16_f16_3:
> +** ...
> +** fmop4s za3\.s, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za32_f16_f16_3, svfloat16_t,
> + svmop4s_1x1_za32_f16_f16 (3, z0, z1),
> + svmop4s_za32 (3, z0, z1));
> +
> +/*
> +** mop4s_1x2_za32_f16_f16_0:
> +** ...
> +** fmop4s za0\.s, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za32_f16_f16_0, svfloat16_t, svfloat16x2_t,
> + svmop4s_1x2_za32_f16_f16 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_1x2_za32_f16_f16_3:
> +** ...
> +** fmop4s za3\.s, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za32_f16_f16_3, svfloat16_t, svfloat16x2_t,
> + svmop4s_1x2_za32_f16_f16 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_2x1_za32_f16_f16_0:
> +** ...
> +** fmop4s za0\.s, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za32_f16_f16_0, svfloat16x2_t, svfloat16_t,
> + svmop4s_2x1_za32_f16_f16 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_2x1_za32_f16_f16_3:
> +** ...
> +** fmop4s za3\.s, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za32_f16_f16_3, svfloat16x2_t, svfloat16_t,
> + svmop4s_2x1_za32_f16_f16 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_2x2_za32_f16_f16_0:
> +** ...
> +** fmop4s za0\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za32_f16_f16_0, svfloat16x2_t,
> + svmop4s_2x2_za32_f16_f16 (0, z0, z1),
> + svmop4s_za32 (0, z0, z1));
> +
> +/*
> +** mop4s_2x2_za32_f16_f16_3:
> +** ...
> +** fmop4s za3\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za32_f16_f16_3, svfloat16x2_t,
> + svmop4s_2x2_za32_f16_f16 (3, z0, z1),
> + svmop4s_za32 (3, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s16_s16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s16_s16.c
> new file mode 100644
> index 00000000000..ee72059d739
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s16_s16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4s_1x1_za32_s16_s16_0:
> +** ...
> +** smop4s za0\.s, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za32_s16_s16_0, svint16_t,
> + svmop4s_1x1_za32_s16_s16 (0, z0, z1),
> + svmop4s_za32 (0, z0, z1));
> +
> +/*
> +** mop4s_1x1_za32_s16_s16_3:
> +** ...
> +** smop4s za3\.s, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za32_s16_s16_3, svint16_t,
> + svmop4s_1x1_za32_s16_s16 (3, z0, z1),
> + svmop4s_za32 (3, z0, z1));
> +
> +/*
> +** mop4s_1x2_za32_s16_s16_0:
> +** ...
> +** smop4s za0\.s, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za32_s16_s16_0, svint16_t, svint16x2_t,
> + svmop4s_1x2_za32_s16_s16 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_1x2_za32_s16_s16_3:
> +** ...
> +** smop4s za3\.s, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za32_s16_s16_3, svint16_t, svint16x2_t,
> + svmop4s_1x2_za32_s16_s16 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_2x1_za32_s16_s16_0:
> +** ...
> +** smop4s za0\.s, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za32_s16_s16_0, svint16x2_t, svint16_t,
> + svmop4s_2x1_za32_s16_s16 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_2x1_za32_s16_s16_3:
> +** ...
> +** smop4s za3\.s, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za32_s16_s16_3, svint16x2_t, svint16_t,
> + svmop4s_2x1_za32_s16_s16 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_2x2_za32_s16_s16_0:
> +** ...
> +** smop4s za0\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za32_s16_s16_0, svint16x2_t,
> + svmop4s_2x2_za32_s16_s16 (0, z0, z1),
> + svmop4s_za32 (0, z0, z1));
> +
> +/*
> +** mop4s_2x2_za32_s16_s16_3:
> +** ...
> +** smop4s za3\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za32_s16_s16_3, svint16x2_t,
> + svmop4s_2x2_za32_s16_s16 (3, z0, z1),
> + svmop4s_za32 (3, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_s8.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_s8.c
> new file mode 100644
> index 00000000000..423b127fcbd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_s8.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4s_1x1_za32_s8_s8_0:
> +** ...
> +** smop4s za0\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za32_s8_s8_0, svint8_t,
> + svmop4s_1x1_za32_s8_s8 (0, z0, z1),
> + svmop4s_za32 (0, z0, z1));
> +
> +/*
> +** mop4s_1x1_za32_s8_s8_3:
> +** ...
> +** smop4s za3\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za32_s8_s8_3, svint8_t,
> + svmop4s_1x1_za32_s8_s8 (3, z0, z1),
> + svmop4s_za32 (3, z0, z1));
> +
> +/*
> +** mop4s_1x2_za32_s8_s8_0:
> +** ...
> +** smop4s za0\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za32_s8_s8_0, svint8_t, svint8x2_t,
> + svmop4s_1x2_za32_s8_s8 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_1x2_za32_s8_s8_3:
> +** ...
> +** smop4s za3\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za32_s8_s8_3, svint8_t, svint8x2_t,
> + svmop4s_1x2_za32_s8_s8 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_2x1_za32_s8_s8_0:
> +** ...
> +** smop4s za0\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za32_s8_s8_0, svint8x2_t, svint8_t,
> + svmop4s_2x1_za32_s8_s8 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_2x1_za32_s8_s8_3:
> +** ...
> +** smop4s za3\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za32_s8_s8_3, svint8x2_t, svint8_t,
> + svmop4s_2x1_za32_s8_s8 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_2x2_za32_s8_s8_0:
> +** ...
> +** smop4s za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za32_s8_s8_0, svint8x2_t,
> + svmop4s_2x2_za32_s8_s8 (0, z0, z1),
> + svmop4s_za32 (0, z0, z1));
> +
> +/*
> +** mop4s_2x2_za32_s8_s8_3:
> +** ...
> +** smop4s za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za32_s8_s8_3, svint8x2_t,
> + svmop4s_2x2_za32_s8_s8 (3, z0, z1),
> + svmop4s_za32 (3, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_u8.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_u8.c
> new file mode 100644
> index 00000000000..b82dc21df8e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_s8_u8.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4s_1x1_za32_s8_u8_0:
> +** ...
> +** sumop4s za0\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x1_za32_s8_u8_0, svint8_t, svuint8_t,
> + svmop4s_1x1_za32_s8_u8 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_1x1_za32_s8_u8_3:
> +** ...
> +** sumop4s za3\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x1_za32_s8_u8_3, svint8_t, svuint8_t,
> + svmop4s_1x1_za32_s8_u8 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_1x2_za32_s8_u8_0:
> +** ...
> +** sumop4s za0\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za32_s8_u8_0, svint8_t, svuint8x2_t,
> + svmop4s_1x2_za32_s8_u8 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_1x2_za32_s8_u8_3:
> +** ...
> +** sumop4s za3\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za32_s8_u8_3, svint8_t, svuint8x2_t,
> + svmop4s_1x2_za32_s8_u8 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_2x1_za32_s8_u8_0:
> +** ...
> +** sumop4s za0\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za32_s8_u8_0, svint8x2_t, svuint8_t,
> + svmop4s_2x1_za32_s8_u8 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_2x1_za32_s8_u8_3:
> +** ...
> +** sumop4s za3\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za32_s8_u8_3, svint8x2_t, svuint8_t,
> + svmop4s_2x1_za32_s8_u8 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_2x2_za32_s8_u8_0:
> +** ...
> +** sumop4s za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x2_za32_s8_u8_0, svint8x2_t, svuint8x2_t,
> + svmop4s_2x2_za32_s8_u8 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_2x2_za32_s8_u8_3:
> +** ...
> +** sumop4s za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x2_za32_s8_u8_3, svint8x2_t, svuint8x2_t,
> + svmop4s_2x2_za32_s8_u8 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u16_u16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u16_u16.c
> new file mode 100644
> index 00000000000..8d7a211c54f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u16_u16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4s_1x1_za32_u16_u16_0:
> +** ...
> +** umop4s za0\.s, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za32_u16_u16_0, svuint16_t,
> + svmop4s_1x1_za32_u16_u16 (0, z0, z1),
> + svmop4s_za32 (0, z0, z1));
> +
> +/*
> +** mop4s_1x1_za32_u16_u16_3:
> +** ...
> +** umop4s za3\.s, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za32_u16_u16_3, svuint16_t,
> + svmop4s_1x1_za32_u16_u16 (3, z0, z1),
> + svmop4s_za32 (3, z0, z1));
> +
> +/*
> +** mop4s_1x2_za32_u16_u16_0:
> +** ...
> +** umop4s za0\.s, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za32_u16_u16_0, svuint16_t, svuint16x2_t,
> + svmop4s_1x2_za32_u16_u16 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_1x2_za32_u16_u16_3:
> +** ...
> +** umop4s za3\.s, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za32_u16_u16_3, svuint16_t, svuint16x2_t,
> + svmop4s_1x2_za32_u16_u16 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_2x1_za32_u16_u16_0:
> +** ...
> +** umop4s za0\.s, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za32_u16_u16_0, svuint16x2_t, svuint16_t,
> + svmop4s_2x1_za32_u16_u16 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_2x1_za32_u16_u16_3:
> +** ...
> +** umop4s za3\.s, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za32_u16_u16_3, svuint16x2_t, svuint16_t,
> + svmop4s_2x1_za32_u16_u16 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_2x2_za32_u16_u16_0:
> +** ...
> +** umop4s za0\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za32_u16_u16_0, svuint16x2_t,
> + svmop4s_2x2_za32_u16_u16 (0, z0, z1),
> + svmop4s_za32 (0, z0, z1));
> +
> +/*
> +** mop4s_2x2_za32_u16_u16_3:
> +** ...
> +** umop4s za3\.s, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za32_u16_u16_3, svuint16x2_t,
> + svmop4s_2x2_za32_u16_u16 (3, z0, z1),
> + svmop4s_za32 (3, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_s8.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_s8.c
> new file mode 100644
> index 00000000000..cd18b3f773d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_s8.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4s_1x1_za32_u8_s8_0:
> +** ...
> +** usmop4s za0\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x1_za32_u8_s8_0, svuint8_t, svint8_t,
> + svmop4s_1x1_za32_u8_s8 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_1x1_za32_u8_s8_3:
> +** ...
> +** usmop4s za3\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x1_za32_u8_s8_3, svuint8_t, svint8_t,
> + svmop4s_1x1_za32_u8_s8 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_1x2_za32_u8_s8_0:
> +** ...
> +** usmop4s za0\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za32_u8_s8_0, svuint8_t, svint8x2_t,
> + svmop4s_1x2_za32_u8_s8 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_1x2_za32_u8_s8_3:
> +** ...
> +** usmop4s za3\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za32_u8_s8_3, svuint8_t, svint8x2_t,
> + svmop4s_1x2_za32_u8_s8 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_2x1_za32_u8_s8_0:
> +** ...
> +** usmop4s za0\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za32_u8_s8_0, svuint8x2_t, svint8_t,
> + svmop4s_2x1_za32_u8_s8 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_2x1_za32_u8_s8_3:
> +** ...
> +** usmop4s za3\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za32_u8_s8_3, svuint8x2_t, svint8_t,
> + svmop4s_2x1_za32_u8_s8 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_2x2_za32_u8_s8_0:
> +** ...
> +** usmop4s za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x2_za32_u8_s8_0, svuint8x2_t, svint8x2_t,
> + svmop4s_2x2_za32_u8_s8 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_2x2_za32_u8_s8_3:
> +** ...
> +** usmop4s za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x2_za32_u8_s8_3, svuint8x2_t, svint8x2_t,
> + svmop4s_2x2_za32_u8_s8 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_u8.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_u8.c
> new file mode 100644
> index 00000000000..4f0b5f9faa8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za32_u8_u8.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4s_1x1_za32_u8_u8_0:
> +** ...
> +** umop4s za0\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za32_u8_u8_0, svuint8_t,
> + svmop4s_1x1_za32_u8_u8 (0, z0, z1),
> + svmop4s_za32 (0, z0, z1));
> +
> +/*
> +** mop4s_1x1_za32_u8_u8_3:
> +** ...
> +** umop4s za3\.s, z0\.b, z30\.b
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za32_u8_u8_3, svuint8_t,
> + svmop4s_1x1_za32_u8_u8 (3, z0, z1),
> + svmop4s_za32 (3, z0, z1));
> +
> +/*
> +** mop4s_1x2_za32_u8_u8_0:
> +** ...
> +** umop4s za0\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za32_u8_u8_0, svuint8_t, svuint8x2_t,
> + svmop4s_1x2_za32_u8_u8 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_1x2_za32_u8_u8_3:
> +** ...
> +** umop4s za3\.s, z0\.b, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za32_u8_u8_3, svuint8_t, svuint8x2_t,
> + svmop4s_1x2_za32_u8_u8 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_2x1_za32_u8_u8_0:
> +** ...
> +** umop4s za0\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za32_u8_u8_0, svuint8x2_t, svuint8_t,
> + svmop4s_2x1_za32_u8_u8 (0, z0, z4),
> + svmop4s_za32 (0, z0, z4));
> +
> +/*
> +** mop4s_2x1_za32_u8_u8_3:
> +** ...
> +** umop4s za3\.s, {z0\.b - z1\.b}, z30\.b
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za32_u8_u8_3, svuint8x2_t, svuint8_t,
> + svmop4s_2x1_za32_u8_u8 (3, z0, z4),
> + svmop4s_za32 (3, z0, z4));
> +
> +/*
> +** mop4s_2x2_za32_u8_u8_0:
> +** ...
> +** umop4s za0\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za32_u8_u8_0, svuint8x2_t,
> + svmop4s_2x2_za32_u8_u8 (0, z0, z1),
> + svmop4s_za32 (0, z0, z1));
> +
> +/*
> +** mop4s_2x2_za32_u8_u8_3:
> +** ...
> +** umop4s za3\.s, {z0\.b - z1\.b}, {z30\.b - z31\.b}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za32_u8_u8_3, svuint8x2_t,
> + svmop4s_2x2_za32_u8_u8 (3, z0, z1),
> + svmop4s_za32 (3, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_f64_f64.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_f64_f64.c
> new file mode 100644
> index 00000000000..4dc30b60e80
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_f64_f64.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-f64f64"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4s_1x1_za64_f64_f64_0:
> +** ...
> +** fmop4s za0\.d, z0\.d, z30\.d
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za64_f64_f64_0, svfloat64_t,
> + svmop4s_1x1_za64_f64_f64 (0, z0, z1),
> + svmop4s_za64 (0, z0, z1));
> +
> +/*
> +** mop4s_1x1_za64_f64_f64_7:
> +** ...
> +** fmop4s za7\.d, z0\.d, z30\.d
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za64_f64_f64_7, svfloat64_t,
> + svmop4s_1x1_za64_f64_f64 (7, z0, z1),
> + svmop4s_za64 (7, z0, z1));
> +
> +/*
> +** mop4s_1x2_za64_f64_f64_0:
> +** ...
> +** fmop4s za0\.d, z0\.d, {z30\.d - z31\.d}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za64_f64_f64_0, svfloat64_t, svfloat64x2_t,
> + svmop4s_1x2_za64_f64_f64 (0, z0, z4),
> + svmop4s_za64 (0, z0, z4));
> +
> +/*
> +** mop4s_1x2_za64_f64_f64_7:
> +** ...
> +** fmop4s za7\.d, z0\.d, {z30\.d - z31\.d}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za64_f64_f64_7, svfloat64_t, svfloat64x2_t,
> + svmop4s_1x2_za64_f64_f64 (7, z0, z4),
> + svmop4s_za64 (7, z0, z4));
> +
> +/*
> +** mop4s_2x1_za64_f64_f64_0:
> +** ...
> +** fmop4s za0\.d, {z0\.d - z1\.d}, z30\.d
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za64_f64_f64_0, svfloat64x2_t, svfloat64_t,
> + svmop4s_2x1_za64_f64_f64 (0, z0, z4),
> + svmop4s_za64 (0, z0, z4));
> +
> +/*
> +** mop4s_2x1_za64_f64_f64_7:
> +** ...
> +** fmop4s za7\.d, {z0\.d - z1\.d}, z30\.d
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za64_f64_f64_7, svfloat64x2_t, svfloat64_t,
> + svmop4s_2x1_za64_f64_f64 (7, z0, z4),
> + svmop4s_za64 (7, z0, z4));
> +
> +/*
> +** mop4s_2x2_za64_f64_f64_0:
> +** ...
> +** fmop4s za0\.d, {z0\.d - z1\.d}, {z30\.d - z31\.d}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za64_f64_f64_0, svfloat64x2_t,
> + svmop4s_2x2_za64_f64_f64 (0, z0, z1),
> + svmop4s_za64 (0, z0, z1));
> +
> +/*
> +** mop4s_2x2_za64_f64_f64_7:
> +** ...
> +** fmop4s za7\.d, {z0\.d - z1\.d}, {z30\.d - z31\.d}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za64_f64_f64_7, svfloat64x2_t,
> + svmop4s_2x2_za64_f64_f64 (7, z0, z1),
> + svmop4s_za64 (7, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_s16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_s16.c
> new file mode 100644
> index 00000000000..c29b6a0172d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_s16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4s_1x1_za64_s16_s16_0:
> +** ...
> +** smop4s za0\.d, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za64_s16_s16_0, svint16_t,
> + svmop4s_1x1_za64_s16_s16 (0, z0, z1),
> + svmop4s_za64 (0, z0, z1));
> +
> +/*
> +** mop4s_1x1_za64_s16_s16_7:
> +** ...
> +** smop4s za7\.d, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za64_s16_s16_7, svint16_t,
> + svmop4s_1x1_za64_s16_s16 (7, z0, z1),
> + svmop4s_za64 (7, z0, z1));
> +
> +/*
> +** mop4s_1x2_za64_s16_s16_0:
> +** ...
> +** smop4s za0\.d, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za64_s16_s16_0, svint16_t, svint16x2_t,
> + svmop4s_1x2_za64_s16_s16 (0, z0, z4),
> + svmop4s_za64 (0, z0, z4));
> +
> +/*
> +** mop4s_1x2_za64_s16_s16_7:
> +** ...
> +** smop4s za7\.d, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za64_s16_s16_7, svint16_t, svint16x2_t,
> + svmop4s_1x2_za64_s16_s16 (7, z0, z4),
> + svmop4s_za64 (7, z0, z4));
> +
> +/*
> +** mop4s_2x1_za64_s16_s16_0:
> +** ...
> +** smop4s za0\.d, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za64_s16_s16_0, svint16x2_t, svint16_t,
> + svmop4s_2x1_za64_s16_s16 (0, z0, z4),
> + svmop4s_za64 (0, z0, z4));
> +
> +/*
> +** mop4s_2x1_za64_s16_s16_7:
> +** ...
> +** smop4s za7\.d, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za64_s16_s16_7, svint16x2_t, svint16_t,
> + svmop4s_2x1_za64_s16_s16 (7, z0, z4),
> + svmop4s_za64 (7, z0, z4));
> +
> +/*
> +** mop4s_2x2_za64_s16_s16_0:
> +** ...
> +** smop4s za0\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za64_s16_s16_0, svint16x2_t,
> + svmop4s_2x2_za64_s16_s16 (0, z0, z1),
> + svmop4s_za64 (0, z0, z1));
> +
> +/*
> +** mop4s_2x2_za64_s16_s16_7:
> +** ...
> +** smop4s za7\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za64_s16_s16_7, svint16x2_t,
> + svmop4s_2x2_za64_s16_s16 (7, z0, z1),
> + svmop4s_za64 (7, z0, z1));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_u16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_u16.c
> new file mode 100644
> index 00000000000..41479abdfdf
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_s16_u16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4s_1x1_za64_s16_u16_0:
> +** ...
> +** sumop4s za0\.d, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x1_za64_s16_u16_0, svint16_t, svuint16_t,
> + svmop4s_1x1_za64_s16_u16 (0, z0, z4),
> + svmop4s_za64 (0, z0, z4));
> +
> +/*
> +** mop4s_1x1_za64_s16_u16_7:
> +** ...
> +** sumop4s za7\.d, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x1_za64_s16_u16_7, svint16_t, svuint16_t,
> + svmop4s_1x1_za64_s16_u16 (7, z0, z4),
> + svmop4s_za64 (7, z0, z4));
> +
> +/*
> +** mop4s_1x2_za64_s16_u16_0:
> +** ...
> +** sumop4s za0\.d, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za64_s16_u16_0, svint16_t, svuint16x2_t,
> + svmop4s_1x2_za64_s16_u16 (0, z0, z4),
> + svmop4s_za64 (0, z0, z4));
> +
> +/*
> +** mop4s_1x2_za64_s16_u16_7:
> +** ...
> +** sumop4s za7\.d, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za64_s16_u16_7, svint16_t, svuint16x2_t,
> + svmop4s_1x2_za64_s16_u16 (7, z0, z4),
> + svmop4s_za64 (7, z0, z4));
> +
> +/*
> +** mop4s_2x1_za64_s16_u16_0:
> +** ...
> +** sumop4s za0\.d, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za64_s16_u16_0, svint16x2_t, svuint16_t,
> + svmop4s_2x1_za64_s16_u16 (0, z0, z4),
> + svmop4s_za64 (0, z0, z4));
> +
> +/*
> +** mop4s_2x1_za64_s16_u16_7:
> +** ...
> +** sumop4s za7\.d, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za64_s16_u16_7, svint16x2_t, svuint16_t,
> + svmop4s_2x1_za64_s16_u16 (7, z0, z4),
> + svmop4s_za64 (7, z0, z4));
> +
> +/*
> +** mop4s_2x2_za64_s16_u16_0:
> +** ...
> +** sumop4s za0\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x2_za64_s16_u16_0, svint16x2_t, svuint16x2_t,
> + svmop4s_2x2_za64_s16_u16 (0, z0, z4),
> + svmop4s_za64 (0, z0, z4));
> +
> +/*
> +** mop4s_2x2_za64_s16_u16_7:
> +** ...
> +** sumop4s za7\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x2_za64_s16_u16_7, svint16x2_t, svuint16x2_t,
> + svmop4s_2x2_za64_s16_u16 (7, z0, z4),
> + svmop4s_za64 (7, z0, z4));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_s16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_s16.c
> new file mode 100644
> index 00000000000..128a73b6d28
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_s16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4s_1x1_za64_u16_s16_0:
> +** ...
> +** usmop4s za0\.d, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x1_za64_u16_s16_0, svuint16_t, svint16_t,
> + svmop4s_1x1_za64_u16_s16 (0, z0, z4),
> + svmop4s_za64 (0, z0, z4));
> +
> +/*
> +** mop4s_1x1_za64_u16_s16_7:
> +** ...
> +** usmop4s za7\.d, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x1_za64_u16_s16_7, svuint16_t, svint16_t,
> + svmop4s_1x1_za64_u16_s16 (7, z0, z4),
> + svmop4s_za64 (7, z0, z4));
> +
> +/*
> +** mop4s_1x2_za64_u16_s16_0:
> +** ...
> +** usmop4s za0\.d, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za64_u16_s16_0, svuint16_t, svint16x2_t,
> + svmop4s_1x2_za64_u16_s16 (0, z0, z4),
> + svmop4s_za64 (0, z0, z4));
> +
> +/*
> +** mop4s_1x2_za64_u16_s16_7:
> +** ...
> +** usmop4s za7\.d, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za64_u16_s16_7, svuint16_t, svint16x2_t,
> + svmop4s_1x2_za64_u16_s16 (7, z0, z4),
> + svmop4s_za64 (7, z0, z4));
> +
> +/*
> +** mop4s_2x1_za64_u16_s16_0:
> +** ...
> +** usmop4s za0\.d, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za64_u16_s16_0, svuint16x2_t, svint16_t,
> + svmop4s_2x1_za64_u16_s16 (0, z0, z4),
> + svmop4s_za64 (0, z0, z4));
> +
> +/*
> +** mop4s_2x1_za64_u16_s16_7:
> +** ...
> +** usmop4s za7\.d, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za64_u16_s16_7, svuint16x2_t, svint16_t,
> + svmop4s_2x1_za64_u16_s16 (7, z0, z4),
> + svmop4s_za64 (7, z0, z4));
> +
> +/*
> +** mop4s_2x2_za64_u16_s16_0:
> +** ...
> +** usmop4s za0\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x2_za64_u16_s16_0, svuint16x2_t, svint16x2_t,
> + svmop4s_2x2_za64_u16_s16 (0, z0, z4),
> + svmop4s_za64 (0, z0, z4));
> +
> +/*
> +** mop4s_2x2_za64_u16_s16_7:
> +** ...
> +** usmop4s za7\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x2_za64_u16_s16_7, svuint16x2_t, svint16x2_t,
> + svmop4s_2x2_za64_u16_s16 (7, z0, z4),
> + svmop4s_za64 (7, z0, z4));
> diff --git
> a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_u16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_u16.c
> new file mode 100644
> index 00000000000..cf0ec1741e5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mop4s_za64_u16_u16.c
> @@ -0,0 +1,85 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#pragma GCC target "+sve2,+sme-mop4,+sme-i16i64"
> +#include <arm_sme.h>
> +#include "test_sme2_acle.h"
> +
> +/*
> +** mop4s_1x1_za64_u16_u16_0:
> +** ...
> +** umop4s za0\.d, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za64_u16_u16_0, svuint16_t,
> + svmop4s_1x1_za64_u16_u16 (0, z0, z1),
> + svmop4s_za64 (0, z0, z1));
> +
> +/*
> +** mop4s_1x1_za64_u16_u16_7:
> +** ...
> +** umop4s za7\.d, z0\.h, z30\.h
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_1x1_za64_u16_u16_7, svuint16_t,
> + svmop4s_1x1_za64_u16_u16 (7, z0, z1),
> + svmop4s_za64 (7, z0, z1));
> +
> +/*
> +** mop4s_1x2_za64_u16_u16_0:
> +** ...
> +** umop4s za0\.d, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za64_u16_u16_0, svuint16_t, svuint16x2_t,
> + svmop4s_1x2_za64_u16_u16 (0, z0, z4),
> + svmop4s_za64 (0, z0, z4));
> +
> +/*
> +** mop4s_1x2_za64_u16_u16_7:
> +** ...
> +** umop4s za7\.d, z0\.h, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_1x2_za64_u16_u16_7, svuint16_t, svuint16x2_t,
> + svmop4s_1x2_za64_u16_u16 (7, z0, z4),
> + svmop4s_za64 (7, z0, z4));
> +
> +/*
> +** mop4s_2x1_za64_u16_u16_0:
> +** ...
> +** umop4s za0\.d, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za64_u16_u16_0, svuint16x2_t, svuint16_t,
> + svmop4s_2x1_za64_u16_u16 (0, z0, z4),
> + svmop4s_za64 (0, z0, z4));
> +
> +/*
> +** mop4s_2x1_za64_u16_u16_7:
> +** ...
> +** umop4s za7\.d, {z0\.h - z1\.h}, z30\.h
> +** ret
> +*/
> +TEST_DUAL_ZA (mop4s_2x1_za64_u16_u16_7, svuint16x2_t, svuint16_t,
> + svmop4s_2x1_za64_u16_u16 (7, z0, z4),
> + svmop4s_za64 (7, z0, z4));
> +
> +/*
> +** mop4s_2x2_za64_u16_u16_0:
> +** ...
> +** umop4s za0\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za64_u16_u16_0, svuint16x2_t,
> + svmop4s_2x2_za64_u16_u16 (0, z0, z1),
> + svmop4s_za64 (0, z0, z1));
> +
> +/*
> +** mop4s_2x2_za64_u16_u16_7:
> +** ...
> +** umop4s za7\.d, {z0\.h - z1\.h}, {z30\.h - z31\.h}
> +** ret
> +*/
> +TEST_UNIFORM_ZA (mop4s_2x2_za64_u16_u16_7, svuint16x2_t,
> + svmop4s_2x2_za64_u16_u16 (7, z0, z1),
> + svmop4s_za64 (7, z0, z1));
> --
> 2.43.0
>
