After commit 9f8409f2e2c, SLP discovery can retry swapped operands for
commutative parents before falling back to an external scalar.
These tests can be vectorized again, so update asm check.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Expect vadd.vx,
vmul.vx, vsadd.vx and vssub.vx.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Likewise.
Signed-off-by: Zhongyao Chen <[email protected]>
---
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c | 8 ++++----
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c | 8 ++++----
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c | 8 ++++----
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c | 8 ++++----
4 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
index a1de51ba172..ddf7827ffc9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
@@ -23,19 +23,19 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T),
sat_sub, VX_BINARY_FUNC_BOD
DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor,
VX_BINARY_FUNC_BODY_X8)
DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil,
VX_BINARY_FUNC_BODY_X8)
-/* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
/* { dg-final { scan-assembler {vrsub.vx} } } */
/* { dg-final { scan-assembler {vand.vx} } } */
/* { dg-final { scan-assembler {vor.vx} } } */
/* { dg-final { scan-assembler {vxor.vx} } } */
-/* { dg-final { scan-assembler-not {vmul.vx} } } */
+/* { dg-final { scan-assembler {vmul.vx} } } */
/* { dg-final { scan-assembler {vdiv.vx} } } */
/* { dg-final { scan-assembler {vrem.vx} } } */
/* { dg-final { scan-assembler {vmax.vx} } } */
/* { dg-final { scan-assembler {vmin.vx} } } */
-/* { dg-final { scan-assembler-not {vsadd.vx} } } */
-/* { dg-final { scan-assembler-not {vssub.vx} } } */
+/* { dg-final { scan-assembler {vsadd.vx} } } */
+/* { dg-final { scan-assembler {vssub.vx} } } */
/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts {
"-mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
"-mrvv-vector-bits=zvl -mrvv-max-lmul=m2"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
index 86f9a29b5f9..e5a38fac842 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
@@ -23,19 +23,19 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T),
sat_sub, VX_BINARY_FUNC_BOD
DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor,
VX_BINARY_FUNC_BODY_X8)
DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil,
VX_BINARY_FUNC_BODY_X8)
-/* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
/* { dg-final { scan-assembler {vrsub.vx} } } */
/* { dg-final { scan-assembler {vand.vx} } } */
/* { dg-final { scan-assembler {vor.vx} } } */
/* { dg-final { scan-assembler {vxor.vx} } } */
-/* { dg-final { scan-assembler-not {vmul.vx} } } */
+/* { dg-final { scan-assembler {vmul.vx} } } */
/* { dg-final { scan-assembler {vdiv.vx} } } */
/* { dg-final { scan-assembler {vrem.vx} } } */
/* { dg-final { scan-assembler {vmax.vx} } } */
/* { dg-final { scan-assembler {vmin.vx} } } */
-/* { dg-final { scan-assembler-not {vsadd.vx} } } */
-/* { dg-final { scan-assembler-not {vssub.vx} } } */
+/* { dg-final { scan-assembler {vsadd.vx} } } */
+/* { dg-final { scan-assembler {vssub.vx} } } */
/* { dg-final { scan-assembler {vaadd.vx} { target { no-opts {
"-mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
"-mrvv-vector-bits=zvl -mrvv-max-lmul=m2"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index 58730d0a0d4..8334e6fc44a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -23,19 +23,19 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T),
sat_sub, VX_BINARY_FUNC_BOD
DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor,
VX_BINARY_FUNC_BODY_X8)
DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil,
VX_BINARY_FUNC_BODY_X8)
-/* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
/* { dg-final { scan-assembler {vrsub.vx} } } */
/* { dg-final { scan-assembler {vand.vx} } } */
/* { dg-final { scan-assembler {vor.vx} } } */
/* { dg-final { scan-assembler {vxor.vx} } } */
-/* { dg-final { scan-assembler-not {vmul.vx} } } */
+/* { dg-final { scan-assembler {vmul.vx} } } */
/* { dg-final { scan-assembler {vdiv.vx} } } */
/* { dg-final { scan-assembler {vrem.vx} } } */
/* { dg-final { scan-assembler {vmax.vx} } } */
/* { dg-final { scan-assembler {vmin.vx} } } */
-/* { dg-final { scan-assembler-not {vsadd.vx} } } */
-/* { dg-final { scan-assembler-not {vssub.vx} } } */
+/* { dg-final { scan-assembler {vsadd.vx} } } */
+/* { dg-final { scan-assembler {vssub.vx} } } */
/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts {
"-mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
"-mrvv-vector-bits=zvl -mrvv-max-lmul=m2"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index f1eece7266f..f1d7663b961 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -23,19 +23,19 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T),
sat_sub, VX_BINARY_FUNC_BOD
DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor,
VX_BINARY_FUNC_BODY_X8)
DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil,
VX_BINARY_FUNC_BODY_X8)
-/* { dg-final { scan-assembler-not {vadd.vx} } } */
+/* { dg-final { scan-assembler {vadd.vx} } } */
/* { dg-final { scan-assembler {vsub.vx} } } */
/* { dg-final { scan-assembler {vrsub.vx} } } */
/* { dg-final { scan-assembler {vand.vx} } } */
/* { dg-final { scan-assembler {vor.vx} } } */
/* { dg-final { scan-assembler {vxor.vx} } } */
-/* { dg-final { scan-assembler-not {vmul.vx} } } */
+/* { dg-final { scan-assembler {vmul.vx} } } */
/* { dg-final { scan-assembler {vdiv.vx} } } */
/* { dg-final { scan-assembler {vrem.vx} } } */
/* { dg-final { scan-assembler {vmax.vx} } } */
/* { dg-final { scan-assembler {vmin.vx} } } */
-/* { dg-final { scan-assembler-not {vsadd.vx} } } */
-/* { dg-final { scan-assembler-not {vssub.vx} } } */
+/* { dg-final { scan-assembler {vsadd.vx} } } */
+/* { dg-final { scan-assembler {vssub.vx} } } */
/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts {
"-mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
"-mrvv-vector-bits=zvl -mrvv-max-lmul=m2"
--
2.43.0
