From: Ezra Sitorus <[email protected]>
This patch adds support for FEAT_F16F32MM, FEAT_F16MM and FEAT_SVE_B16MM
intrinsics.
gcc/ChangeLog:
* config/aarch64/aarch64-c.cc: Add new __ARM_FEATURE__ macros.
* config/aarch64/aarch64-simd-builtins.def (fmmlaqv8hf, fmmlaqv4sf):
Define.
* config/aarch64/aarch64-simd-pragma-builtins.def (vmmlaq_f32_f16,
vmmlaq_f16_f16): Add new intrinsics.
* config/aarch64/aarch64-simd.md (@aarch64_fmmlaq<mode>): New
pattern.
* config/aarch64/aarch64-sve-builtins-base.cc: Update
svmmla_impl::expand for new instructions.
* config/aarch64/aarch64-sve-builtins-sve2.def (svmmla): Add new
intrinsics.
* config/aarch64/aarch64-sve2.md
(@aarch64_sve2_fmmla<SVE_FULL_HF_FMMLA:mode><SVE_FULL_HF_FMMLA:mode>):
New pattern.
* config/aarch64/aarch64.h (TARGET_F16F32MM, TARGET_F16MM,
TARGET_SVE_B16MM): New macro.
* config/aarch64/arm_neon.h (vmmlaq_f32_f16): New intrinsic.
(vmmlaq_f16_f16): Likewise.
* config/aarch64/iterators.md (VDQ_HSF_HF_FMMLA): New iterator.
(SVE_FULL_HF_FMMLA): Likewise.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp ("f16mm", "f16f32mm", "sve-b16mm"):
Add new extensions.
* gcc.target/aarch64/advsimd-intrinsics/fmmla-compile.c: New
test.
* gcc.target/aarch64/pragma_cpp_predefs_4.c: Test new feature
macros.
* gcc.target/aarch64/sve/acle/general-c/mmla_1.c: Remove test
that now works.
* gcc.target/aarch64/sve2/acle/asm/fmmla_bf16mm_sve2.c: New
test.
* gcc.target/aarch64/sve2/acle/asm/fmmla_f16mm_sve2.c: New test.
---
gcc/config/aarch64/aarch64-c.cc | 3 +++
gcc/config/aarch64/aarch64-simd-builtins.def | 6 +++++
.../aarch64/aarch64-simd-pragma-builtins.def | 10 +++++++
gcc/config/aarch64/aarch64-simd.md | 12 +++++++++
.../aarch64/aarch64-sve-builtins-base.cc | 8 +++++-
.../aarch64/aarch64-sve-builtins-sve2.def | 10 +++++++
gcc/config/aarch64/aarch64-sve2.md | 23 ++++++++++++++++
gcc/config/aarch64/aarch64.h | 6 +++++
gcc/config/aarch64/arm_neon.h | 14 ++++++++++
gcc/config/aarch64/iterators.md | 7 +++++
.../advsimd-intrinsics/fmmla-compile.c | 26 ++++++++++++++++++
.../gcc.target/aarch64/pragma_cpp_predefs_4.c | 15 +++++++++++
.../aarch64/sve/acle/general-c/mmla_1.c | 1 -
.../aarch64/sve2/acle/asm/fmmla_bf16mm_sve2.c | 27 +++++++++++++++++++
.../aarch64/sve2/acle/asm/fmmla_f16mm_sve2.c | 27 +++++++++++++++++++
gcc/testsuite/lib/target-supports.exp | 2 +-
16 files changed, 194 insertions(+), 3 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/fmmla-compile.c
create mode 100644
gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/fmmla_bf16mm_sve2.c
create mode 100644
gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/fmmla_f16mm_sve2.c
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index 2168dbf6c85..dfc96016996 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -347,6 +347,9 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
aarch64_def_or_undef (TARGET_F8F16MM, "__ARM_FEATURE_F8F16MM", pfile);
aarch64_def_or_undef (TARGET_F8F32MM, "__ARM_FEATURE_F8F32MM", pfile);
+ aarch64_def_or_undef (TARGET_F16MM, "__ARM_FEATURE_F16MM", pfile);
+ aarch64_def_or_undef (TARGET_F16F32MM, "__ARM_FEATURE_F16F32MM", pfile);
+ aarch64_def_or_undef (TARGET_SVE_B16MM, "__ARM_FEATURE_SVE_B16MM", pfile);
aarch64_def_or_undef (TARGET_SVE_F16F32MM, "__ARM_FEATURE_SVE_F16F32MM",
pfile);
}
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def
b/gcc/config/aarch64/aarch64-simd-builtins.def
index 5b5c17a7f3a..703ef79b515 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -962,6 +962,12 @@
VAR1 (QUADOP_LANE_PAIR, simdfdot_lane, 0, QUIET, v2sf)
VAR1 (QUADOP_LANE_PAIR, simdfdot_laneq, 0, QUIET, v4sf)
+ /* Implemented by aarch64_fmmlaqv8hf */
+ VAR1 (TERNOP, fmmlaq, 0, QUIET, v8hf)
+
+ /* Implemented by aarch64_fmmlaqv4sf */
+ VAR1 (TERNOP, fmmlaq, 0, QUIET, v4sf)
+
/* Implemented by aarch64_bfmmlaqv4sf */
VAR1 (TERNOP, bfmmlaq, 0, QUIET, v4sf)
diff --git a/gcc/config/aarch64/aarch64-simd-pragma-builtins.def
b/gcc/config/aarch64/aarch64-simd-pragma-builtins.def
index 41bafb2a96e..ee7ebcb3a09 100644
--- a/gcc/config/aarch64/aarch64-simd-pragma-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-pragma-builtins.def
@@ -306,6 +306,16 @@ ENTRY_TERNARY (vmmlaq_f16_mf8, f16q, f16q, mf8q, mf8q,
UNSPEC_FMMLA, FP8)
ENTRY_TERNARY (vmmlaq_f32_mf8, f32q, f32q, mf8q, mf8q, UNSPEC_FMMLA, FP8)
#undef REQUIRED_EXTENSIONS
+// mmla f32 f16
+#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_F16F32MM)
+ENTRY_TERNARY (vmmlaq_f32_f16, f32q, f32q, f16q, f16q, UNSPEC_FMMLA, QUIET)
+#undef REQUIRED_EXTENSIONS
+
+// mmla f16 f16
+#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_F16MM)
+ENTRY_TERNARY (vmmlaq_f16_f16, f16q, f16q, f16q, f16q, UNSPEC_FMMLA, QUIET)
+#undef REQUIRED_EXTENSIONS
+
// mov
#define REQUIRED_EXTENSIONS nonstreaming_only (AARCH64_FL_SIMD)
ENTRY_UNARY (vmov_n_mf8, mf8, mf8_scalar, UNSPEC_DUP, QUIET)
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index 8a5059f4ec1..1a197ae820e 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -10689,6 +10689,18 @@
[(set_attr "type" "neon_fp_mla_s_q")]
)
+;; fmmla
+(define_insn "@aarch64_fmmlaq<mode>"
+ [(set (match_operand:VDQ_HSF_HF_FMMLA 0 "register_operand" "=w")
+ (plus:VDQ_HSF_HF_FMMLA (match_operand:VDQ_HSF_HF_FMMLA 1
"register_operand" "0")
+ (unspec:VDQ_HSF_HF_FMMLA [(match_operand:V8HF 2
"register_operand" "w")
+ (match_operand:V8HF 3 "register_operand" "w")]
+ UNSPEC_FMMLA)))]
+ ""
+ "fmmla\t%0.<Vtype>, %2.8h, %3.8h"
+ [(set_attr "type" "neon_fp_mla_s_q")]
+)
+
;; bfmlal<bt>
(define_insn "aarch64_bfmlal<bt>v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=w")
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
index 212002574e8..d2627ab1831 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
@@ -2327,7 +2327,13 @@ public:
else
{
if (e.type_suffix_ids[1] == NUM_TYPE_SUFFIXES)
- icode = code_for_aarch64_sve (UNSPEC_FMMLA, e.vector_mode (0));
+ {
+ if (e.type_suffix (0).element_bytes == 2)
+ icode = code_for_aarch64_sve2_fmmla (e.vector_mode (0),
+ e.vector_mode (0));
+ else
+ icode = code_for_aarch64_sve (UNSPEC_FMMLA, e.vector_mode (0));
+ }
else
icode = code_for_aarch64_sve2 (UNSPEC_FMMLA,
e.vector_mode (0),
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
index 5c348bbb1d8..88d8eabfb24 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
@@ -492,6 +492,16 @@ DEF_SVE_FUNCTION_GS_FPM (svmmla, mmla, s_float_mf8, none,
none, set)
DEF_SVE_FUNCTION (svmmla, mmla, cvt_f32_f16, none)
#undef REQUIRED_EXTENSIONS
+#define REQUIRED_EXTENSIONS \
+ nonstreaming_sve (AARCH64_FL_SVE_B16MM)
+DEF_SVE_FUNCTION_GS (svmmla, mmla, h_bfloat, none, none)
+#undef REQUIRED_EXTENSIONS
+
+#define REQUIRED_EXTENSIONS \
+ nonstreaming_sve (AARCH64_FL_F16MM)
+DEF_SVE_FUNCTION_GS (svmmla, mmla, h_float, none, none)
+#undef REQUIRED_EXTENSIONS
+
/*
- BFSCALE (predicated)
// Only if __ARM_FEATURE_SVE_BFSCALE != 0 && __ARM_FEATURE_SVE2 != 0
diff --git a/gcc/config/aarch64/aarch64-sve2.md
b/gcc/config/aarch64/aarch64-sve2.md
index a0713633e28..3c9754707bf 100644
--- a/gcc/config/aarch64/aarch64-sve2.md
+++ b/gcc/config/aarch64/aarch64-sve2.md
@@ -144,6 +144,7 @@
;;
;; == FMMLA extensions
;; ---- [FP] Matrix multiply-accumulate widening
+;; ---- [FP] Matrix multiply-accumulate non-widening
;; =========================================================================
;; == Moves
@@ -5098,3 +5099,25 @@
}
[(set_attr "sve_type" "sve_fp_mul")]
)
+
+;; -------------------------------------------------------------------------
+;; ---- [FP] Matrix multiply-accumulate non-widening
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - FMMLA (F16MM)
+;; - BFMMLA (SVE_B16MM)
+;; -------------------------------------------------------------------------
+
+(define_insn
"@aarch64_sve2_fmmla<SVE_FULL_HF_FMMLA:mode><SVE_FULL_HF_FMMLA:mode>"
+ [(set (match_operand:SVE_FULL_HF_FMMLA 0 "register_operand")
+ (unspec:SVE_FULL_HF_FMMLA
+ [(match_operand:SVE_FULL_HF_FMMLA 2 "register_operand")
+ (match_operand:SVE_FULL_HF_FMMLA 3 "register_operand")
+ (match_operand:SVE_FULL_HF_FMMLA 1 "register_operand")]
+ FMMLA))]
+ "TARGET_SVE2 && TARGET_NON_STREAMING"
+ {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ]
+ [ w , 0 , w , w ; * ] <b>fmmla\t%0.h, %2.h, %3.h
+ }
+ [(set_attr "sve_type" "sve_fp_mul")]
+)
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 4c8ccd11eb2..1131a86c461 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -447,10 +447,16 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE
ATTRIBUTE_UNUSED
#define TARGET_F8F32MM (AARCH64_HAVE_ISA (F8F32MM))
/* F8F16MM instructions, enabled through +f8f16mm. */
#define TARGET_F8F16MM (AARCH64_HAVE_ISA (F8F16MM))
+/* F16F32MM instructions, enabled through +f16f32mm. */
+#define TARGET_F16F32MM (AARCH64_HAVE_ISA (F16F32MM))
+/* F16MM instructions, enabled through +f16mm. */
+#define TARGET_F16MM (AARCH64_HAVE_ISA (F16MM))
/* SVE_F16F32MM instructions, enabled through +sve-f16f32mm. */
#define TARGET_SVE_F16F32MM (AARCH64_HAVE_ISA (SVE_F16F32MM))
/* F16F32DOT instructions enabled through +f16f32dot. */
#define TARGET_F16F32DOT (AARCH64_HAVE_ISA (F16F32DOT))
+/* SVE_B16MM instructions, enabled through +sve-b16mm. */
+#define TARGET_SVE_B16MM (AARCH64_HAVE_ISA (SVE_B16MM))
/* Make sure this is always defined so we don't have to check for ifdefs
but rather use normal ifs. */
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 1cd905d6b7d..31a9e50caa1 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -26789,6 +26789,20 @@ vminnmvq_f16 (float16x8_t __a)
return __builtin_aarch64_reduc_smin_scal_v8hf (__a);
}
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vmmlaq_f32_f16 (float32x4_t __r, float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_aarch64_fmmlaqv4sf (__r, __a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vmmlaq_f16_f16 (float16x8_t __r, float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_aarch64_fmmlaqv8hf (__r, __a, __b);
+}
+
#pragma GCC pop_options
/* AdvSIMD Dot Product intrinsics. */
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index d35470e6fe2..63132f39ab1 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -220,6 +220,10 @@
(V2SF "TARGET_FP8DOT4")
(V4SF "TARGET_FP8DOT4")])
+;; Same, but with the appropriate conditions for FMMLA support with FP16
source.
+(define_mode_iterator VDQ_HSF_HF_FMMLA [(V8HF "TARGET_F16MM")
+ (V4SF "TARGET_F16F32MM")])
+
(define_mode_iterator VDQ_HSF_FMMLA [(V8HF "TARGET_F8F16MM")
(V4SF "TARGET_F8F32MM")])
@@ -578,6 +582,9 @@
;; Fully-packed SVE vector modes that have 16-bit float elements.
(define_mode_iterator SVE_FULL_HF [VNx8BF VNx8HF])
+;; Same, but with the appropriate conditions for FMMLA support.
+(define_mode_iterator SVE_FULL_HF_FMMLA [(VNx8BF "TARGET_SVE_B16MM") (VNx8HF
"TARGET_F16MM")])
+
;; Pairs of the above.
(define_mode_iterator SVE_FULL_HFx2 [VNx16BF VNx16HF])
diff --git
a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/fmmla-compile.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/fmmla-compile.c
new file mode 100644
index 00000000000..13d3b1b0223
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/fmmla-compile.c
@@ -0,0 +1,26 @@
+/* { dg-do assemble { target { aarch64_asm_f16f32mm_ok && aarch64_asm_f16mm_ok
} } } */
+/* { dg-do compile { target { ! { aarch64_asm_f16f32mm_ok &&
aarch64_asm_f16mm_ok } } } } */
+/* { dg-additional-options "-O2 -march=armv8-a+f16f32mm+f16mm -save-temps" } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include <arm_neon.h>
+
+/*
+**test_fmmla1:
+** fmmla v0.4s, v1.8h, v2.8h
+** ret
+*/
+float32x4_t test_fmmla1 (float32x4_t r, float16x8_t x, float16x8_t y)
+{
+ return vmmlaq_f32_f16 (r, x, y);
+}
+
+/*
+**test_fmmla2:
+** fmmla v0.8h, v1.8h, v2.8h
+** ret
+*/
+float16x8_t test_fmmla2 (float16x8_t r, float16x8_t x, float16x8_t y)
+{
+ return vmmlaq_f16_f16 (r, x, y);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
index cb009ec2752..aa8aaf190ee 100644
--- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
@@ -394,6 +394,21 @@
#error Foo
#endif
+#pragma GCC target "+nothing+f16mm"
+#ifndef __ARM_FEATURE_F16MM
+#error Foo
+#endif
+
+#pragma GCC target "+nothing+f16f32mm"
+#ifndef __ARM_FEATURE_F16F32MM
+#error Foo
+#endif
+
+#pragma GCC target "+nothing+sve-b16mm"
+#ifndef __ARM_FEATURE_SVE_B16MM
+#error Foo
+#endif
+
#pragma GCC target "arch=armv9.5-a+sme"
#ifdef __ARM_FEATURE_SME_TMOP
#error Foo
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mmla_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mmla_1.c
index a23c45c86b1..c616ad425c4 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mmla_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/mmla_1.c
@@ -52,7 +52,6 @@ f2 (svbool_t pg, svint8_t s8, svuint8_t u8, svuint32_t u32,
svint32_t s32,
svmmla (f64, f32, f16); /* { dg-error {'svmmla' has no form that takes
'svfloat64_t' and 'svfloat32_t' arguments} } */
svmmla (f64, f64, f16); /* { dg-error {passing 'svfloat16_t' to argument 3
of 'svmmla', but argument 2 had type 'svfloat64_t'} } */
- svmmla (f16, f16, f16); /* { dg-error {'svmmla' has no form that takes
'svfloat16_t' arguments} } */
svmmla (f32, f32, f32);
svmmla (f64, f64, f64);
}
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/fmmla_bf16mm_sve2.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/fmmla_bf16mm_sve2.c
new file mode 100644
index 00000000000..0539a351530
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/fmmla_bf16mm_sve2.c
@@ -0,0 +1,27 @@
+/* { dg-do assemble { target aarch64_asm_sve-b16mm_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sve-b16mm_ok } } } */
+/* { dg-skip-if "" { *-*-* } { "-DSTREAMING_COMPATIBLE" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+
+#pragma GCC target "+sve+sve-b16mm"
+
+/*
+** svmmla_bf16mm_tied:
+** bfmmla z0\.h, z4\.h, z5\.h
+** ret
+*/
+TEST_DUAL_Z (svmmla_bf16mm_tied, svbfloat16_t, svbfloat16_t,
+ z0 = svmmla_bf16 (z0, z4, z5),
+ z0 = svmmla (z0, z4, z5))
+
+/*
+** svmmla_bf16mm:
+** bfmmla z1\.h, z4\.h, z5\.h
+** mov z0\.d, z1\.d
+** ret
+*/
+TEST_DUAL_Z (svmmla_bf16mm, svbfloat16_t, svbfloat16_t,
+ z0 = svmmla_bf16 (z1, z4, z5),
+ z0 = svmmla (z1, z4, z5))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/fmmla_f16mm_sve2.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/fmmla_f16mm_sve2.c
new file mode 100644
index 00000000000..efa4f96481b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/fmmla_f16mm_sve2.c
@@ -0,0 +1,27 @@
+/* { dg-do assemble { target aarch64_asm_f16mm_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_f16mm_ok } } } */
+/* { dg-skip-if "" { *-*-* } { "-DSTREAMING_COMPATIBLE" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+
+#pragma GCC target "+sve+f16mm"
+
+/*
+** svmmla_f16mm_tied:
+** fmmla z0\.h, z4\.h, z5\.h
+** ret
+*/
+TEST_DUAL_Z (svmmla_f16mm_tied, svfloat16_t, svfloat16_t,
+ z0 = svmmla_f16 (z0, z4, z5),
+ z0 = svmmla (z0, z4, z5))
+
+/*
+** svmmla_f16mm:
+** fmmla z1\.h, z4\.h, z5\.h
+** mov z0\.d, z1\.d
+** ret
+*/
+TEST_DUAL_Z (svmmla_f16mm, svfloat16_t, svfloat16_t,
+ z0 = svmmla_f16 (z1, z4, z5),
+ z0 = svmmla (z1, z4, z5))
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index ad7ba8ba213..c34814ca76a 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -12878,7 +12878,7 @@ set exts {
"bf16" "cmpbr" "crc" "crypto" "dotprod" "f32mm" "f64mm" "faminmax"
"fp" "fp8" "fp8dot2" "fp8dot4" "fp8fma" "i8mm" "ls64" "lse" "lut"
"sb" "simd" "sve-b16b16" "sve" "sve2" "sve2p3" "sve-sm4" "sve-aes"
"sve-bitperm"
- "sve-sha3" "f8f16mm" "f8f32mm" "sve-f16f32mm"
+ "sve-sha3" "f8f16mm" "f8f32mm" "sve-f16f32mm" "f16mm" "f16f32mm"
"sve-b16mm"
"sme-f8f16" "sme-f8f32"
"sme-b16b16" "sme-f16f16" "sme-i16i64" "sme" "sme2" "sme2p1" "sme2p2"
"sme2p3"
"ssve-fp8dot2" "ssve-fp8dot4" "ssve-fp8fma" "sve-bfscale" "sme-lutv2"
--
2.53.0
