On 6/15/2026 9:35 AM, Robin Dapp wrote:
Hi,
In the PR we ICE during vsetvl, expecting a register in the VL operand
slot which only contains an immediate 4. Non-VLMAX insns with immediate
length have a NULL_RTX in that slot.
However, during a split, we erroneously use operand[5] instead of
operand[6]. operand[5] is the mask policy and happened to be "1".
"1" indicates a VLMAX insn in the avl_type operand. This caused the
wrong turn in vsetvl.
The patch just corrects the operand number.
Regtested on rv64gcv_zvl512b. Going to wait for the CI.
Regards
Robin
PR target/125670
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Use avl_type operand number.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr125670.c: New test.
Looks like the CI system is down, so I spun this overnight on mine. It's
clean and I pushed it to the trunk.
Jeff
