Hi Jeff , On 4/23/26 03:19, Jeffrey Law wrote: > > On 4/22/2026 4:35 AM, Kito Cheng wrote: >>> diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md >>> index 37f15d816595..8ccdbe8fb0ed 100644 >>> --- a/gcc/config/riscv/sync.md >>> +++ b/gcc/config/riscv/sync.md >>> @@ -605,7 +605,8 @@ >>> value is sign-extended. */ >>> rtx tmp0 = gen_reg_rtx (word_mode); >>> emit_insn (gen_extend_insn (tmp0, operands[3], word_mode, >>> <MODE>mode, 0)); >>> - operands[3] = gen_lowpart (<MODE>mode, tmp0); >>> + poly_int64 offset = BYTES_BIG_ENDIAN ? GET_MODE_SIZE (<MODE>mode) : >>> 0; >>> + operands[3] = simplify_gen_subreg (<MODE>mode, tmp0, word_mode, >>> offset); >> As Jeff mention before, I also try to trace gen_lowpart, it seems >> already handle big-endian? >> Do we really this fix? If so does it mean we should not use >> gen_lowpart at all for big-endian? >> I guess the answer should be no, but I am not sure why we need this here? > It seems like it's papering over a problem elsewhere. If you want the > lowpart, then gen_lowpart is the way to do that, even for big endian. > This was an issue on GCC 14 and I was not able to reproduce this on newer builds. Dropping this patch.
Best regards, Aleksa
