Hi! (resending this as it doesnt seem to have made it to the list)
On 23/06/2026 10:52, Robin Dapp wrote:
>> AArch64 first faulting reads are safe to execute speculatively
because the
>> hardware is able to return less than a full vector read.
>>
>> The loads (both "first faulting" (FF) and "non-faulting" (NF)) set a
predicate
>> register (first fault register) with a mask of loaded elements.
>
> Just interrupting here right away without having read the rest 🙂
>
> Is this (the content of the predicate register) actually a length?
> (i.e. AND-masked with your regular loop/predicate mask?)
Yes exactly that
>
> I would hope it is, at least conceptually.
>
> For riscv there is no dedicated FoF state, a FoF load just sets the
vector
> length to a value potentially lower than before. It can be read by a
control
> register if needed.
>
> I'm just wondering if there is any benefit (for comprehension and
otherwise) of
> treating it as a length as well for aarch64?
>
Possibly, though I cant quite imagine how that would work.
We are already going to need to treat riscv and aarch64 differently as
aarch64 has ffr partial reads whenever the hardware likes, whereas (from
my understanding) riscv does not, and only does a partial read at a
genuine fault boundary.
To handle the aarch64 spurious partial reads this patch series repeats
the partial iteration with the previously successfully loaded elements
masked out by inverting the returned ffr mask. So we do use the "mask"
nature of this more than just a length?
I don't think anything like that would be necessary for riscv or len
based vector targets as we never really have to deal with the next
iteration as it should be a genuine fault boundary so either the program
will take the early break, or the next iteration is a genuine fault.
