This patch adds support for the following absolute difference accumulation
intrinsics defined by SVE/SME2.3:
* svabal_s16
* svabal_n_s16
* svabal_s32
* svabal_n_s32
* svabal_s64
* svabal_n_s64
* svabal_u16
* svabal_n_u16
* svabal_u32
* svabal_n_u32
* svabal_u64
* svabal_n_u64
gcc/ChangeLog:
* config/aarch64/aarch64-sve-builtins-sve2.cc (svabal): Define.
* config/aarch64/aarch64-sve-builtins-sve2.def (svabal): New
function.
* config/aarch64/aarch64-sve-builtins-sve2.h (svabal): Declare.
* config/aarch64/iterators.md (UNSPEC_SABAL): New unspec.
(UNSPEC_UABAL): Likewise.
(SVE2_INT_BINARY_LONG): Add UNSPEC_SABAL and UNSPEC_UABAL.
(SVE2_INT_ADD_BINARY_LONG): Likewise.
(sve_int_op): Add sabal and uabal mappings.
(sve_int_add_op): Likewise.
(sve_type_unspec): Add UNSPEC_SABAL and UNSPEC_UABAL.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve2/acle/asm/abal_s16.c: New test.
* gcc.target/aarch64/sve2/acle/asm/abal_s32.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/abal_s64.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/abal_u16.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/abal_u32.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/abal_u64.c: Likewise.
---
.../aarch64/aarch64-sve-builtins-sve2.cc | 2 +
.../aarch64/aarch64-sve-builtins-sve2.def | 4 +
.../aarch64/aarch64-sve-builtins-sve2.h | 1 +
gcc/config/aarch64/iterators.md | 18 +++-
.../aarch64/sve2/acle/asm/abal_s16.c | 90 +++++++++++++++++++
.../aarch64/sve2/acle/asm/abal_s32.c | 90 +++++++++++++++++++
.../aarch64/sve2/acle/asm/abal_s64.c | 90 +++++++++++++++++++
.../aarch64/sve2/acle/asm/abal_u16.c | 90 +++++++++++++++++++
.../aarch64/sve2/acle/asm/abal_u32.c | 90 +++++++++++++++++++
.../aarch64/sve2/acle/asm/abal_u64.c | 90 +++++++++++++++++++
gcc/testsuite/lib/target-supports.exp | 4 +-
11 files changed, 564 insertions(+), 5 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s16.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s32.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s64.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u16.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u32.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u64.c
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
index 5ea08056ae3..857c37e7ba6 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
@@ -1022,6 +1022,8 @@ public:
namespace aarch64_sve {
FUNCTION (svaba, svaba_impl,)
+FUNCTION (svabal, unspec_based_add_function, (UNSPEC_SABAL,
+ UNSPEC_UABAL, -1))
FUNCTION (svabalb, unspec_based_add_function, (UNSPEC_SABDLB,
UNSPEC_UABDLB, -1))
FUNCTION (svabalt, unspec_based_add_function, (UNSPEC_SABDLT,
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
index 1a55de890cf..9f1b3c69f34 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
@@ -315,6 +315,10 @@ DEF_SVE_FUNCTION (svrint64x, unary, sd_float, mxz)
DEF_SVE_FUNCTION (svrint64z, unary, sd_float, mxz)
#undef REQUIRED_EXTENSIONS
+#define REQUIRED_EXTENSIONS sve_and_sme (AARCH64_FL_SVE2p3, AARCH64_FL_SME2p3)
+DEF_SVE_FUNCTION (svabal, ternary_long_opt_n, hsd_integer, none)
+#undef REQUIRED_EXTENSIONS
+
#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2)
DEF_SVE_FUNCTION_GS (svadd, binary_single, all_integer, x24, none)
DEF_SVE_FUNCTION_GS (svclamp, clamp, all_arith, x24, none)
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
index b2f2698b880..33b4298a404 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
@@ -25,6 +25,7 @@ namespace aarch64_sve
namespace functions
{
extern const function_base *const svaba;
+ extern const function_base *const svabal;
extern const function_base *const svabalb;
extern const function_base *const svabalt;
extern const function_base *const svabdlb;
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 2d1522a348a..6799b55d552 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -1172,6 +1172,7 @@
UNSPEC_RSHRNT ; Used in aarch64-sve2.md.
UNSPEC_RSUBHNB ; Used in aarch64-sve2.md.
UNSPEC_RSUBHNT ; Used in aarch64-sve2.md.
+ UNSPEC_SABAL ; Used in aarch64-sve2.md.
UNSPEC_SABDLB ; Used in aarch64-sve2.md.
UNSPEC_SABDLT ; Used in aarch64-sve2.md.
UNSPEC_SADDLB ; Used in aarch64-sve2.md.
@@ -1230,6 +1231,7 @@
UNSPEC_SUBHNT ; Used in aarch64-sve2.md.
UNSPEC_TBL2 ; Used in aarch64-sve2.md.
UNSPEC_TRN ; Used in aarch64-builtins.cc
+ UNSPEC_UABAL ; Used in aarch64-sve2.md.
UNSPEC_UABDLB ; Used in aarch64-sve2.md.
UNSPEC_UABDLT ; Used in aarch64-sve2.md.
UNSPEC_UADDLB ; Used in aarch64-sve2.md.
@@ -3958,7 +3960,8 @@
(define_int_iterator SVE2_INT_BINARY_LANE [UNSPEC_SQDMULH
UNSPEC_SQRDMULH])
-(define_int_iterator SVE2_INT_BINARY_LONG [UNSPEC_SABDLB
+(define_int_iterator SVE2_INT_BINARY_LONG [UNSPEC_SABAL
+ UNSPEC_SABDLB
UNSPEC_SABDLT
UNSPEC_SADDLB
UNSPEC_SADDLBT
@@ -3971,6 +3974,7 @@
UNSPEC_SSUBLBT
UNSPEC_SSUBLT
UNSPEC_SSUBLTB
+ UNSPEC_UABAL
UNSPEC_UABDLB
UNSPEC_UABDLT
UNSPEC_UADDLB
@@ -4114,10 +4118,12 @@
UNSPEC_CDOT180
UNSPEC_CDOT270])
-(define_int_iterator SVE2_INT_ADD_BINARY_LONG [UNSPEC_SABDLB
+(define_int_iterator SVE2_INT_ADD_BINARY_LONG [UNSPEC_SABAL
+ UNSPEC_SABDLB
UNSPEC_SABDLT
UNSPEC_SMULLB
UNSPEC_SMULLT
+ UNSPEC_UABAL
UNSPEC_UABDLB
UNSPEC_UABDLT
UNSPEC_UMULLB
@@ -4902,6 +4908,7 @@
(UNSPEC_RSQRTE "ursqrte")
(UNSPEC_RSUBHNB "rsubhnb")
(UNSPEC_RSUBHNT "rsubhnt")
+ (UNSPEC_SABAL "sabal")
(UNSPEC_SABDLB "sabdlb")
(UNSPEC_SABDLT "sabdlt")
(UNSPEC_SADALP "sadalp")
@@ -4971,6 +4978,7 @@
(UNSPEC_SUBHNB "subhnb")
(UNSPEC_SUBHNT "subhnt")
(UNSPEC_SUQADD "suqadd")
+ (UNSPEC_UABAL "uabal")
(UNSPEC_UABDLB "uabdlb")
(UNSPEC_UABDLT "uabdlt")
(UNSPEC_UADALP "uadalp")
@@ -5021,10 +5029,12 @@
(UNSPEC_URHADD "urhadd")
(UNSPEC_URSHL "urshlr")])
-(define_int_attr sve_int_add_op [(UNSPEC_SABDLB "sabalb")
+(define_int_attr sve_int_add_op [(UNSPEC_SABAL "sabal")
+ (UNSPEC_SABDLB "sabalb")
(UNSPEC_SABDLT "sabalt")
(UNSPEC_SMULLB "smlalb")
(UNSPEC_SMULLT "smlalt")
+ (UNSPEC_UABAL "uabal")
(UNSPEC_UABDLB "uabalb")
(UNSPEC_UABDLT "uabalt")
(UNSPEC_UMULLB "umlalb")
@@ -5089,6 +5099,7 @@
(UNSPEC_SBCLT "int_general")
(UNSPEC_SQRDMLAH "int_mul")
(UNSPEC_SQRDMLSH "int_mul")
+ (UNSPEC_SABAL "int_general")
(UNSPEC_SABDLB "int_general")
(UNSPEC_SABDLT "int_general")
(UNSPEC_SADDLB "int_general")
@@ -5103,6 +5114,7 @@
(UNSPEC_SSUBLBT "int_general")
(UNSPEC_SSUBLT "int_general")
(UNSPEC_SSUBLTB "int_general")
+ (UNSPEC_UABAL "int_general")
(UNSPEC_UABDLB "int_general")
(UNSPEC_UABDLT "int_general")
(UNSPEC_UADDLB "int_general")
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s16.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s16.c
new file mode 100644
index 00000000000..e1685296455
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s16.c
@@ -0,0 +1,90 @@
+/* { dg-do assemble { target aarch64_asm_sve2p3_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sve2p3_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+#pragma GCC target "+sve2p3"
+#pragma GCC target "+sme2p3"
+
+/*
+** abal_s16_tied1:
+** sabal z0\.h, z4\.b, z5\.b
+** ret
+*/
+TEST_DUAL_Z (abal_s16_tied1, svint16_t, svint8_t,
+ z0 = svabal_s16 (z0, z4, z5),
+ z0 = svabal (z0, z4, z5))
+
+/*
+** abal_s16_tied2:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** sabal z0\.h, \1\.b, z1\.b
+** ret
+*/
+TEST_DUAL_Z_REV (abal_s16_tied2, svint16_t, svint8_t,
+ z0_res = svabal_s16 (z4, z0, z1),
+ z0_res = svabal (z4, z0, z1))
+
+/*
+** abal_s16_tied3:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** sabal z0\.h, z1\.b, \1\.b
+** ret
+*/
+TEST_DUAL_Z_REV (abal_s16_tied3, svint16_t, svint8_t,
+ z0_res = svabal_s16 (z4, z1, z0),
+ z0_res = svabal (z4, z1, z0))
+
+/*
+** abal_s16_untied:
+** movprfx z0, z1
+** sabal z0\.h, z4\.b, z5\.b
+** ret
+*/
+TEST_DUAL_Z (abal_s16_untied, svint16_t, svint8_t,
+ z0 = svabal_s16 (z1, z4, z5),
+ z0 = svabal (z1, z4, z5))
+
+/*
+** abal_w0_s16_tied1:
+** mov (z[0-9]+\.b), w0
+** sabal z0\.h, z4\.b, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_s16_tied1, svint16_t, svint8_t, int8_t,
+ z0 = svabal_n_s16 (z0, z4, x0),
+ z0 = svabal (z0, z4, x0))
+
+/*
+** abal_w0_s16_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.b), w0
+** movprfx z0, z1
+** sabal z0\.h, z4\.b, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_s16_untied, svint16_t, svint8_t, int8_t,
+ z0 = svabal_n_s16 (z1, z4, x0),
+ z0 = svabal (z1, z4, x0))
+
+/*
+** abal_11_s16_tied1:
+** mov (z[0-9]+\.b), #11
+** sabal z0\.h, z4\.b, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_s16_tied1, svint16_t, svint8_t,
+ z0 = svabal_n_s16 (z0, z4, 11),
+ z0 = svabal (z0, z4, 11))
+
+/*
+** abal_11_s16_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.b), #11
+** movprfx z0, z1
+** sabal z0\.h, z4\.b, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_s16_untied, svint16_t, svint8_t,
+ z0 = svabal_n_s16 (z1, z4, 11),
+ z0 = svabal (z1, z4, 11))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s32.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s32.c
new file mode 100644
index 00000000000..5faac313e45
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s32.c
@@ -0,0 +1,90 @@
+/* { dg-do assemble { target aarch64_asm_sve2p3_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sve2p3_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+#pragma GCC target "+sve2p3"
+#pragma GCC target "+sme2p3"
+
+/*
+** abal_s32_tied1:
+** sabal z0\.s, z4\.h, z5\.h
+** ret
+*/
+TEST_DUAL_Z (abal_s32_tied1, svint32_t, svint16_t,
+ z0 = svabal_s32 (z0, z4, z5),
+ z0 = svabal (z0, z4, z5))
+
+/*
+** abal_s32_tied2:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** sabal z0\.s, \1\.h, z1\.h
+** ret
+*/
+TEST_DUAL_Z_REV (abal_s32_tied2, svint32_t, svint16_t,
+ z0_res = svabal_s32 (z4, z0, z1),
+ z0_res = svabal (z4, z0, z1))
+
+/*
+** abal_s32_tied3:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** sabal z0\.s, z1\.h, \1\.h
+** ret
+*/
+TEST_DUAL_Z_REV (abal_s32_tied3, svint32_t, svint16_t,
+ z0_res = svabal_s32 (z4, z1, z0),
+ z0_res = svabal (z4, z1, z0))
+
+/*
+** abal_s32_untied:
+** movprfx z0, z1
+** sabal z0\.s, z4\.h, z5\.h
+** ret
+*/
+TEST_DUAL_Z (abal_s32_untied, svint32_t, svint16_t,
+ z0 = svabal_s32 (z1, z4, z5),
+ z0 = svabal (z1, z4, z5))
+
+/*
+** abal_w0_s32_tied1:
+** mov (z[0-9]+\.h), w0
+** sabal z0\.s, z4\.h, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_s32_tied1, svint32_t, svint16_t, int16_t,
+ z0 = svabal_n_s32 (z0, z4, x0),
+ z0 = svabal (z0, z4, x0))
+
+/*
+** abal_w0_s32_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.h), w0
+** movprfx z0, z1
+** sabal z0\.s, z4\.h, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_s32_untied, svint32_t, svint16_t, int16_t,
+ z0 = svabal_n_s32 (z1, z4, x0),
+ z0 = svabal (z1, z4, x0))
+
+/*
+** abal_11_s32_tied1:
+** mov (z[0-9]+\.h), #11
+** sabal z0\.s, z4\.h, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_s32_tied1, svint32_t, svint16_t,
+ z0 = svabal_n_s32 (z0, z4, 11),
+ z0 = svabal (z0, z4, 11))
+
+/*
+** abal_11_s32_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.h), #11
+** movprfx z0, z1
+** sabal z0\.s, z4\.h, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_s32_untied, svint32_t, svint16_t,
+ z0 = svabal_n_s32 (z1, z4, 11),
+ z0 = svabal (z1, z4, 11))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s64.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s64.c
new file mode 100644
index 00000000000..580b7c7d5bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s64.c
@@ -0,0 +1,90 @@
+/* { dg-do assemble { target aarch64_asm_sve2p3_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sve2p3_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+#pragma GCC target "+sve2p3"
+#pragma GCC target "+sme2p3"
+
+/*
+** abal_s64_tied1:
+** sabal z0\.d, z4\.s, z5\.s
+** ret
+*/
+TEST_DUAL_Z (abal_s64_tied1, svint64_t, svint32_t,
+ z0 = svabal_s64 (z0, z4, z5),
+ z0 = svabal (z0, z4, z5))
+
+/*
+** abal_s64_tied2:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** sabal z0\.d, \1\.s, z1\.s
+** ret
+*/
+TEST_DUAL_Z_REV (abal_s64_tied2, svint64_t, svint32_t,
+ z0_res = svabal_s64 (z4, z0, z1),
+ z0_res = svabal (z4, z0, z1))
+
+/*
+** abal_s64_tied3:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** sabal z0\.d, z1\.s, \1\.s
+** ret
+*/
+TEST_DUAL_Z_REV (abal_s64_tied3, svint64_t, svint32_t,
+ z0_res = svabal_s64 (z4, z1, z0),
+ z0_res = svabal (z4, z1, z0))
+
+/*
+** abal_s64_untied:
+** movprfx z0, z1
+** sabal z0\.d, z4\.s, z5\.s
+** ret
+*/
+TEST_DUAL_Z (abal_s64_untied, svint64_t, svint32_t,
+ z0 = svabal_s64 (z1, z4, z5),
+ z0 = svabal (z1, z4, z5))
+
+/*
+** abal_w0_s64_tied1:
+** mov (z[0-9]+\.s), w0
+** sabal z0\.d, z4\.s, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_s64_tied1, svint64_t, svint32_t, int32_t,
+ z0 = svabal_n_s64 (z0, z4, x0),
+ z0 = svabal (z0, z4, x0))
+
+/*
+** abal_w0_s64_untied:
+** mov (z[0-9]+\.s), w0
+** movprfx z0, z1
+** sabal z0\.d, z4\.s, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_s64_untied, svint64_t, svint32_t, int32_t,
+ z0 = svabal_n_s64 (z1, z4, x0),
+ z0 = svabal (z1, z4, x0))
+
+/*
+** abal_11_s64_tied1:
+** mov (z[0-9]+\.s), #11
+** sabal z0\.d, z4\.s, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_s64_tied1, svint64_t, svint32_t,
+ z0 = svabal_n_s64 (z0, z4, 11),
+ z0 = svabal (z0, z4, 11))
+
+/*
+** abal_11_s64_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.s), #11
+** movprfx z0, z1
+** sabal z0\.d, z4\.s, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_s64_untied, svint64_t, svint32_t,
+ z0 = svabal_n_s64 (z1, z4, 11),
+ z0 = svabal (z1, z4, 11))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u16.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u16.c
new file mode 100644
index 00000000000..dc6da978d26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u16.c
@@ -0,0 +1,90 @@
+/* { dg-do assemble { target aarch64_asm_sve2p3_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sve2p3_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+#pragma GCC target "+sve2p3"
+#pragma GCC target "+sme2p3"
+
+/*
+** abal_u16_tied1:
+** uabal z0\.h, z4\.b, z5\.b
+** ret
+*/
+TEST_DUAL_Z (abal_u16_tied1, svuint16_t, svuint8_t,
+ z0 = svabal_u16 (z0, z4, z5),
+ z0 = svabal (z0, z4, z5))
+
+/*
+** abal_u16_tied2:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** uabal z0\.h, \1\.b, z1\.b
+** ret
+*/
+TEST_DUAL_Z_REV (abal_u16_tied2, svuint16_t, svuint8_t,
+ z0_res = svabal_u16 (z4, z0, z1),
+ z0_res = svabal (z4, z0, z1))
+
+/*
+** abal_u16_tied3:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** uabal z0\.h, z1\.b, \1\.b
+** ret
+*/
+TEST_DUAL_Z_REV (abal_u16_tied3, svuint16_t, svuint8_t,
+ z0_res = svabal_u16 (z4, z1, z0),
+ z0_res = svabal (z4, z1, z0))
+
+/*
+** abal_u16_untied:
+** movprfx z0, z1
+** uabal z0\.h, z4\.b, z5\.b
+** ret
+*/
+TEST_DUAL_Z (abal_u16_untied, svuint16_t, svuint8_t,
+ z0 = svabal_u16 (z1, z4, z5),
+ z0 = svabal (z1, z4, z5))
+
+/*
+** abal_w0_u16_tied1:
+** mov (z[0-9]+\.b), w0
+** uabal z0\.h, z4\.b, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_u16_tied1, svuint16_t, svuint8_t, uint8_t,
+ z0 = svabal_n_u16 (z0, z4, x0),
+ z0 = svabal (z0, z4, x0))
+
+/*
+** abal_w0_u16_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.b), w0
+** movprfx z0, z1
+** uabal z0\.h, z4\.b, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_u16_untied, svuint16_t, svuint8_t, uint8_t,
+ z0 = svabal_n_u16 (z1, z4, x0),
+ z0 = svabal (z1, z4, x0))
+
+/*
+** abal_11_u16_tied1:
+** mov (z[0-9]+\.b), #11
+** uabal z0\.h, z4\.b, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_u16_tied1, svuint16_t, svuint8_t,
+ z0 = svabal_n_u16 (z0, z4, 11),
+ z0 = svabal (z0, z4, 11))
+
+/*
+** abal_11_u16_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.b), #11
+** movprfx z0, z1
+** uabal z0\.h, z4\.b, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_u16_untied, svuint16_t, svuint8_t,
+ z0 = svabal_n_u16 (z1, z4, 11),
+ z0 = svabal (z1, z4, 11))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u32.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u32.c
new file mode 100644
index 00000000000..cf906adb340
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u32.c
@@ -0,0 +1,90 @@
+/* { dg-do assemble { target aarch64_asm_sve2p3_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sve2p3_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+#pragma GCC target "+sve2p3"
+#pragma GCC target "+sme2p3"
+
+/*
+** abal_u32_tied1:
+** uabal z0\.s, z4\.h, z5\.h
+** ret
+*/
+TEST_DUAL_Z (abal_u32_tied1, svuint32_t, svuint16_t,
+ z0 = svabal_u32 (z0, z4, z5),
+ z0 = svabal (z0, z4, z5))
+
+/*
+** abal_u32_tied2:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** uabal z0\.s, \1\.h, z1\.h
+** ret
+*/
+TEST_DUAL_Z_REV (abal_u32_tied2, svuint32_t, svuint16_t,
+ z0_res = svabal_u32 (z4, z0, z1),
+ z0_res = svabal (z4, z0, z1))
+
+/*
+** abal_u32_tied3:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** uabal z0\.s, z1\.h, \1\.h
+** ret
+*/
+TEST_DUAL_Z_REV (abal_u32_tied3, svuint32_t, svuint16_t,
+ z0_res = svabal_u32 (z4, z1, z0),
+ z0_res = svabal (z4, z1, z0))
+
+/*
+** abal_u32_untied:
+** movprfx z0, z1
+** uabal z0\.s, z4\.h, z5\.h
+** ret
+*/
+TEST_DUAL_Z (abal_u32_untied, svuint32_t, svuint16_t,
+ z0 = svabal_u32 (z1, z4, z5),
+ z0 = svabal (z1, z4, z5))
+
+/*
+** abal_w0_u32_tied1:
+** mov (z[0-9]+\.h), w0
+** uabal z0\.s, z4\.h, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_u32_tied1, svuint32_t, svuint16_t, uint16_t,
+ z0 = svabal_n_u32 (z0, z4, x0),
+ z0 = svabal (z0, z4, x0))
+
+/*
+** abal_w0_u32_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.h), w0
+** movprfx z0, z1
+** uabal z0\.s, z4\.h, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_u32_untied, svuint32_t, svuint16_t, uint16_t,
+ z0 = svabal_n_u32 (z1, z4, x0),
+ z0 = svabal (z1, z4, x0))
+
+/*
+** abal_11_u32_tied1:
+** mov (z[0-9]+\.h), #11
+** uabal z0\.s, z4\.h, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_u32_tied1, svuint32_t, svuint16_t,
+ z0 = svabal_n_u32 (z0, z4, 11),
+ z0 = svabal (z0, z4, 11))
+
+/*
+** abal_11_u32_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.h), #11
+** movprfx z0, z1
+** uabal z0\.s, z4\.h, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_u32_untied, svuint32_t, svuint16_t,
+ z0 = svabal_n_u32 (z1, z4, 11),
+ z0 = svabal (z1, z4, 11))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u64.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u64.c
new file mode 100644
index 00000000000..cd09c1ec07f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u64.c
@@ -0,0 +1,90 @@
+/* { dg-do assemble { target aarch64_asm_sve2p3_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sve2p3_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+#pragma GCC target "+sve2p3"
+#pragma GCC target "+sme2p3"
+
+/*
+** abal_u64_tied1:
+** uabal z0\.d, z4\.s, z5\.s
+** ret
+*/
+TEST_DUAL_Z (abal_u64_tied1, svuint64_t, svuint32_t,
+ z0 = svabal_u64 (z0, z4, z5),
+ z0 = svabal (z0, z4, z5))
+
+/*
+** abal_u64_tied2:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** uabal z0\.d, \1\.s, z1\.s
+** ret
+*/
+TEST_DUAL_Z_REV (abal_u64_tied2, svuint64_t, svuint32_t,
+ z0_res = svabal_u64 (z4, z0, z1),
+ z0_res = svabal (z4, z0, z1))
+
+/*
+** abal_u64_tied3:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** uabal z0\.d, z1\.s, \1\.s
+** ret
+*/
+TEST_DUAL_Z_REV (abal_u64_tied3, svuint64_t, svuint32_t,
+ z0_res = svabal_u64 (z4, z1, z0),
+ z0_res = svabal (z4, z1, z0))
+
+/*
+** abal_u64_untied:
+** movprfx z0, z1
+** uabal z0\.d, z4\.s, z5\.s
+** ret
+*/
+TEST_DUAL_Z (abal_u64_untied, svuint64_t, svuint32_t,
+ z0 = svabal_u64 (z1, z4, z5),
+ z0 = svabal (z1, z4, z5))
+
+/*
+** abal_w0_u64_tied1:
+** mov (z[0-9]+\.s), w0
+** uabal z0\.d, z4\.s, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_u64_tied1, svuint64_t, svuint32_t, uint32_t,
+ z0 = svabal_n_u64 (z0, z4, x0),
+ z0 = svabal (z0, z4, x0))
+
+/*
+** abal_w0_u64_untied:
+** mov (z[0-9]+\.s), w0
+** movprfx z0, z1
+** uabal z0\.d, z4\.s, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_u64_untied, svuint64_t, svuint32_t, uint32_t,
+ z0 = svabal_n_u64 (z1, z4, x0),
+ z0 = svabal (z1, z4, x0))
+
+/*
+** abal_11_u64_tied1:
+** mov (z[0-9]+\.s), #11
+** uabal z0\.d, z4\.s, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_u64_tied1, svuint64_t, svuint32_t,
+ z0 = svabal_n_u64 (z0, z4, 11),
+ z0 = svabal (z0, z4, 11))
+
+/*
+** abal_11_u64_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.s), #11
+** movprfx z0, z1
+** uabal z0\.d, z4\.s, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_u64_untied, svuint64_t, svuint32_t,
+ z0 = svabal_n_u64 (z1, z4, 11),
+ z0 = svabal (z1, z4, 11))
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index c6ebbed4f4b..54fb2bbcaaa 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -12887,10 +12887,10 @@ proc
check_effective_target_aarch64_gas_has_build_attributes { } {
set exts {
"bf16" "cmpbr" "crc" "crypto" "dotprod" "f32mm" "f64mm" "faminmax"
"fp" "fp8" "fp8dot2" "fp8dot4" "fp8fma" "i8mm" "ls64" "lse" "lut"
- "sb" "simd" "sve-b16b16" "sve" "sve2" "sve-sm4" "sve-aes" "sve-bitperm"
+ "sb" "simd" "sve-b16b16" "sve" "sve2" "sve2p3" "sve-sm4" "sve-aes"
"sve-bitperm"
"sve-sha3" "f8f16mm" "f8f32mm" "sve-f16f32mm"
"sme-f8f16" "sme-f8f32"
- "sme-b16b16" "sme-f16f16" "sme-i16i64" "sme" "sme2" "sme2p1" "sme2p2"
+ "sme-b16b16" "sme-f16f16" "sme-i16i64" "sme" "sme2" "sme2p1" "sme2p2"
"sme2p3"
"ssve-fp8dot2" "ssve-fp8dot4" "ssve-fp8fma" "sve-bfscale" "sme-lutv2"
"ssve-fexpa" "ssve-bitperm"
}
--
2.43.0
