---
gcc/ChangeLog:
* config/i386/avx10_v2_auxintrin.h (__attribute__):
(_mm_cvtbf8_ps):
(_mm_mask_cvtbf8_ps):
(_mm_maskz_cvtbf8_ps):
(_mm256_cvtbf8_ps):
(_mm256_mask_cvtbf8_ps):
(_mm256_maskz_cvtbf8_ps):
(_mm512_cvtbf8_ps):
(_mm512_mask_cvtbf8_ps):
(_mm512_maskz_cvtbf8_ps):
(_mm_cvthf8_ps):
(_mm_mask_cvthf8_ps):
(_mm_maskz_cvthf8_ps):
(_mm256_cvthf8_ps):
(_mm256_mask_cvthf8_ps):
(_mm256_maskz_cvthf8_ps):
(_mm512_cvthf8_ps):
(_mm512_mask_cvthf8_ps):
(_mm512_maskz_cvthf8_ps):
* config/i386/i386-builtin-types.def (V4SF):
(V8SF):
(V16SF):
* config/i386/i386-builtin.def (BDESC):
* config/i386/i386-expand.cc (ix86_expand_args_builtin):
* config/i386/sse.md (vcvt<convertfp82ps><mode>):
(vcvt<convertfp82ps><mode>_mask):
(*vcvt<convertfp82ps><mode>_mask):
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10_2-v2-aux-convert-4.c: New test.
gcc/config/i386/avx10_v2_auxintrin.h | 175 ++++++++++++++++++
gcc/config/i386/i386-builtin-types.def | 3 +
gcc/config/i386/i386-builtin.def | 6 +
gcc/config/i386/i386-expand.cc | 3 +
gcc/config/i386/sse.md | 51 +++++
.../i386/avx10_2-v2-aux-convert-4.c | 46 +++++
6 files changed, 284 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-v2-aux-convert-4.c
diff --git a/gcc/config/i386/avx10_v2_auxintrin.h
b/gcc/config/i386/avx10_v2_auxintrin.h
index 18997ba8e6f..f63f835f08f 100644
--- a/gcc/config/i386/avx10_v2_auxintrin.h
+++ b/gcc/config/i386/avx10_v2_auxintrin.h
@@ -972,6 +972,181 @@ _mm512_maskz_cvts_biasps_hf8(__mmask16 __U, __m512i __A,
__m512 __B)
(__mmask16) __U);
}
+// VCVTBF82PS - 128-bit
+
+extern __inline __m128
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtbf8_ps(__m128i __A)
+{
+ return (__m128) __builtin_ia32_vcvtbf82ps128_mask ((__v16qi) __A,
+ (__v4sf) _mm_undefined_ps (),
+ (__mmask8) -1);
+}
+
+
+extern __inline __m128
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvtbf8_ps(__m128 __W, __mmask8 __U, __m128i __A)
+{
+ return (__m128) __builtin_ia32_vcvtbf82ps128_mask ((__v16qi) __A,
+ (__v4sf) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvtbf8_ps(__mmask8 __U, __m128i __A)
+{
+ return (__m128) __builtin_ia32_vcvtbf82ps128_mask ((__v16qi) __A,
+ (__v4sf) _mm_setzero_ps (),
+ (__mmask8) __U);
+}
+
+// VCVTBF82PS - 256-bit
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtbf8_ps(__m128i __A)
+{
+ return (__m256) __builtin_ia32_vcvtbf82ps256_mask ((__v16qi) __A,
+ (__v8sf) _mm256_undefined_ps
(),
+ (__mmask8) -1);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvtbf8_ps(__m256 __W, __mmask8 __U, __m128i __A)
+{
+ return (__m256) __builtin_ia32_vcvtbf82ps256_mask ((__v16qi) __A,
+ (__v8sf) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvtbf8_ps(__mmask8 __U, __m128i __A)
+{
+ return (__m256) __builtin_ia32_vcvtbf82ps256_mask ((__v16qi) __A,
+ (__v8sf) _mm256_setzero_ps (),
+ (__mmask8) __U);
+}
+
+// VCVTBF82PS - 512-bit
+
+extern __inline __m512
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvtbf8_ps(__m128i __A)
+{
+ return (__m512) __builtin_ia32_vcvtbf82ps512_mask ((__v16qi) __A,
+ (__v16sf) _mm512_undefined_ps
(),
+ (__mmask16) -1);
+}
+
+extern __inline __m512
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvtbf8_ps(__m512 __W, __mmask16 __U, __m128i __A)
+{
+ return (__m512) __builtin_ia32_vcvtbf82ps512_mask ((__v16qi) __A,
+ (__v16sf) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m512
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvtbf8_ps(__mmask16 __U, __m128i __A)
+{
+ return (__m512) __builtin_ia32_vcvtbf82ps512_mask ((__v16qi) __A,
+ (__v16sf) _mm512_setzero_ps (),
+ (__mmask16) __U);
+}
+
+// // VCVTHF82PS - 128-bit
+
+extern __inline __m128
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvthf8_ps(__m128i __A)
+{
+ return (__m128) __builtin_ia32_vcvthf82ps128_mask ((__v16qi) __A,
+ (__v4sf) _mm_undefined_ps (),
+ (__mmask8) -1);
+}
+
+extern __inline __m128
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvthf8_ps(__m128 __W, __mmask8 __U, __m128i __A)
+{
+ return (__m128) __builtin_ia32_vcvthf82ps128_mask ((__v16qi) __A,
+ (__v4sf) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvthf8_ps(__mmask8 __U, __m128i __A)
+{
+ return (__m128) __builtin_ia32_vcvthf82ps128_mask ((__v16qi) __A,
+ (__v4sf) _mm_setzero_ps (),
+ (__mmask8) __U);
+}
+
+// VCVTHF82PS - 256-bit
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvthf8_ps(__m128i __A)
+{
+ return (__m256) __builtin_ia32_vcvthf82ps256_mask ((__v16qi) __A,
+ (__v8sf) _mm256_undefined_ps
(),
+ (__mmask8) -1);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvthf8_ps(__m256 __W, __mmask8 __U, __m128i __A)
+{
+ return (__m256) __builtin_ia32_vcvthf82ps256_mask ((__v16qi) __A,
+ (__v8sf) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvthf8_ps(__mmask8 __U, __m128i __A)
+{
+ return (__m256) __builtin_ia32_vcvthf82ps256_mask ((__v16qi) __A,
+ (__v8sf) _mm256_setzero_ps (),
+ (__mmask8) __U);
+}
+
+// VCVTHF82PS - 512-bit
+
+extern __inline __m512
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvthf8_ps(__m128i __A)
+{
+ return (__m512) __builtin_ia32_vcvthf82ps512_mask ((__v16qi) __A,
+ (__v16sf) _mm512_undefined_ps
(),
+ (__mmask16) -1);
+}
+
+extern __inline __m512
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvthf8_ps(__m512 __W, __mmask16 __U, __m128i __A)
+{
+ return (__m512) __builtin_ia32_vcvthf82ps512_mask ((__v16qi) __A,
+ (__v16sf) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m512
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvthf8_ps(__mmask16 __U, __m128i __A)
+{
+ return (__m512) __builtin_ia32_vcvthf82ps512_mask ((__v16qi) __A,
+ (__v16sf) _mm512_setzero_ps (),
+ (__mmask16) __U);
+}
+
#ifdef __DISABLE_AVX10_V2_AUX__
#undef __DISABLE_AVX10_V2_AUX__
#pragma GCC pop_options
diff --git a/gcc/config/i386/i386-builtin-types.def
b/gcc/config/i386/i386-builtin-types.def
index 59bc019c637..a23b0fed1dd 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -1475,6 +1475,9 @@ DEF_FUNCTION_TYPE (V8DI, V8DF, V8DI, UQI)
DEF_FUNCTION_TYPE (V8SI, V8DF, V8SI, UQI)
# AVX10_V2_AUX builtins
+DEF_FUNCTION_TYPE (V4SF, V16QI, V4SF, UQI)
+DEF_FUNCTION_TYPE (V8SF, V16QI, V8SF, UQI)
+DEF_FUNCTION_TYPE (V16SF, V16QI, V16SF, UHI)
DEF_FUNCTION_TYPE (V16QI, V4SF, V16QI, UQI)
DEF_FUNCTION_TYPE (V16QI, V8SF, V16QI, UQI)
DEF_FUNCTION_TYPE (V16QI, V16SF, V16QI, UHI)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index cdb28295000..f89252a3f1e 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -3400,6 +3400,12 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX,
CODE_FOR_vcvtbiasps2hf8v16sf_mask, "__b
BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbiasps2hf8sv4sf_mask,
"__builtin_ia32_vcvtbiasps2hf8s128_mask", IX86_BUILTIN_VCVTBIASPS2HF8S128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V4SF_V16QI_UQI)
BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbiasps2hf8sv8sf_mask,
"__builtin_ia32_vcvtbiasps2hf8s256_mask", IX86_BUILTIN_VCVTBIASPS2HF8S256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V32QI_V8SF_V16QI_UQI)
BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbiasps2hf8sv16sf_mask,
"__builtin_ia32_vcvtbiasps2hf8s512_mask", IX86_BUILTIN_VCVTBIASPS2HF8S512_MASK,
UNKNOWN, (int) V16QI_FTYPE_V64QI_V16SF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbf82psv4sf_mask,
"__builtin_ia32_vcvtbf82ps128_mask", IX86_BUILTIN_VCVTBF82PS128_MASK, UNKNOWN,
(int) V4SF_FTYPE_V16QI_V4SF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbf82psv8sf_mask,
"__builtin_ia32_vcvtbf82ps256_mask", IX86_BUILTIN_VCVTBF82PS256_MASK, UNKNOWN,
(int) V8SF_FTYPE_V16QI_V8SF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbf82psv16sf_mask,
"__builtin_ia32_vcvtbf82ps512_mask", IX86_BUILTIN_VCVTBF82PS512_MASK, UNKNOWN,
(int) V16SF_FTYPE_V16QI_V16SF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvthf82psv4sf_mask,
"__builtin_ia32_vcvthf82ps128_mask", IX86_BUILTIN_VCVTHF82PS128_MASK, UNKNOWN,
(int) V4SF_FTYPE_V16QI_V4SF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvthf82psv8sf_mask,
"__builtin_ia32_vcvthf82ps256_mask", IX86_BUILTIN_VCVTHF82PS256_MASK, UNKNOWN,
(int) V8SF_FTYPE_V16QI_V8SF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvthf82psv16sf_mask,
"__builtin_ia32_vcvthf82ps512_mask", IX86_BUILTIN_VCVTHF82PS512_MASK, UNKNOWN,
(int) V16SF_FTYPE_V16QI_V16SF_UHI)
/* Builtins with rounding support. */
BDESC_END (ARGS, ROUND_ARGS)
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index a31a19c744c..f40ac2780b2 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -12901,6 +12901,9 @@ ix86_expand_args_builtin (const struct
builtin_description *d,
case V16QI_FTYPE_V4SF_V16QI_UQI:
case V16QI_FTYPE_V8SF_V16QI_UQI:
case V16QI_FTYPE_V16SF_V16QI_UHI:
+ case V4SF_FTYPE_V16QI_V4SF_UQI:
+ case V8SF_FTYPE_V16QI_V8SF_UQI:
+ case V16SF_FTYPE_V16QI_V16SF_UHI:
nargs = 3;
break;
case V32QI_FTYPE_V32QI_V32QI_INT:
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index c72e24da6cc..358ac449c8b 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -270,6 +270,8 @@
UNSPEC_VCVTBIASPS2BF8S
UNSPEC_VCVTBIASPS2HF8
UNSPEC_VCVTBIASPS2HF8S
+ UNSPEC_VCVTBF82PS
+ UNSPEC_VCVTHF82PS
])
(define_c_enum "unspecv" [
@@ -33926,3 +33928,52 @@
"vcvt<convertbiasps2fp8>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
[(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
+
+;; FP8 to FP32 converts (VCVTBF82PS, VCVTHF82PS)
+
+(define_int_iterator UNSPEC_CONVERTFP82PS
+ [UNSPEC_VCVTBF82PS UNSPEC_VCVTHF82PS])
+
+(define_int_attr convertfp82ps
+ [(UNSPEC_VCVTBF82PS "bf82ps")
+ (UNSPEC_VCVTHF82PS "hf82ps")])
+
+(define_insn "vcvt<convertfp82ps><mode>"
+ [(set (match_operand:VF1_AVX512VL 0 "register_operand" "=v")
+ (unspec:VF1_AVX512VL
+ [(match_operand:V16QI 1 "nonimmediate_operand" "vm")]
+ UNSPEC_CONVERTFP82PS))]
+ "TARGET_AVX10_V2_AUX"
+ "vcvt<convertfp82ps>\t{%1, %0|%0, %1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
+(define_expand "vcvt<convertfp82ps><mode>_mask"
+ [(set (match_operand:VF1_AVX512VL 0 "register_operand")
+ (vec_merge:VF1_AVX512VL
+ (unspec:VF1_AVX512VL
+ [(match_operand:V16QI 1 "nonimmediate_operand")]
+ UNSPEC_CONVERTFP82PS)
+ (match_operand:VF1_AVX512VL 2 "nonimm_or_0_operand")
+ (match_operand:<avx512fmaskmode> 3 "register_or_constm1_operand")))]
+ "TARGET_AVX10_V2_AUX"
+{
+ if (CONST_INT_P (operands[3]))
+ {
+ emit_insn (gen_vcvt<convertfp82ps><mode> (operands[0], operands[1]));
+ DONE;
+ }
+})
+
+(define_insn "*vcvt<convertfp82ps><mode>_mask"
+ [(set (match_operand:VF1_AVX512VL 0 "register_operand" "=v")
+ (vec_merge:VF1_AVX512VL
+ (unspec:VF1_AVX512VL
+ [(match_operand:V16QI 1 "nonimmediate_operand" "vm")]
+ UNSPEC_CONVERTFP82PS)
+ (match_operand:VF1_AVX512VL 2 "nonimm_or_0_operand" "0C")
+ (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))]
+ "TARGET_AVX10_V2_AUX"
+ "vcvt<convertfp82ps>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-v2-aux-convert-4.c
b/gcc/testsuite/gcc.target/i386/avx10_2-v2-aux-convert-4.c
new file mode 100644
index 00000000000..50f96c1745c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-v2-aux-convert-4.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10-v2-aux -O2" } */
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtbf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvthf82ps\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+
+#include <immintrin.h>
+
+__m128 test_mm_cvtbf8_ps (__m128i a) { return _mm_cvtbf8_ps (a); }
+__m128 test_mm_mask_cvtbf8_ps (__m128 w, __mmask8 u, __m128i a) { return
_mm_mask_cvtbf8_ps (w, u, a); }
+__m128 test_mm_maskz_cvtbf8_ps (__mmask8 u, __m128i a) { return
_mm_maskz_cvtbf8_ps (u, a); }
+
+__m256 test_mm256_cvtbf8_ps (__m128i a) { return _mm256_cvtbf8_ps (a); }
+__m256 test_mm256_mask_cvtbf8_ps (__m256 w, __mmask8 u, __m128i a) { return
_mm256_mask_cvtbf8_ps (w, u, a); }
+__m256 test_mm256_maskz_cvtbf8_ps (__mmask8 u, __m128i a) { return
_mm256_maskz_cvtbf8_ps (u, a); }
+
+__m512 test_mm512_cvtbf8_ps (__m128i a) { return _mm512_cvtbf8_ps (a); }
+__m512 test_mm512_mask_cvtbf8_ps (__m512 w, __mmask16 u, __m128i a) { return
_mm512_mask_cvtbf8_ps (w, u, a); }
+__m512 test_mm512_maskz_cvtbf8_ps (__mmask16 u, __m128i a) { return
_mm512_maskz_cvtbf8_ps (u, a); }
+
+__m128 test_mm_cvthf8_ps (__m128i a) { return _mm_cvthf8_ps (a); }
+__m128 test_mm_mask_cvthf8_ps (__m128 w, __mmask8 u, __m128i a) { return
_mm_mask_cvthf8_ps (w, u, a); }
+__m128 test_mm_maskz_cvthf8_ps (__mmask8 u, __m128i a) { return
_mm_maskz_cvthf8_ps (u, a); }
+
+__m256 test_mm256_cvthf8_ps (__m128i a) { return _mm256_cvthf8_ps (a); }
+__m256 test_mm256_mask_cvthf8_ps (__m256 w, __mmask8 u, __m128i a) { return
_mm256_mask_cvthf8_ps (w, u, a); }
+__m256 test_mm256_maskz_cvthf8_ps (__mmask8 u, __m128i a) { return
_mm256_maskz_cvthf8_ps (u, a); }
+
+__m512 test_mm512_cvthf8_ps (__m128i a) { return _mm512_cvthf8_ps (a); }
+__m512 test_mm512_mask_cvthf8_ps (__m512 w, __mmask16 u, __m128i a) { return
_mm512_mask_cvthf8_ps (w, u, a); }
+__m512 test_mm512_maskz_cvthf8_ps (__mmask16 u, __m128i a) { return
_mm512_maskz_cvthf8_ps (u, a); }
--
2.34.1
