---
gcc/ChangeLog:
* common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_TILE_SET):
(OPTION_MASK_ISA2_TILE_SET):
(OPTION_MASK_ISA2_TILE_UNSET):
(ix86_handle_option):
* common/config/i386/i386-cpuinfo.h (enum processor_features):
* common/config/i386/i386-isas.h:
* config.gcc:
* config/i386/amxtileintrin.h (__attribute__):
(_tile_loadconfig):
(_tile_storeconfig):
(_tile_release):
(_tile_zero):
(_tile_zero_internal):
* config/i386/i386-builtin.def (BDESC):
* config/i386/i386-c.cc (ix86_target_macros_internal):
* config/i386/i386-isa.def (TILE):
* config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p):
* config/i386/i386.md:
* config/i386/i386.opt:
* config/i386/immintrin.h:
* config/i386/tileintrin.h: New file.
gcc/testsuite/ChangeLog:
* g++.dg/other/i386-2.C:
* g++.dg/other/i386-3.C:
* gcc.target/i386/funcspec-56.inc:
* gcc.target/i386/tile-asmatt-1.c: New test.
* gcc.target/i386/tile-asmintel-1.c: New test.
* gcc.target/i386/tile-define-1.c: New test.
* gcc.target/i386/tile-define-2.c: New test.
gcc/common/config/i386/i386-common.cc | 21 +++++-
gcc/common/config/i386/i386-cpuinfo.h | 1 +
gcc/common/config/i386/i386-isas.h | 1 +
gcc/config.gcc | 2 +-
gcc/config/i386/amxtileintrin.h | 28 --------
gcc/config/i386/i386-builtin.def | 6 +-
gcc/config/i386/i386-c.cc | 2 +
gcc/config/i386/i386-isa.def | 1 +
gcc/config/i386/i386-options.cc | 4 +-
gcc/config/i386/i386.md | 4 +-
gcc/config/i386/i386.opt | 4 ++
gcc/config/i386/immintrin.h | 2 +
gcc/config/i386/tileintrin.h | 69 +++++++++++++++++++
gcc/testsuite/g++.dg/other/i386-2.C | 2 +-
gcc/testsuite/g++.dg/other/i386-3.C | 2 +-
gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 +
gcc/testsuite/gcc.target/i386/tile-asmatt-1.c | 19 +++++
.../gcc.target/i386/tile-asmintel-1.c | 18 +++++
gcc/testsuite/gcc.target/i386/tile-define-1.c | 13 ++++
gcc/testsuite/gcc.target/i386/tile-define-2.c | 13 ++++
20 files changed, 175 insertions(+), 39 deletions(-)
create mode 100644 gcc/config/i386/tileintrin.h
create mode 100644 gcc/testsuite/gcc.target/i386/tile-asmatt-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/tile-asmintel-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/tile-define-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/tile-define-2.c
diff --git a/gcc/common/config/i386/i386-common.cc
b/gcc/common/config/i386/i386-common.cc
index a57f7887b58..4a306827715 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -98,7 +98,8 @@ along with GCC; see the file COPYING3. If not see
(OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
#define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET
OPTION_MASK_ISA2_AVX512VP2INTERSECT
-#define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE
+#define OPTION_MASK_ISA2_AMX_TILE_SET \
+ (OPTION_MASK_ISA2_TILE_SET | OPTION_MASK_ISA2_AMX_TILE)
#define OPTION_MASK_ISA2_AMX_INT8_SET \
(OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_INT8)
#define OPTION_MASK_ISA2_AMX_BF16_SET \
@@ -142,6 +143,8 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_AVX512BMM_SET OPTION_MASK_ISA2_AVX512BMM
#define OPTION_MASK_ISA2_AVX10_V2_AUX_SET \
(OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10_V2_AUX)
+#define OPTION_MASK_ISA2_TILE_SET OPTION_MASK_ISA2_TILE
+
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2. */
#define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
@@ -336,7 +339,8 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_AMX_MOVRS_UNSET OPTION_MASK_ISA2_AMX_MOVRS
#define OPTION_MASK_ISA2_AVX512BMM_UNSET OPTION_MASK_ISA2_AVX512BMM
#define OPTION_MASK_ISA2_AVX10_V2_AUX_UNSET OPTION_MASK_ISA2_AVX10_V2_AUX
-
+#define OPTION_MASK_ISA2_TILE_UNSET \
+ (OPTION_MASK_ISA2_TILE | OPTION_MASK_ISA2_AMX_TILE_UNSET)
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
#define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
@@ -998,6 +1002,19 @@ ix86_handle_option (struct gcc_options *opts,
}
return true;
+ case OPT_mtile:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_TILE_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TILE_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_TILE_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TILE_UNSET;
+ }
+ return true;
+
case OPT_msgx:
if (value)
{
diff --git a/gcc/common/config/i386/i386-cpuinfo.h
b/gcc/common/config/i386/i386-cpuinfo.h
index 9291e3187d5..20444fae38b 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -285,6 +285,7 @@ enum processor_features
FEATURE_AMX_MOVRS,
FEATURE_AVX512BMM,
FEATURE_AVX10_V2_AUX,
+ FEATURE_TILE,
CPU_FEATURE_MAX
};
diff --git a/gcc/common/config/i386/i386-isas.h
b/gcc/common/config/i386/i386-isas.h
index 5959a3a17df..ec3e9273a47 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -194,4 +194,5 @@ ISA_NAMES_TABLE_START
ISA_NAMES_TABLE_ENTRY("avx512bmm", FEATURE_AVX512BMM, P_NONE, "-mavx512bmm")
ISA_NAMES_TABLE_ENTRY("avx10-v2-aux", FEATURE_AVX10_V2_AUX, P_NONE,
"-mavx10-v2-aux")
+ ISA_NAMES_TABLE_ENTRY("tile", FEATURE_TILE, P_NONE, "-mtile")
ISA_NAMES_TABLE_END
diff --git a/gcc/config.gcc b/gcc/config.gcc
index c21e263fc2f..8fc0b37c0f9 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -472,7 +472,7 @@ i[34567]86-*-* | x86_64-*-*)
avx10_2minmaxintrin.h avx10_2copyintrin.h
amxavx512intrin.h amxtf32intrin.h amxfp8intrin.h
movrsintrin.h amxmovrsintrin.h avx512bmmintrin.h
- avx512bmmvlintrin.h avx10_v2_auxintrin.h"
+ avx512bmmvlintrin.h avx10_v2_auxintrin.h tileintrin.h"
;;
ia64-*-*)
extra_headers=ia64intrin.h
diff --git a/gcc/config/i386/amxtileintrin.h b/gcc/config/i386/amxtileintrin.h
index 7dd32c5bfc0..c120ef1d926 100644
--- a/gcc/config/i386/amxtileintrin.h
+++ b/gcc/config/i386/amxtileintrin.h
@@ -35,27 +35,6 @@
#endif /* __AMX_TILE__ */
#if defined(__x86_64__)
-extern __inline void
-__attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_tile_loadconfig (const void *__config)
-{
- __builtin_ia32_ldtilecfg (__config);
-}
-
-extern __inline void
-__attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_tile_storeconfig (void *__config)
-{
- __builtin_ia32_sttilecfg (__config);
-}
-
-extern __inline void
-__attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_tile_release (void)
-{
- __asm__ volatile ("tilerelease" ::);
-}
-
#define _tile_loadd(dst,base,stride) \
_tile_loadd_internal (dst, base, stride)
@@ -81,13 +60,6 @@ _tile_release (void)
:: "r" ((void*) (base)), "r" ((__PTRDIFF_TYPE__) (stride)), [_src]"i"(src) \
: "memory")
-#define _tile_zero(dst) \
- _tile_zero_internal (dst)
-
-#define _tile_zero_internal(dst) \
- __asm__ volatile \
- ("{tilezero\t%%tmm%c[_dst]|tilezero\ttmm%c[_dst]}" :: [_dst]"i"(dst))
-
#endif
#ifdef __DISABLE_AMX_TILE__
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 85895f19703..d486bd9f09a 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -126,9 +126,9 @@ BDESC (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, 0,
CODE_FOR_nothing, "__b
BDESC (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_nothing,
"__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int)
VOID_FTYPE_PVOID_INT64)
BDESC (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_nothing,
"__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int)
VOID_FTYPE_PVOID_INT64)
-/* LDFILECFG and STFILECFG. */
-BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_AMX_TILE, CODE_FOR_nothing,
"__builtin_ia32_ldtilecfg", IX86_BUILTIN_LDTILECFG, UNKNOWN, (int)
VOID_FTYPE_PCVOID)
-BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_AMX_TILE, CODE_FOR_nothing,
"__builtin_ia32_sttilecfg", IX86_BUILTIN_STTILECFG, UNKNOWN, (int)
VOID_FTYPE_PVOID)
+/* LDTILECFG and STTILECFG. */
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_TILE, CODE_FOR_nothing,
"__builtin_ia32_ldtilecfg", IX86_BUILTIN_LDTILECFG, UNKNOWN, (int)
VOID_FTYPE_PCVOID)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_TILE, CODE_FOR_nothing,
"__builtin_ia32_sttilecfg", IX86_BUILTIN_STTILECFG, UNKNOWN, (int)
VOID_FTYPE_PVOID)
/* SSE */
BDESC (OPTION_MASK_ISA_SSE, 0, CODE_FOR_movv4sf_internal,
"__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int)
VOID_FTYPE_PFLOAT_V4SF)
diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
index d8688f43563..7f2e2f58109 100644
--- a/gcc/config/i386/i386-c.cc
+++ b/gcc/config/i386/i386-c.cc
@@ -794,6 +794,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__AVX512BMM__");
if (isa_flag2 & OPTION_MASK_ISA2_AVX10_V2_AUX)
def_or_undef (parse_in, "__AVX10_V2_AUX__");
+ if (isa_flag2 & OPTION_MASK_ISA2_TILE)
+ def_or_undef (parse_in, "__TILE__");
if (TARGET_IAMCU)
{
def_or_undef (parse_in, "__iamcu");
diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def
index cd2a436295e..58800e1dc4f 100644
--- a/gcc/config/i386/i386-isa.def
+++ b/gcc/config/i386/i386-isa.def
@@ -127,3 +127,4 @@ DEF_PTA(MOVRS)
DEF_PTA(AMX_MOVRS)
DEF_PTA(AVX512BMM)
DEF_PTA(AVX10_V2_AUX)
+DEF_PTA(TILE)
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index f780c3202ee..84f8cc683fe 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -276,7 +276,8 @@ static struct ix86_target_opts isa2_opts[] =
{ "-mmovrs", OPTION_MASK_ISA2_MOVRS },
{ "-mamx-movrs", OPTION_MASK_ISA2_AMX_MOVRS },
{ "-mavx512bmm", OPTION_MASK_ISA2_AVX512BMM },
- { "-mavx10-v2-aux", OPTION_MASK_ISA2_AVX10_V2_AUX }
+ { "-mavx10-v2-aux", OPTION_MASK_ISA2_AVX10_V2_AUX },
+ { "-mtile", OPTION_MASK_ISA2_TILE }
};
static struct ix86_target_opts isa_opts[] =
{
@@ -1143,6 +1144,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree
args, char *p_strings[],
IX86_ATTR_ISA ("amx-movrs", OPT_mamx_movrs),
IX86_ATTR_ISA ("avx512bmm", OPT_mavx512bmm),
IX86_ATTR_ISA ("avx10-v2-aux", OPT_mavx10_v2_aux),
+ IX86_ATTR_ISA ("tile", OPT_mtile),
/* enum options */
IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 912fc1af018..4ba4688014f 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -31411,7 +31411,7 @@
(define_insn "ldtilecfg"
[(unspec_volatile [(match_operand:BLK 0 "memory_operand" "m")]
UNSPECV_LDTILECFG)]
- "TARGET_AMX_TILE"
+ "TARGET_TILE"
"ldtilecfg\t%0"
[(set_attr "type" "other")
(set_attr "prefix" "maybe_evex")
@@ -31420,7 +31420,7 @@
(define_insn "sttilecfg"
[(set (match_operand:BLK 0 "memory_operand" "=m")
(unspec_volatile:BLK [(const_int 0)] UNSPECV_STTILECFG))]
- "TARGET_AMX_TILE"
+ "TARGET_TILE"
"sttilecfg\t%0"
[(set_attr "type" "other")
(set_attr "prefix" "maybe_evex")
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 6f6fc081448..db45ed64c61 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1393,3 +1393,7 @@ Support AVX512BMM built-in functions and code generation.
mavx10-v2-aux
Target Mask(ISA2_AVX10_V2_AUX) Var(ix86_isa_flags2) Save
Support AVX10_V2_AUX built-in functions and code generation.
+
+mtile
+Target Mask(ISA2_TILE) Var(ix86_isa_flags2) Save
+Support TILE built-in functions and code generation.
diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index 9811f7a0bae..18afee336e7 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -124,6 +124,8 @@
#include <avxneconvertintrin.h>
+#include <tileintrin.h>
+
#include <amxtileintrin.h>
#include <amxint8intrin.h>
diff --git a/gcc/config/i386/tileintrin.h b/gcc/config/i386/tileintrin.h
new file mode 100644
index 00000000000..9c0e1d93ce4
--- /dev/null
+++ b/gcc/config/i386/tileintrin.h
@@ -0,0 +1,69 @@
+/* Copyright (C) 2020-2026 Free Software Foundation, Inc.
+This file is part of GCC.
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+<http://www.gnu.org/licenses/>. */
+
+#if !defined _IMMINTRIN_H_INCLUDED
+#error "Never use <tileintrin.h> directly; include <immintrin.h> instead."
+#endif
+
+#ifndef _TILEINTRIN_H_INCLUDED
+#define _TILEINTRIN_H_INCLUDED
+
+#if !defined(__TILE__)
+#pragma GCC push_options
+#pragma GCC target("tile")
+#define __DISABLE_TILE__
+#endif /* __TILE__ */
+
+#if defined(__x86_64__)
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_tile_loadconfig (const void *__config)
+{
+ __builtin_ia32_ldtilecfg (__config);
+}
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_tile_storeconfig (void *__config)
+{
+ __builtin_ia32_sttilecfg (__config);
+}
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_tile_release (void)
+{
+ __asm__ volatile ("tilerelease" ::);
+}
+
+#define _tile_zero(dst) \
+ _tile_zero_internal (dst)
+
+#define _tile_zero_internal(dst) \
+ __asm__ volatile \
+ ("{tilezero\t%%tmm%c[_dst]|tilezero\ttmm%c[_dst]}" :: [_dst]"i"(dst))
+
+#endif /* __x86_64__ */
+
+#ifdef __DISABLE_TILE__
+#undef __DISABLE_TILE__
+#pragma GCC pop_options
+#endif /* __DISABLE_TILE__ */
+
+#endif /* _TILEINTRIN_H_INCLUDED */
diff --git a/gcc/testsuite/g++.dg/other/i386-2.C
b/gcc/testsuite/g++.dg/other/i386-2.C
index d4c73f541ca..89b9420397a 100644
--- a/gcc/testsuite/g++.dg/other/i386-2.C
+++ b/gcc/testsuite/g++.dg/other/i386-2.C
@@ -6,7 +6,7 @@
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
popcntintrin.h, fmaintrin.h, pkuintrin.h, avx512vpopcntdqintrin.h,
gfniintrin.h, avx512bitalgintrin.h, avx512vp2intersectintrin.h,
- tsxldtrkintrin.h, amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h,
+ tsxldtrkintrin.h, tileintrin.h, amxtileintrin.h, amxint8intrin.h,
amxbf16intrin.h,
avx512vp2intersectvlintrin.h and mm_malloc.h.h are usable
with -O -pedantic-errors. */
diff --git a/gcc/testsuite/g++.dg/other/i386-3.C
b/gcc/testsuite/g++.dg/other/i386-3.C
index e925607c486..6c25b028029 100644
--- a/gcc/testsuite/g++.dg/other/i386-3.C
+++ b/gcc/testsuite/g++.dg/other/i386-3.C
@@ -6,7 +6,7 @@
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
popcntintrin.h, fmaintrin.h, pkuintrin.h, avx512vpopcntdqintrin.h,
gfniintrin.h, avx512bitalgintrin.h, avx512vp2intersectintrin.h,
- tsxldtrkintrin.h, amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h,
+ tsxldtrkintrin.h, tileintrin.h, amxtileintrin.h, amxint8intrin.h,
amxbf16intrin.h,
avx512vp2intersectvlintrin.h and mm_malloc.h are usable
with -O -fkeep-inline-functions. */
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index f41067560d0..9d4eb832b1e 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -93,6 +93,7 @@ extern void test_amx_tf32 (void)
__attribute__((__target__("amx-tf32")));
extern void test_amx_fp8 (void)
__attribute__((__target__("amx-fp8")));
extern void test_movrs (void)
__attribute__((__target__("movrs")));
extern void test_amx_movrs (void)
__attribute__((__target__("amx-movrs")));
+extern void test_tile (void)
__attribute__((__target__("tile")));
extern void test_no_sgx (void)
__attribute__((__target__("no-sgx")));
extern void test_no_avx512vpopcntdq(void)
__attribute__((__target__("no-avx512vpopcntdq")));
@@ -187,6 +188,7 @@ extern void test_no_amx_tf32 (void)
__attribute__((__target__("no-amx-tf32")));
extern void test_no_amx_fp8 (void)
__attribute__((__target__("no-amx-fp8")));
extern void test_no_movrs (void)
__attribute__((__target__("no-movrs")));
extern void test_no_amx_movrs (void)
__attribute__((__target__("no-amx-movrs")));
+extern void test_no_tile (void)
__attribute__((__target__("no-tile")));
extern void test_arch_nocona (void)
__attribute__((__target__("arch=nocona")));
extern void test_arch_core2 (void)
__attribute__((__target__("arch=core2")));
diff --git a/gcc/testsuite/gcc.target/i386/tile-asmatt-1.c
b/gcc/testsuite/gcc.target/i386/tile-asmatt-1.c
new file mode 100644
index 00000000000..cb350c19aee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/tile-asmatt-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mtile" } */
+/* { dg-final { scan-assembler "ldtilecfg\[ \\t]" } } */
+/* { dg-final { scan-assembler "sttilecfg\[ \\t]" } } */
+/* { dg-final { scan-assembler "tilerelease" } } */
+/* { dg-final { scan-assembler "tilezero\[ \\t]+\[^\n\]*%tmm\[0-9\]" } } */
+#include <immintrin.h>
+
+extern int a[];
+
+#define TMM0 0
+
+void TEST ()
+{
+ _tile_loadconfig (a);
+ _tile_storeconfig (a);
+ _tile_release ();
+ _tile_zero (TMM0);
+}
diff --git a/gcc/testsuite/gcc.target/i386/tile-asmintel-1.c
b/gcc/testsuite/gcc.target/i386/tile-asmintel-1.c
new file mode 100644
index 00000000000..5023f15749e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/tile-asmintel-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-require-effective-target masm_intel } */
+/* { dg-options "-O2 -mtile -masm=intel" } */
+/* { dg-final { scan-assembler "ldtilecfg\[ \\t]" } } */
+/* { dg-final { scan-assembler "sttilecfg\[ \\t]" } } */
+/* { dg-final { scan-assembler "tilerelease" } } */
+/* { dg-final { scan-assembler "tilezero\[ \\t]+\[^\n%\]*tmm\[0-9\]" } } */
+#include <immintrin.h>
+
+extern int a[];
+
+void TEST ()
+{
+ _tile_loadconfig (a);
+ _tile_storeconfig (a);
+ _tile_release ();
+ _tile_zero (2);
+}
diff --git a/gcc/testsuite/gcc.target/i386/tile-define-1.c
b/gcc/testsuite/gcc.target/i386/tile-define-1.c
new file mode 100644
index 00000000000..cb98d9bcab3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/tile-define-1.c
@@ -0,0 +1,13 @@
+/* Verify that -mtile defines __TILE__. */
+/* { dg-do compile } */
+/* { dg-options "-mtile" } */
+
+#ifndef __TILE__
+#error "-mtile should define __TILE__"
+#endif
+
+int
+foo (void)
+{
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/i386/tile-define-2.c
b/gcc/testsuite/gcc.target/i386/tile-define-2.c
new file mode 100644
index 00000000000..c090e49e0fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/tile-define-2.c
@@ -0,0 +1,13 @@
+/* Verify that -mamx-tile implies -mtile (AMX-TILE enables TILE). */
+/* { dg-do compile } */
+/* { dg-options "-mamx-tile" } */
+
+#ifndef __TILE__
+#error "-mamx-tile should imply -mtile and define __TILE__"
+#endif
+
+int
+foo (void)
+{
+ return 0;
+}
--
2.34.1
