From: juewang <[email protected]>
This patch introduces a conservative loop unrolling heuristic for the
RISC-V backend, controlled by the new -munroll-only-small-loops option.
When -munroll-only-small-loops is active, only small loops (those whose
body does not exceed a per-tune instruction threshold) are unrolled, and
the unroll factor is capped by a per-tune parameter, so that tight loops
benefit from unrolling without exposing larger loops to its code-size and
instruction-cache costs.
Mirroring the i386 model, -funroll-loops and -munroll-only-small-loops are
enabled by default at -O2 and above (for speed). An explicit -funroll-loops
(or -funroll-all-loops) turns -munroll-only-small-loops off, so a user who
explicitly asks for unrolling still gets loops of any size unrolled. The
size threshold and the maximum unroll factor come from the -mtune tuning
parameters.
Since -funroll-loops is now enabled by default at -O2 and above, a number
of pre-existing RISC-V tests that scan for a specific code sequence change
their output once loops are unrolled. As those tests do not aim to exercise
unrolling, add -fno-unroll-loops to their options so they keep validating
their intended property regardless of the unrolling decision.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_option_optimization_table):
Enable -funroll-loops and -munroll-only-small-loops at -O2 and above.
* config/riscv/riscv.cc (struct riscv_tune_param): Add fields
small_loop_unroll_ninsns and small_loop_unroll_factor.
(xt_c9501_tune_info): Set them.
(riscv_loop_unroll_adjust): New function.
(riscv_option_override): Turn off -munroll-only-small-loops when
-funroll-loops or -funroll-all-loops is explicitly given.
(TARGET_LOOP_UNROLL_ADJUST): Define.
* config/riscv/riscv.opt (munroll-only-small-loops): New option.
* config/riscv/riscv.opt.urls: Regenerate.
* doc/invoke.texi (RISC-V Options): Document -munroll-only-small-loops.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/unroll-explicit.c: New test.
* gcc.target/riscv/unroll-large-loop.c: New test.
* gcc.target/riscv/unroll-small-loop.c: New test.
* gcc.target/riscv/unroll-pragma.c: New test.
* gcc.target/riscv/unroll-small-loop-tune.c: New test.
* g++.target/riscv/pr97682.C: Add -fno-unroll-loops.
* gcc.target/riscv/rvv/autovec/pr113206-1.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-66.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-67.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-68.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-frm-insert-4.c: Likewise.
* gcc.target/riscv/rvv/base/float-point-frm-insert-5.c: Likewise.
* gcc.target/riscv/rvv/base/pr114352-3.c: Likewise.
* gcc.target/riscv/rvv/base/scalar_move-7.c: Likewise.
* gcc.target/riscv/rvv/base/spill-10.c: Likewise.
* gcc.target/riscv/rvv/base/spill-11.c: Likewise.
* gcc.target/riscv/rvv/base/spill-12.c: Likewise.
* gcc.target/riscv/rvv/base/spill-8.c: Likewise.
* gcc.target/riscv/rvv/base/spill-9.c: Likewise.
* gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c: Likewise.
* gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_single-4.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_single-6.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_single-66.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c: Likewise.
---
gcc/common/config/riscv/riscv-common.cc | 4 +++
gcc/config/riscv/riscv.cc | 32 +++++++++++++++++++
gcc/config/riscv/riscv.opt | 4 +++
gcc/config/riscv/riscv.opt.urls | 3 ++
gcc/doc/invoke.texi | 15 +++++++++
gcc/testsuite/g++.target/riscv/pr97682.C | 2 +-
.../gcc.target/riscv/rvv/autovec/pr113206-1.c | 2 +-
.../rvv/autovec/vls-vlmax/vec_extract-1u.c | 2 +-
.../rvv/autovec/vls-vlmax/vec_extract-2u.c | 2 +-
.../rvv/autovec/vls-vlmax/vec_extract-3u.c | 2 +-
.../rvv/autovec/vls-vlmax/vec_extract-4u.c | 2 +-
.../rvv/autovec/vls/calling-convention-1.c | 2 +-
.../rvv/autovec/vls/calling-convention-2.c | 2 +-
.../rvv/autovec/vls/calling-convention-3.c | 2 +-
.../rvv/autovec/vls/calling-convention-4.c | 2 +-
.../rvv/autovec/vls/calling-convention-5.c | 2 +-
.../rvv/autovec/vls/calling-convention-6.c | 2 +-
.../rvv/autovec/vls/calling-convention-7.c | 2 +-
.../rvv/base/float-point-dynamic-frm-39.c | 2 +-
.../rvv/base/float-point-dynamic-frm-41.c | 2 +-
.../rvv/base/float-point-dynamic-frm-45.c | 2 +-
.../rvv/base/float-point-dynamic-frm-46.c | 2 +-
.../rvv/base/float-point-dynamic-frm-48.c | 2 +-
.../rvv/base/float-point-dynamic-frm-49.c | 2 +-
.../rvv/base/float-point-dynamic-frm-50.c | 2 +-
.../rvv/base/float-point-dynamic-frm-52.c | 2 +-
.../rvv/base/float-point-dynamic-frm-56.c | 2 +-
.../rvv/base/float-point-dynamic-frm-59.c | 2 +-
.../rvv/base/float-point-dynamic-frm-60.c | 2 +-
.../rvv/base/float-point-dynamic-frm-61.c | 2 +-
.../rvv/base/float-point-dynamic-frm-62.c | 2 +-
.../rvv/base/float-point-dynamic-frm-64.c | 2 +-
.../rvv/base/float-point-dynamic-frm-65.c | 2 +-
.../rvv/base/float-point-dynamic-frm-66.c | 2 +-
.../rvv/base/float-point-dynamic-frm-67.c | 2 +-
.../rvv/base/float-point-dynamic-frm-68.c | 2 +-
.../rvv/base/float-point-dynamic-frm-69.c | 2 +-
.../rvv/base/float-point-dynamic-frm-70.c | 2 +-
.../rvv/base/float-point-dynamic-frm-71.c | 2 +-
.../riscv/rvv/base/float-point-frm-insert-4.c | 2 +-
.../riscv/rvv/base/float-point-frm-insert-5.c | 2 +-
.../gcc.target/riscv/rvv/base/pr114352-3.c | 2 +-
.../gcc.target/riscv/rvv/base/scalar_move-7.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-10.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-11.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-12.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-8.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-9.c | 2 +-
.../riscv/rvv/base/zvbb_vandn_vx_constraint.c | 2 +-
.../riscv/rvv/base/zvbc_vx_constraint-2.c | 2 +-
.../riscv/rvv/vsetvl/avl_multiple-3.c | 2 +-
.../riscv/rvv/vsetvl/avl_multiple-4.c | 2 +-
.../riscv/rvv/vsetvl/avl_single-4.c | 2 +-
.../riscv/rvv/vsetvl/avl_single-6.c | 2 +-
.../riscv/rvv/vsetvl/avl_single-66.c | 2 +-
.../riscv/rvv/vsetvl/imm_loop_invariant-1.c | 2 +-
.../riscv/rvv/vsetvl/imm_loop_invariant-2.c | 2 +-
.../riscv/rvv/vsetvl/imm_loop_invariant-3.c | 2 +-
.../riscv/rvv/vsetvl/imm_loop_invariant-4.c | 2 +-
.../riscv/rvv/vsetvl/imm_loop_invariant-5.c | 2 +-
.../riscv/rvv/vsetvl/imm_loop_invariant-6.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-1.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-10.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-14.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-15.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-16.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-17.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-18.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-19.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-20.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-21.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-22.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-23.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-27.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-28.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-29.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-3.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-30.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-31.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-35.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-37.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-7.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-8.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-9.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_bb_prop-17.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_bb_prop-18.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_bb_prop-19.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_bb_prop-20.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_conflict-11.c | 2 +-
.../gcc.target/riscv/unroll-explicit.c | 22 +++++++++++++
.../gcc.target/riscv/unroll-large-loop.c | 22 +++++++++++++
.../gcc.target/riscv/unroll-pragma.c | 23 +++++++++++++
.../gcc.target/riscv/unroll-small-loop-tune.c | 22 +++++++++++++
.../gcc.target/riscv/unroll-small-loop.c | 19 +++++++++++
94 files changed, 250 insertions(+), 84 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/unroll-explicit.c
create mode 100644 gcc/testsuite/gcc.target/riscv/unroll-large-loop.c
create mode 100644 gcc/testsuite/gcc.target/riscv/unroll-pragma.c
create mode 100644 gcc/testsuite/gcc.target/riscv/unroll-small-loop-tune.c
create mode 100644 gcc/testsuite/gcc.target/riscv/unroll-small-loop.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 74929381a06..cfae0b1fc43 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -2340,6 +2340,10 @@ static const struct default_options
riscv_option_optimization_table[] =
/* Enable -fsched-pressure starting at -O1. */
{ OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 },
{ OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
+ /* Turn on -funroll-loops with -munroll-only-small-loops to enable small
+ loop unrolling at -O2 and above. */
+ { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_funroll_loops, NULL, 1 },
+ { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_munroll_only_small_loops, NULL, 1 },
#if TARGET_DEFAULT_ASYNC_UNWIND_TABLES == 1
{ OPT_LEVELS_ALL, OPT_fasynchronous_unwind_tables, NULL, 1 },
{ OPT_LEVELS_ALL, OPT_funwind_tables, NULL, 1},
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index cc1b8cd16a9..6306ac23ed1 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -300,6 +300,8 @@ struct riscv_tune_param
const char *jump_align;
const char *loop_align;
bool prefer_agnostic;
+ unsigned int small_loop_unroll_ninsns = 4;
+ unsigned int small_loop_unroll_factor = 2;
};
@@ -734,6 +736,8 @@ static const struct riscv_tune_param xt_c9501_tune_info = {
"8", /* jump_align */
"16", /* loop_align */
true, /* prefer-agnostic. */
+ 4, /* small_loop_unroll_ninsns. */
+ 8, /* small_loop_unroll_factor. */
};
/* Costs to use when optimizing for Tenstorrent Ascalon 8 wide. */
@@ -5055,6 +5059,22 @@ riscv_insn_cost (rtx_insn *insn, bool speed)
return cost;
}
+/* This function adjusts the unroll factor based on
+ the current tune parameters. */
+
+static unsigned
+riscv_loop_unroll_adjust (unsigned nunroll, class loop *loop)
+{
+ if (riscv_unroll_only_small_loops && !loop->unroll)
+ {
+ if (loop->ninsns <= tune_param->small_loop_unroll_ninsns)
+ return MIN (tune_param->small_loop_unroll_factor, nunroll);
+ else
+ return 1;
+ }
+ return nunroll;
+}
+
/* Implement TARGET_MAX_NOCE_IFCVT_SEQ_COST. Like the default implementation,
but we consider cost units of branch instructions equal to cost units of
other instructions. */
@@ -12139,6 +12159,16 @@ riscv_option_override (void)
flag_pcc_struct_return = 0;
+ /* Explicit -funroll-loops or -funroll-all-loops turns
+ -munroll-only-small-loops off, allowing the unroller to handle
+ all loops without the conservative small-loop restriction. */
+ if ((OPTION_SET_P (flag_unroll_loops) && flag_unroll_loops)
+ || (OPTION_SET_P (flag_unroll_all_loops) && flag_unroll_all_loops))
+ {
+ if (!OPTION_SET_P (riscv_unroll_only_small_loops))
+ riscv_unroll_only_small_loops = 0;
+ }
+
if (flag_pic)
g_switch_value = 0;
@@ -16364,6 +16394,8 @@ riscv_memtag_tag_bitsize ()
#define TARGET_RTX_COSTS riscv_rtx_costs
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST riscv_address_cost
+#undef TARGET_LOOP_UNROLL_ADJUST
+#define TARGET_LOOP_UNROLL_ADJUST riscv_loop_unroll_adjust
#undef TARGET_INSN_COST
#define TARGET_INSN_COST riscv_insn_cost
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index c2670ad87b2..3226367bf8a 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -454,3 +454,7 @@ Enum(arcv_mpy_option) String(10c) Value(ARCV_MPY_OPTION_10C)
mmpy-option=
Target RejectNegative Joined Enum(arcv_mpy_option) Var(arcv_mpy_option)
Init(ARCV_MPY_OPTION_2C)
The type of MPY unit used by the RMX-100 core (to be used in combination with
-mtune=arc-v-rmx-100-series) (default: 2c).
+
+munroll-only-small-loops
+Target Var(riscv_unroll_only_small_loops) Init(0) Save
+Enable conservative small loop unrolling.
diff --git a/gcc/config/riscv/riscv.opt.urls b/gcc/config/riscv/riscv.opt.urls
index a11299b310a..15c1a8badc7 100644
--- a/gcc/config/riscv/riscv.opt.urls
+++ b/gcc/config/riscv/riscv.opt.urls
@@ -129,3 +129,6 @@ UrlSuffix(gcc/RISC-V-Options.html#index-mautovec-segment)
; skipping UrlSuffix for 'mmpy-option=' due to finding no URLs
+munroll-only-small-loops
+UrlSuffix(gcc/RISC-V-Options.html#index-munroll-only-small-loops)
+
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 8da5f03ccbd..11f97535c1e 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1349,6 +1349,7 @@ See RS/6000 and PowerPC Options.
-mno-inline-atomics -mno-inline-strlen
-mno-inline-strcmp -mno-inline-strncmp
-mstringop-strategy=@var{strategy}
+-munroll-only-small-loops -mno-unroll-only-small-loops
-mtls-dialect=desc -mtls-dialect=trad
-mrvv-vector-bits=@var{value} -mrvv-max-lmul=@var{value}
-madjust-lmul-cost -mmax-vectorization -mno-autovec-segment}
@@ -31564,6 +31565,20 @@ of TLS variables.
Use traditional TLS as the thread-local storage mechanism for dynamic accesses
of TLS variables. This is the default.
+@opindex munroll-only-small-loops
+@opindex mno-unroll-only-small-loops
+@item -munroll-only-small-loops
+@itemx -mno-unroll-only-small-loops
+Controls conservative small loop unrolling. It is enabled by default at
+@option{-O2} and above. When enabled, only loops whose RTL instruction
+count does not exceed a tune-specific threshold are unrolled, and the
+unroll factor is capped by a tune-specific parameter. This gives better
+utilization of the instruction decoding pipeline without enlarging bigger
+loops. You can disable it with @option{-mno-unroll-only-small-loops}; it
+is also turned off when @option{-funroll-loops} or
+@option{-funroll-all-loops} is explicitly enabled, so that an explicit
+unrolling request applies to loops of any size.
+
@opindex mrvv-vector-bits
@item -mrvv-vector-bits=@var{value}
Specify how the number of bits for an RVV vector register, as taken from
diff --git a/gcc/testsuite/g++.target/riscv/pr97682.C
b/gcc/testsuite/g++.target/riscv/pr97682.C
index 03c7a447de5..68e332a9993 100644
--- a/gcc/testsuite/g++.target/riscv/pr97682.C
+++ b/gcc/testsuite/g++.target/riscv/pr97682.C
@@ -1,6 +1,6 @@
/* PR target/97682 */
/* { dg-do compile } */
-/* { dg-options "-fPIC -O2 -march=rv64g -mabi=lp64" } */
+/* { dg-options "-fPIC -O2 -march=rv64g -mabi=lp64 -fno-unroll-loops" } */
template <typename ab, int ac> struct g { ab b[ac]; };
long i, m;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113206-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113206-1.c
index 45086182aa8..c8e4400b555 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113206-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113206-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m8
-fno-unroll-loops" } */
signed char e;
short f = 8;
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c
index 14334ba1a94..9552d09f48d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic
-fno-unroll-loops" } */
#include <stdint-gcc.h>
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c
index b9865948087..fd297e1a6f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic
-fno-unroll-loops" } */
#include <stdint-gcc.h>
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c
index 552c48ecc49..1dca3a337a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic
-fno-unroll-loops" } */
#include <stdint-gcc.h>
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c
index 36d4926e4f8..7fcf21271db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic
-fno-unroll-loops" } */
#include <stdint-gcc.h>
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
index 86c2400ce51..4a1ec041898 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-unroll-loops" } */
#include "def.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
index c489a9ff796..c2ab5ea9d28 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-unroll-loops" } */
#include "def.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
index 97a3282a657..7c9d23e748b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-unroll-loops" } */
#include "def.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
index a892919feb7..f0cccf76155 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-unroll-loops" } */
#include "def.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
index 0d40349fb0f..b1c7570d0ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-unroll-loops" } */
#include "def.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
index 8b5a779467d..72080058be5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-unroll-loops" } */
#include "def.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
index 3ba4e1f1864..10f6f1dc608 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable
-mabi=lp64d -O3 -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-unroll-loops" } */
#include "def.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c
index fe497c757db..5507706ea7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c
index 4f86fcb938a..5b2835ddf91 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c
index 69ccd4fe04d..029695a79ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c
index a11a1b45f50..471f68bba9c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c
index 2855d5f4562..3b8fb158286 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c
index 3e8a9808ba7..b2cbbd7b0f4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c
index e8fc7bbd6c2..f8d7c77497a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c
index 9828987d7d2..1579392fa18 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c
index aa9c06f625c..7cef51d9329 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c
index 8a752697cd8..f22e389f05b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c
index 96f009185cc..4a89eb0ff01 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c
index 5028b789192..995400ed2a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c
index 44bf9ffd059..3dac687db13 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c
index 45c8b8408de..0f2bbf0b1f7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c
index 329f98c5c1a..8efc2d46881 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-66.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-66.c
index b9240f24ec7..064c93369af 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-66.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-66.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-67.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-67.c
index 2008cc60b46..9bc910f2daa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-67.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-67.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-68.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-68.c
index cad2f1d5f9c..30371f600cf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-68.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-68.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c
index a971103c3ee..ef1bdfc45d7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c
index b1c51924567..6f3cd43dd03 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c
index c3170556d2f..bb054f9b996 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c
index 17e47eb0f41..2398d26b477 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c
index 32c938db123..ee097dc6be9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
index 4f375e526be..f3dfb33df7b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64 -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -O3 -fno-schedule-insns
-fno-schedule-insns2 -fno-unroll-loops" } */
/* { dg-final { check-function-bodies "**" "" } } */
/*
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c
index cf53aca5c62..4897a22e472 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-schedule-insns
-fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-schedule-insns
-fno-schedule-insns2 -O3 -fno-unroll-loops" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
index d5a839a2ce9..67954af0fd5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3
-fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3
-fno-schedule-insns -fno-schedule-insns2 -O3 -fno-unroll-loops" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
index cbfe9210514..5fd4b30f53d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32
-msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32
-msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3 -fno-unroll-loops"
} */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c
index 7e83cb7b7c1..65566d6b09e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -msave-restore -fno-schedule-insns
-fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -msave-restore -fno-schedule-insns
-fno-schedule-insns2 -O3 -fno-unroll-loops" } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-8.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-8.c
index ddc36e888eb..a3e7c9898e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
-fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
-fno-schedule-insns2 -O3 -fno-unroll-loops" } */
/* { dg-final { check-function-bodies "**" "" } } */
void f2 (char*);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
index 375d3166a46..c0c424c64ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns
-fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns
-fno-schedule-insns2 -O3 -fno-unroll-loops" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c
index 0d626095544..e70b1e326bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zvbb_zve64x -mabi=ilp32 -O3" } */
+/* { dg-options "-march=rv32gc_zvbb_zve64x -mabi=ilp32 -O3 -fno-unroll-loops"
} */
#include "riscv_vector.h"
vuint64m1_t test_vandn_vx_u64m1(vuint64m1_t vs2, uint64_t rs1, size_t vl) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c
index 3fb14660af8..daec087be73 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zvbc -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gc_zvbc -mabi=lp64d -O3 -fno-unroll-loops" } */
#include "riscv_vector.h"
vuint64m1_t test_vclmul_vx_u64m1_extend(vuint64m1_t vs2, uint32_t rs1, size_t
vl) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c
index 2ec94b2e482..9954e3538ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c
index 5f2ef672c90..26884589a4e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
index cf2ece80bef..aef7377e522 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
index b6776cd9713..ef179d09018 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
index c174845f7bc..38ed49455e7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops"
} */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c
index cee9e36ff2d..ad968b03abc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c
index 46b79ce2313..19abe42d5bd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c
index 05604f83974..19d79637665 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c
index b55f74a323c..b2a85af55c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c
index 50874c9acb6..eb2eb78a874 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c
index 63039357fe8..20d7aafa232 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c
index bfa81ba8294..f79bb848e0d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c
index 4ba81601c29..f2f445db290 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c
index e10f12ea205..ad869690344 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c
index 54074836e1d..662289275a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c
index e2963ddac15..fc1bf6ed894 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c
index aa18c3a6180..9c7940c0244 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c
index 81eba9ea259..1bdb2d2851a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c
index a7c1478b2a8..ed7adb82c20 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c
index aa18c3a6180..9c7940c0244 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c
index 5f770ae0257..38a6e3cfc66 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c
index dc012c8c1d2..b6251e7aca7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c
index 18700d518e9..40dfa3f973d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
index ffa95f90e49..a9f1a8d7a10 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
index d997762f877..1fce7ebc46e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2
-fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
index 2b3722decd8..76867b45125 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2
-fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c
index af46a81de6f..ac13999dd0d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
index 4c977e4e169..10eb6af8214 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2
-fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
index 2e2fc0282c9..1724c5ebc32 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2
-fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c
index 4de390c249c..6ae36ba8793 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
index 945beed5ebb..b864d6f0dd9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c
index 8e613899509..a82e90d33e5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c
index 15e82e08d89..f26ed8f97d7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c
index d1a6a944f40..752c12c5fdb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
index 321eb3b9f29..ee37b53507d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -mtune=rocket" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -mtune=rocket -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
index 29dcfefbd0c..4aa06ca09dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -mtune=rocket" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -mtune=rocket -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
index 8b6299e99d1..f13f02f4764 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -mtune=rocket" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -mtune=rocket -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
index 3b836f927d2..a6ffa12a681 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -mtune=rocket" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -mtune=rocket -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c
index ddc3f2c22a6..49f28eb846c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32
-fno-tree-vectorize -fno-unroll-loops" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/unroll-explicit.c
b/gcc/testsuite/gcc.target/riscv/unroll-explicit.c
new file mode 100644
index 00000000000..3f8e265c847
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/unroll-explicit.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-funroll-loops -fdump-rtl-loop2_unroll-details" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" } { "" } } */
+
+/* An explicit -funroll-loops turns off the default -munroll-only-small-loops,
+ so a loop exceeding the small-loop instruction threshold is unrolled
+ normally. */
+
+void
+large_loop_explicit (int *a, int *b, int *c, int *d, int n)
+{
+ int i;
+ for (i = 0; i < n; i++)
+ {
+ a[i] = b[i] + c[i];
+ d[i] = a[i] * b[i] - c[i];
+ b[i] = c[i] + d[i] + a[i];
+ c[i] = a[i] - d[i] + b[i];
+ }
+}
+
+/* { dg-final { scan-rtl-dump "Unrolled loop" "loop2_unroll" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/unroll-large-loop.c
b/gcc/testsuite/gcc.target/riscv/unroll-large-loop.c
new file mode 100644
index 00000000000..c17b1c03965
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/unroll-large-loop.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-fdump-rtl-loop2_unroll-details" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" "-funroll-loops"
} { "" } } */
+
+/* With the default -O2 small loop unrolling (-munroll-only-small-loops),
+ a loop whose body exceeds the small-loop instruction threshold is NOT
+ unrolled. */
+
+void
+large_loop (int *a, int *b, int *c, int *d, int n)
+{
+ int i;
+ for (i = 0; i < n; i++)
+ {
+ a[i] = b[i] + c[i];
+ d[i] = a[i] * b[i] - c[i];
+ b[i] = c[i] + d[i] + a[i];
+ c[i] = a[i] - d[i] + b[i];
+ }
+}
+
+/* { dg-final { scan-rtl-dump-not "Unrolled loop" "loop2_unroll" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/unroll-pragma.c
b/gcc/testsuite/gcc.target/riscv/unroll-pragma.c
new file mode 100644
index 00000000000..ea271865a8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/unroll-pragma.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-fdump-rtl-loop2_unroll-details" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" "-funroll-loops"
} { "" } } */
+
+/* An explicit "#pragma GCC unroll" sets loop->unroll, which makes
+ riscv_loop_unroll_adjust bypass the -munroll-only-small-loops
+ restriction. Hence a loop exceeding the small-loop instruction
+ threshold is still unrolled as requested. */
+
+void
+large_loop_pragma (int *a, int *b, int *c, int *d, int n)
+{
+#pragma GCC unroll 2
+ for (int i = 0; i < n; i++)
+ {
+ a[i] = b[i] + c[i];
+ d[i] = a[i] * b[i] - c[i];
+ b[i] = c[i] + d[i] + a[i];
+ c[i] = a[i] - d[i] + b[i];
+ }
+}
+
+/* { dg-final { scan-rtl-dump "Unrolled loop" "loop2_unroll" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/unroll-small-loop-tune.c
b/gcc/testsuite/gcc.target/riscv/unroll-small-loop-tune.c
new file mode 100644
index 00000000000..89e8a437ae9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/unroll-small-loop-tune.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=xt-c9501fdvt -fdump-rtl-loop2_unroll-details" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" "-funroll-loops"
} { "" } } */
+
+/* The xt-c9501fdvt tune model sets small_loop_unroll_factor to 8, so a small
+ loop is unrolled by a factor of 8 (rather than the generic default of 2).
+ The unroller reports the number of extra copies, i.e. factor - 1, so an
+ 8x unroll is dumped as "Unrolled loop 7 times". This verifies the tune
+ parameter actually takes effect; with the default factor the dump would
+ instead read "Unrolled loop 1 times". */
+
+int
+small_loop (int n)
+{
+ int sum = 0;
+ do
+ sum += n;
+ while (--n);
+ return sum;
+}
+
+/* { dg-final { scan-rtl-dump "Unrolled loop 7 times" "loop2_unroll" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/unroll-small-loop.c
b/gcc/testsuite/gcc.target/riscv/unroll-small-loop.c
new file mode 100644
index 00000000000..ebbe1e3551f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/unroll-small-loop.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-fdump-rtl-loop2_unroll-details" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" "-funroll-loops"
} { "" } } */
+
+/* Small loop unrolling is enabled by default at -O2 (-funroll-loops with
+ -munroll-only-small-loops), so a loop whose body is within the small-loop
+ instruction threshold is unrolled without any explicit option. */
+
+int
+small_loop (int n)
+{
+ int sum = 0;
+ do
+ sum += n;
+ while (--n);
+ return sum;
+}
+
+/* { dg-final { scan-rtl-dump "Unrolled loop" "loop2_unroll" } } */
--
2.39.5 (Apple Git-154)
