These set of 5 patches add some new instruction support that may be
added to future PowerPCs.
I have committed all of the patches in my backlog (dense math registers, other
-mcpu=future instructions, random bug fixes, support for _Float16 and
__bfloat16, and optimizations for vector logical operations on power10/power11)
into the IBM vendor branch:
vendors/ibm/gcc-17-future
Patch #1 changes the default so that load/store vector pair
instructions are used in generating memory move and string operations.
Patch #2 adds support for 32-bit and 64-bit saturating subtract
instructions.
Patch #3 adds support for a vector rotate left word instruction that
uses all 64 vector registers.
Patch #4 adds support to use alternative load/store vectors with
variable byte instructions that have the byte count in a more
convenient location.
Patch #5 adds support for a prefixed add immediate shifted instruction.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: [email protected]
