There are several insts that will be reused from legacy AMX, coming
from AMX-TILE and AMX-AVX512.
Since legacy AMX and ACE should not be used together, we choose not
to use the same intrin name for ACE and legacy AMX, while the builtins
could be shared.
For AMX-TILE related insts, we add "_ace_" in the middle of the intrin
name to explicitly mention the intrin is used by ACE.
For tilerelease, we keep it simple for now to use inline assembly since
no tmm register number need to be mentioned for the intrin and using
pattern does not help compiler knowing the dependency.
gcc/ChangeLog:
* config.gcc: Include acev1intrin.h.
* config/i386/i386-builtin-types.def: Add new function type.
* config/i386/i386-builtin.def (BDESC): Reuse AMX-TILE builtins
and handle ACEV1 new builtins.
* config/i386/i386-builtins.cc
(BDESC_VERIFYS): Add BDESC_ACE.
(def_builtin): Share builtin between AMX-TILE and ACEv1.
(ix86_init_mmx_sse_builtins): Handle BDESC_ACE.
* config/i386/i386-expand.cc
(ix86_expand_ace_builtin): New.
(ix86_check_builtin_isa_match): Share builtin between AMX-TILE
and ACEv1.
(ix86_expand_builtin): Handle BDESC_ACE.
* config/i386/i386.md (ldtilecfg): Add TARGET_ACEV1.
(sttilecfg): Ditto.
* config/i386/immintrin.h: Include acev1intrin.h.
* config/i386/sse.md (UNSPECV_TILEZERO): New.
(tilezero): Ditto.
* config/i386/acev1intrin.h: New intrin file.
gcc/testsuite/ChangeLog:
* g++.dg/other/i386-2.C: Add acev1 tests.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/avx-1.c: Ditto.
* gcc.target/i386/funcspec-56.inc: Ditto.
* gcc.target/i386/sse-12.c: Ditto.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/acev1-1.c: New test.
Co-authored-by: Dipesh Sharma <[email protected]>
---
gcc/config.gcc | 2 +-
gcc/config/i386/acev1intrin.h | 73 +++++++++++++++
gcc/config/i386/i386-builtin-types.def | 3 +
gcc/config/i386/i386-builtin.def | 10 +-
gcc/config/i386/i386-builtins.cc | 30 +++++-
gcc/config/i386/i386-expand.cc | 93 +++++++++++++++++++
gcc/config/i386/i386.md | 4 +-
gcc/config/i386/immintrin.h | 2 +
gcc/config/i386/sse.md | 12 +++
gcc/testsuite/g++.dg/other/i386-2.C | 2 +-
gcc/testsuite/g++.dg/other/i386-3.C | 2 +-
gcc/testsuite/gcc.target/i386/acev1-1.c | 17 ++++
gcc/testsuite/gcc.target/i386/avx-1.c | 7 +-
gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 +
gcc/testsuite/gcc.target/i386/sse-12.c | 2 +-
gcc/testsuite/gcc.target/i386/sse-13.c | 7 +-
gcc/testsuite/gcc.target/i386/sse-14.c | 11 ++-
gcc/testsuite/gcc.target/i386/sse-22.c | 13 ++-
gcc/testsuite/gcc.target/i386/sse-23.c | 7 +-
19 files changed, 279 insertions(+), 20 deletions(-)
create mode 100644 gcc/config/i386/acev1intrin.h
create mode 100644 gcc/testsuite/gcc.target/i386/acev1-1.c
diff --git a/gcc/config.gcc b/gcc/config.gcc
index eca5d254ba5..51a734d8247 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -488,7 +488,7 @@ i[34567]86-*-* | x86_64-*-*)
avx10_2minmaxintrin.h avx10_2copyintrin.h
amxavx512intrin.h amxfp8intrin.h movrsintrin.h
amxmovrsintrin.h avx512bmmintrin.h avx512bmmvlintrin.h
- avx10v2auxintrin.h"
+ avx10v2auxintrin.h acev1intrin.h"
;;
ia64-*-*)
extra_headers=ia64intrin.h
diff --git a/gcc/config/i386/acev1intrin.h b/gcc/config/i386/acev1intrin.h
new file mode 100644
index 00000000000..6daa05db342
--- /dev/null
+++ b/gcc/config/i386/acev1intrin.h
@@ -0,0 +1,73 @@
+/* Copyright (C) 2026 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef _IMMINTRIN_H_INCLUDED
+#error "Never use <acev1intrin.h> directly; include <immintrin.h> instead."
+#endif
+
+#ifndef _ACEV1INTRIN_H_INCLUDED
+#define _ACEV1INTRIN_H_INCLUDED
+
+#if !defined(__ACEV1__)
+#pragma GCC push_options
+#pragma GCC target("acev1")
+#define __DISABLE_ACEV1__
+#endif /* __ACEV1__ */
+
+#if defined(__x86_64__)
+
+#define _tile_ace_loadconfig(A) \
+ __builtin_ia32_ldtilecfg (A)
+
+#define _tile_ace_storeconfig(A) \
+ __builtin_ia32_sttilecfg (A)
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_tile_ace_release (void)
+{
+ __asm__ volatile ("tilerelease" ::);
+}
+
+#ifdef __OPTIMIZE__
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_tile_ace_zero (const int __A)
+{
+ __builtin_ia32_tilezero (__A);
+}
+
+#else
+#define _tile_ace_zero(A) \
+ __builtin_ia32_tilezero (A);
+
+#endif /* __OPTIMIZE__ */
+
+#endif /* __x86_64__ */
+
+#ifdef __DISABLE_ACEV1__
+#undef __DISABLE_ACEV1__
+#pragma GCC pop_options
+#endif /* __DISABLE_ACEV1__ */
+
+#endif /* _ACEV1INTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/i386-builtin-types.def
b/gcc/config/i386/i386-builtin-types.def
index e4c761fae24..90876723ceb 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -1499,3 +1499,6 @@ DEF_FUNCTION_TYPE (V64QI, V32QI, V64QI, UDI)
DEF_FUNCTION_TYPE (V16QI, V4SF, V16QI, UQI)
DEF_FUNCTION_TYPE (V16QI, V8SF, V16QI, UQI)
DEF_FUNCTION_TYPE (V16QI, V16SF, V16QI, UHI)
+
+# ACEv1 builtins
+DEF_FUNCTION_TYPE (VOID, UQI)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index ee06461725c..ae712a93479 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -127,8 +127,8 @@ BDESC (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, 0,
CODE_FOR_nothing, "__b
BDESC (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_nothing,
"__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int)
VOID_FTYPE_PVOID_INT64)
/* LDFILECFG and STFILECFG. */
-BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_AMX_TILE, CODE_FOR_nothing,
"__builtin_ia32_ldtilecfg", IX86_BUILTIN_LDTILECFG, UNKNOWN, (int)
VOID_FTYPE_PCVOID)
-BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_AMX_TILE, CODE_FOR_nothing,
"__builtin_ia32_sttilecfg", IX86_BUILTIN_STTILECFG, UNKNOWN, (int)
VOID_FTYPE_PVOID)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_AMX_TILE |
OPTION_MASK_ISA2_ACEV1, CODE_FOR_nothing, "__builtin_ia32_ldtilecfg",
IX86_BUILTIN_LDTILECFG, UNKNOWN, (int) VOID_FTYPE_PCVOID)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_AMX_TILE |
OPTION_MASK_ISA2_ACEV1, CODE_FOR_nothing, "__builtin_ia32_sttilecfg",
IX86_BUILTIN_STTILECFG, UNKNOWN, (int) VOID_FTYPE_PVOID)
/* SSE */
BDESC (OPTION_MASK_ISA_SSE, 0, CODE_FOR_movv4sf_internal,
"__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int)
VOID_FTYPE_PFLOAT_V4SF)
@@ -3973,5 +3973,9 @@ BDESC (OPTION_MASK_ISA_SHSTK, 0, CODE_FOR_nothing,
"__builtin_ia32_wrussd", IX86
BDESC (OPTION_MASK_ISA_SHSTK | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_nothing,
"__builtin_ia32_wrussq", IX86_BUILTIN_WRUSSQ, UNKNOWN, (int)
VOID_FTYPE_UINT64_PVOID)
BDESC (OPTION_MASK_ISA_SHSTK, 0, CODE_FOR_setssbsy, "__builtin_ia32_setssbsy",
IX86_BUILTIN_SETSSBSY, UNKNOWN, (int) VOID_FTYPE_VOID)
BDESC (OPTION_MASK_ISA_SHSTK, 0, CODE_FOR_clrssbsy, "__builtin_ia32_clrssbsy",
IX86_BUILTIN_CLRSSBSY, UNKNOWN, (int) VOID_FTYPE_PVOID)
+BDESC_END (CET, ACE)
-BDESC_END (CET, MAX)
+/* ACEv1. */
+BDESC_FIRST (ace, ACE,
+ OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_ACEV1, CODE_FOR_tilezero,
"__builtin_ia32_tilezero", IX86_BUILTIN_TILEZERO, UNKNOWN, (int) VOID_FTYPE_UQI)
+BDESC_END (ACE, MAX)
diff --git a/gcc/config/i386/i386-builtins.cc b/gcc/config/i386/i386-builtins.cc
index 6837efd8da5..d0c7cd47a6b 100644
--- a/gcc/config/i386/i386-builtins.cc
+++ b/gcc/config/i386/i386-builtins.cc
@@ -119,8 +119,10 @@ BDESC_VERIFYS (IX86_BUILTIN__BDESC_MULTI_ARG_FIRST,
IX86_BUILTIN__BDESC_ROUND_ARGS_LAST, 1);
BDESC_VERIFYS (IX86_BUILTIN__BDESC_CET_FIRST,
IX86_BUILTIN__BDESC_MULTI_ARG_LAST, 1);
-BDESC_VERIFYS (IX86_BUILTIN_MAX,
+BDESC_VERIFYS (IX86_BUILTIN__BDESC_ACE_FIRST,
IX86_BUILTIN__BDESC_CET_LAST, 1);
+BDESC_VERIFYS (IX86_BUILTIN_MAX,
+ IX86_BUILTIN__BDESC_ACE_LAST, 1);
/* Table for the ix86 builtin non-function types. */
@@ -281,10 +283,11 @@ def_builtin (HOST_WIDE_INT mask, HOST_WIDE_INT mask2,
&& (mask == 0 || (mask & ix86_isa_flags) != 0))
|| ((mask & OPTION_MASK_ISA_MMX) != 0 && TARGET_MMX_WITH_SSE)
/* "Unified" builtin used by either AVXVNNI/AVXIFMA/AES/
- AVXVNNIINT{8,16} intrinsics or AVX512VNNIVL/AVX512IFMAVL/VAESVL/
- AVX10.2 non-mask intrinsics should be defined whenever avxvnni/
- avxifma/aes/avxvnniint{8,16} or avx512vnni && avx512vl/avx512ifma
- && avx512vl/vaes && avx512vl/avx10.2 exist. */
+ AVXVNNIINT{8,16}/AMX-TILE intrinsics or AVX512VNNIVL/AVX512IFMAVL/
+ VAESVL/AVX10.2/ACEv1 non-mask intrinsics should be defined
+ whenever avxvnni/avxifma/aes/avxvnniint{8,16}/amx-tile or
+ avx512vnni && avx512vl/avx512ifma && avx512vl/vaes && avx512vl/
+ avx10.2/acev1 exist. */
|| (mask2 == OPTION_MASK_ISA2_AVXVNNI)
|| (mask2 == OPTION_MASK_ISA2_AVXIFMA)
|| (mask2 == (OPTION_MASK_ISA2_AVXNECONVERT
@@ -292,6 +295,7 @@ def_builtin (HOST_WIDE_INT mask, HOST_WIDE_INT mask2,
|| ((mask2 & OPTION_MASK_ISA2_VAES) != 0)
|| ((mask2 & OPTION_MASK_ISA2_AVXVNNIINT8) != 0)
|| ((mask2 & OPTION_MASK_ISA2_AVXVNNIINT16) != 0)
+ || ((mask2 & OPTION_MASK_ISA2_AMX_TILE) != 0)
|| (lang_hooks.builtin_function
== lang_hooks.builtin_function_ext_scope))
{
@@ -1292,6 +1296,22 @@ ix86_init_mmx_sse_builtins (void)
BDESC_VERIFYS (IX86_BUILTIN__BDESC_CET_LAST,
IX86_BUILTIN__BDESC_CET_FIRST,
ARRAY_SIZE (bdesc_cet) - 1);
+
+
+ /* Add ACE inrinsics. */
+ for (i = 0, d = bdesc_ace; i < ARRAY_SIZE (bdesc_ace);
+ i++, d++)
+ {
+ BDESC_VERIFY (d->code, IX86_BUILTIN__BDESC_ACE_FIRST, i);
+ if (d->name == 0)
+ continue;
+
+ ftype = (enum ix86_builtin_func_type) d->flag;
+ def_builtin (d->mask, d->mask2, d->name, ftype, d->code);
+ }
+ BDESC_VERIFYS (IX86_BUILTIN__BDESC_ACE_LAST,
+ IX86_BUILTIN__BDESC_ACE_FIRST,
+ ARRAY_SIZE (bdesc_ace) - 1);
}
#undef BDESC_VERIFY
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index c6c089bcaf6..7f8b36bd9c7 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -14780,6 +14780,90 @@ ix86_expand_special_args_builtin (const struct
builtin_description *d,
return klass == store ? 0 : target;
}
+/* Subroutine of ix86_expand_builtin to take care of amx insns
+ with variable number of operands. */
+
+static rtx
+ix86_expand_ace_builtin (const struct builtin_description *d, tree exp)
+{
+ tree arg;
+ rtx pat, op;
+ unsigned int i, nargs;
+ rtx xops[4];
+ enum insn_code icode = d->icode;
+ const struct insn_data_d *insn_p = &insn_data[icode];
+
+ switch ((enum ix86_builtin_func_type) d->flag)
+ {
+ case VOID_FTYPE_UQI:
+ nargs = 1;
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+
+ gcc_assert (nargs <= ARRAY_SIZE (xops));
+
+ for (i = 0; i < nargs; i++)
+ {
+ machine_mode mode = insn_p->operand[i].mode;
+
+ arg = CALL_EXPR_ARG (exp, i);
+ op = ix86_expand_unsigned_small_int_cst_argument (arg);
+
+ if (i == 0)
+ {
+ /* This must be the tmm reg number constant. */
+ if (!insn_p->operand[i].predicate(op, SImode))
+ {
+ error ("the argument must be constant");
+ return const0_rtx;
+ }
+
+ if (!IN_RANGE (INTVAL (op), 0, 7))
+ {
+ error ("the tmm register number argument must be between 0 to 7");
+ return const0_rtx;
+ }
+
+ }
+ else
+ {
+ /* This must be register. */
+ if (VECTOR_MODE_P (mode))
+ op = safe_vector_operand (op, mode);
+
+ op = fixup_modeless_constant (op, mode);
+
+ if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
+ op = copy_to_mode_reg (mode, op);
+ else
+ {
+ op = copy_to_reg (op);
+ op = lowpart_subreg (mode, op, GET_MODE (op));
+ }
+ }
+
+ xops[i] = op;
+ }
+
+ switch (nargs)
+ {
+ case 1:
+ pat = GEN_FCN (icode) (xops[0]);
+ break;
+ default:
+ gcc_unreachable ();
+ }
+
+ if (!pat)
+ return 0;
+
+ emit_insn (pat);
+ return 0;
+}
+
/* Return the integer constant in ARG. Constrain it to be in the range
of the subparts of VEC_TYPE; issue an error if not. */
@@ -14931,6 +15015,7 @@ ix86_check_builtin_isa_match (unsigned int fcode,
OPTION_MASK_ISA_AES or (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA2_VAES)
OPTION_MASK_ISA2_AVX10_2 or OPTION_MASK_ISA2_AVXVNNIINT8
OPTION_MASK_ISA2_AVX10_2 or OPTION_MASK_ISA2_AVXVNNIINT16
+ OPTION_MASK_ISA2_AMX_TILE or OPTION_MASK_ISA2_ACEV1
where for each such pair it is sufficient if either of the ISAs is
enabled, plus if it is ored with other options also those others.
OPTION_MASK_ISA_MMX in bisa is satisfied also if TARGET_MMX_WITH_SSE. */
@@ -14960,6 +15045,7 @@ ix86_check_builtin_isa_match (unsigned int fcode,
OPTION_MASK_ISA2_AVX10_2);
SHARE_BUILTIN (0, OPTION_MASK_ISA2_AVXVNNIINT16, 0,
OPTION_MASK_ISA2_AVX10_2);
+ SHARE_BUILTIN (0, OPTION_MASK_ISA2_AMX_TILE, 0, OPTION_MASK_ISA2_ACEV1);
isa = tmp_isa;
isa2 = tmp_isa2;
@@ -17351,6 +17437,13 @@ rdseed_step:
target);
}
+ if (fcode >= IX86_BUILTIN__BDESC_ACE_FIRST
+ && fcode <= IX86_BUILTIN__BDESC_ACE_LAST)
+ {
+ i = fcode - IX86_BUILTIN__BDESC_ACE_FIRST;
+ return ix86_expand_ace_builtin (bdesc_ace + i, exp);
+ }
+
gcc_unreachable ();
}
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index ccc1411a2fc..e9e5042ec13 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -31451,7 +31451,7 @@
(define_insn "ldtilecfg"
[(unspec_volatile [(match_operand:BLK 0 "memory_operand" "m")]
UNSPECV_LDTILECFG)]
- "TARGET_AMX_TILE"
+ "TARGET_AMX_TILE || TARGET_ACEV1"
"ldtilecfg\t%0"
[(set_attr "type" "other")
(set_attr "prefix" "maybe_evex")
@@ -31460,7 +31460,7 @@
(define_insn "sttilecfg"
[(set (match_operand:BLK 0 "memory_operand" "=m")
(unspec_volatile:BLK [(const_int 0)] UNSPECV_STTILECFG))]
- "TARGET_AMX_TILE"
+ "TARGET_AMX_TILE || TARGET_ACEV1"
"sttilecfg\t%0"
[(set_attr "type" "other")
(set_attr "prefix" "maybe_evex")
diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index d986c16f55d..4297af4c583 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -164,4 +164,6 @@
#include <avx10v2auxintrin.h>
+#include <acev1intrin.h>
+
#endif /* _IMMINTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 1b2dd8a530a..3fc593c596a 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -303,6 +303,9 @@
UNSPECV_AESENCWIDE256KLU8
UNSPECV_ENCODEKEY128U32
UNSPECV_ENCODEKEY256U32
+
+ ;; For ACEv1
+ UNSPECV_TILEZERO
])
;; All vector modes including V?TImode, used in move patterns.
@@ -34475,3 +34478,12 @@
"vcvt<pscvtfp8>{z}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "prefix" "evex")
(set_attr "mode" "V16SF")])
+
+(define_insn "tilezero"
+ [(set (reg:V32SI TMM_REGNUM)
+ (unspec_volatile:V32SI
+ [(match_operand:QI 0 "const_0_to_7_operand")]
+ UNSPECV_TILEZERO))]
+ "TARGET_ACEV1"
+ "tilezero\t{%%tmm%c0|tmm%c0}"
+ [(set_attr "prefix" "vex")])
diff --git a/gcc/testsuite/g++.dg/other/i386-2.C
b/gcc/testsuite/g++.dg/other/i386-2.C
index 7cb1ab56592..d0c6f9990db 100644
--- a/gcc/testsuite/g++.dg/other/i386-2.C
+++ b/gcc/testsuite/g++.dg/other/i386-2.C
@@ -1,5 +1,5 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2
-mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp
-mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt
-msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx
-mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize
-mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma
-mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint
-mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512
-mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux" } */
+/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2
-mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp
-mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt
-msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx
-mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize
-mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma
-mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint
-mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512
-mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1" } */
/* { dg-skip-if "requires hosted libstdc++ for cstdlib malloc" { ! hostedlib }
} */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
diff --git a/gcc/testsuite/g++.dg/other/i386-3.C
b/gcc/testsuite/g++.dg/other/i386-3.C
index efe7f24cfdf..f879c489ac8 100644
--- a/gcc/testsuite/g++.dg/other/i386-3.C
+++ b/gcc/testsuite/g++.dg/other/i386-3.C
@@ -1,5 +1,5 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx
-mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm
-mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr
-mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku
-msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect
-mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni
-mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi
-mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2
-mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux" } */
+/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx
-mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm
-mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr
-mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku
-msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect
-mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni
-mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi
-mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2
-mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1" } */
/* { dg-skip-if "requires hosted libstdc++ for cstdlib malloc" { ! hostedlib }
} */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
diff --git a/gcc/testsuite/gcc.target/i386/acev1-1.c
b/gcc/testsuite/gcc.target/i386/acev1-1.c
new file mode 100644
index 00000000000..9165f571ef9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/acev1-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -macev1" } */
+/* { dg-final { scan-assembler-times "ldtilecfg\[ \t]" 1 } } */
+/* { dg-final { scan-assembler-times "sttilecfg\[ \t]" 1 } } */
+/* { dg-final { scan-assembler-times "tilerelease" 1 } } */
+/* { dg-final { scan-assembler-times "tilezero\[ \t]" 1 } } */
+#include <immintrin.h>
+
+extern int t[];
+
+void amxtile ()
+{
+ _tile_ace_loadconfig (t);
+ _tile_ace_storeconfig (t);
+ _tile_ace_release ();
+ _tile_ace_zero (0);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c
b/gcc/testsuite/gcc.target/i386/avx-1.c
index cf6e0ba25ad..154a873c6b7 100644
--- a/gcc/testsuite/gcc.target/i386/avx-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow
-mavx -mavx2 -maes -mpclmul -mgfni -mprefetchi -mavx10.2 -mmovrs -mavx10v2aux"
} */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow
-mavx -mavx2 -maes -mpclmul -mgfni -mprefetchi -mavx10.2 -mmovrs -mavx10v2aux
-macev1" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
@@ -918,6 +918,11 @@
#define __builtin_ia32_vunpackb256_mask(A, B, C, M)
__builtin_ia32_vunpackb256_mask(A, 8, C, M)
#define __builtin_ia32_vunpackb512_mask(A, B, C, M)
__builtin_ia32_vunpackb512_mask(A, 8, C, M)
+/* acev1intrin.h */
+#ifdef __x86_64__
+#define __builtin_ia32_tilezero(A) __builtin_ia32_tilezero (1)
+#endif
+
#include <wmmintrin.h>
#include <immintrin.h>
#include <mm3dnow.h>
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index 241c36e8cfd..f1877802575 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -93,6 +93,7 @@ extern void test_amx_fp8 (void)
__attribute__((__target__("amx-f
extern void test_movrs (void)
__attribute__((__target__("movrs")));
extern void test_amx_movrs (void)
__attribute__((__target__("amx-movrs")));
extern void test_avx10v2aux (void)
__attribute__((__target__("avx10v2aux")));
+extern void test_acev1 (void)
__attribute__((__target__("acev1")));
extern void test_no_sgx (void)
__attribute__((__target__("no-sgx")));
extern void test_no_avx512vpopcntdq(void)
__attribute__((__target__("no-avx512vpopcntdq")));
@@ -187,6 +188,7 @@ extern void test_no_amx_fp8 (void)
__attribute__((__target__("no-am
extern void test_no_movrs (void)
__attribute__((__target__("no-movrs")));
extern void test_no_amx_movrs (void)
__attribute__((__target__("no-amx-movrs")));
extern void test_no_avx10v2aux (void)
__attribute__((__target__("no-avx10v2aux")));
+extern void test_no_acev1 (void)
__attribute__((__target__("no-acev1")));
extern void test_arch_nocona (void)
__attribute__((__target__("arch=nocona")));
extern void test_arch_core2 (void)
__attribute__((__target__("arch=core2")));
diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c
b/gcc/testsuite/gcc.target/i386/sse-12.c
index 6b05962b3c2..7d8cb38b561 100644
--- a/gcc/testsuite/gcc.target/i386/sse-12.c
+++ b/gcc/testsuite/gcc.target/i386/sse-12.c
@@ -3,7 +3,7 @@
popcntintrin.h gfniintrin.h and mm_malloc.h are usable
with -O -std=c89 -pedantic-errors. */
/* { dg-do compile } */
-/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx
-mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm
-mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr
-mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku
-msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect
-mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni
-mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex
-mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs
-mamx-movrs -mavx10v2aux" } */
+/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx
-mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm
-mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr
-mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku
-msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect
-mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni
-mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex
-mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs
-mamx-movrs -mavx10v2aux -macev1" } */
#include <x86intrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c
b/gcc/testsuite/gcc.target/i386/sse-13.c
index 356c2d40d27..0bb1a886ddb 100644
--- a/gcc/testsuite/gcc.target/i386/sse-13.c
+++ b/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a
-m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi
-mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw
-madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt
-mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni
-mpconfig -mwbnoinvd -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8
-mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert
-mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3
-msha512 -msm4 -mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs
-mavx10v2aux" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a
-m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi
-mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw
-madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt
-mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni
-mpconfig -mwbnoinvd -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8
-mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert
-mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3
-msha512 -msm4 -mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs
-mavx10v2aux -macev1" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
@@ -925,4 +925,9 @@
#define __builtin_ia32_vunpackb256_mask(A, B, C, M)
__builtin_ia32_vunpackb256_mask(A, 8, C, M)
#define __builtin_ia32_vunpackb512_mask(A, B, C, M)
__builtin_ia32_vunpackb512_mask(A, 8, C, M)
+/* acev1intrin.h */
+#ifdef __x86_64__
+#define __builtin_ia32_tilezero(A) __builtin_ia32_tilezero (1)
+#endif
+
#include <x86intrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c
b/gcc/testsuite/gcc.target/i386/sse-14.c
index 03dfd6cc074..9842d8fcbb9 100644
--- a/gcc/testsuite/gcc.target/i386/sse-14.c
+++ b/gcc/testsuite/gcc.target/i386/sse-14.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a
-m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi
-mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw
-madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx
-mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd
-mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16
-mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16
-mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2
-mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux" } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a
-m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi
-mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw
-madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx
-mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd
-mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16
-mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16
-mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2
-mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
@@ -24,6 +24,10 @@
type _CONCAT(_,func) (int const I) \
{ return func (imm); }
+#define test_0v(func, imm) \
+ void _CONCAT(_,func) (int const I) \
+ { func (imm); }
+
#define test_1(func, type, op1_type, imm) \
type _CONCAT(_,func) (op1_type A, int const I) \
{ return func (A, imm); }
@@ -1199,3 +1203,8 @@ test_3 (_mm256_mask_unpack_epi8, __m256i, __m256i,
__mmask32, __m256i, 8)
test_1 (_mm512_unpack_epi8, __m512i, __m512i, 8)
test_2 (_mm512_maskz_unpack_epi8, __m512i, __mmask64, __m512i, 8)
test_3 (_mm512_mask_unpack_epi8, __m512i, __m512i, __mmask64, __m512i, 8)
+
+/* acev1intrin.h */
+#ifdef __x86_64__
+test_0v (_tile_ace_zero, 1)
+#endif
diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c
b/gcc/testsuite/gcc.target/i386/sse-22.c
index 50a5280c18b..040826d442e 100644
--- a/gcc/testsuite/gcc.target/i386/sse-22.c
+++ b/gcc/testsuite/gcc.target/i386/sse-22.c
@@ -26,6 +26,10 @@
type _CONCAT(_,func) (int const I) \
{ return func (imm); }
+#define test_0v(func, imm) \
+ void _CONCAT(_,func) (int const I) \
+ { func (imm); }
+
#define test_1(func, type, op1_type, imm) \
type _CONCAT(_,func) (op1_type A, int const I) \
{ return func (A, imm); }
@@ -103,7 +107,7 @@
#ifndef DIFFERENT_PRAGMAS
-#pragma GCC target
("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux")
+#pragma GCC target
("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1")
#endif
/* Following intrinsics require immediate arguments. They
@@ -220,7 +224,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
/* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */
#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target
("avx,avx2,rdrnd,fsgsbase,f16c,rtm,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux")
+#pragma GCC target
("avx,avx2,rdrnd,fsgsbase,f16c,rtm,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1")
#endif
#include <immintrin.h>
test_1 (_cvtss_sh, unsigned short, float, 1)
@@ -1240,3 +1244,8 @@ test_3 (_mm256_mask_unpack_epi8, __m256i, __m256i,
__mmask32, __m256i, 8)
test_1 (_mm512_unpack_epi8, __m512i, __m512i, 8)
test_2 (_mm512_maskz_unpack_epi8, __m512i, __mmask64, __m512i, 8)
test_3 (_mm512_mask_unpack_epi8, __m512i, __m512i, __mmask64, __m512i, 8)
+
+/* acev1intrin.h */
+#ifdef __x86_64__
+test_0v (_tile_ace_zero, 1)
+#endif
diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c
b/gcc/testsuite/gcc.target/i386/sse-23.c
index 6fae64c57fd..3edebe4c328 100644
--- a/gcc/testsuite/gcc.target/i386/sse-23.c
+++ b/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -900,6 +900,11 @@
#define __builtin_ia32_vunpackb256_mask(A, B, C, M)
__builtin_ia32_vunpackb256_mask(A, 8, C, M)
#define __builtin_ia32_vunpackb512_mask(A, B, C, M)
__builtin_ia32_vunpackb512_mask(A, 8, C, M)
-#pragma GCC target
("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux")
+/* acev1intrin.h */
+#ifdef __x86_64__
+#define __builtin_ia32_tilezero(A) __builtin_ia32_tilezero (1)
+#endif
+
+#pragma GCC target
("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1")
#include <x86intrin.h>
--
2.31.1
