This patch series mainly implements support for the naming convention of OpenMP
vectorized functions on RISC-V. This specification has been merged into the
riscv-elf-psabi document, details are available at

https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/455

There are two patches in this series:

1. The first patch adds support for ISA mangling values exceeding one byte.
2. The second patch introduces three target hooks for RISC-V:
   1) TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
   2) TARGET_SIMD_CLONE_ADJUST
   3) TARGET_SIMD_CLONE_USABLE.

Zhijin Zeng (2):
  OpenMP: Support ISA mangles longer than one byte
  RISC-V: support name mangling for vector function

 gcc/cgraph.h                                  |   5 +
 gcc/config/riscv/riscv.cc                     | 319 +++++++++++++++++-
 gcc/omp-simd-clone.cc                         |   5 +-
 .../g++.target/riscv/rvv/autovec/simd-L-vls.C |  19 ++
 .../riscv/rvv/autovec/simd-Ls-vls.C           |  18 +
 .../g++.target/riscv/rvv/autovec/simd-M-vls.C |  18 +
 .../g++.target/riscv/rvv/autovec/simd-R-vls.C |  20 ++
 .../riscv/rvv/autovec/simd-Rs-vls.C           |  19 ++
 .../g++.target/riscv/rvv/autovec/simd-U-vls.C |  18 +
 .../riscv/rvv/autovec/simd-Us-vls.C           |  19 ++
 .../g++.target/riscv/rvv/autovec/simd-l-vls.C |  21 ++
 .../riscv/rvv/autovec/simd-ls-vls.C           |  19 ++
 .../g++.target/riscv/rvv/autovec/simd-u-vls.C |  18 +
 .../g++.target/riscv/rvv/autovec/simd-v-vls.C |  21 ++
 .../riscv/rvv/autovec/libmvec-exp-vls.c       |  38 +++
 .../riscv/rvv/autovec/libmvec-log-vla.c       |  32 ++
 .../riscv/rvv/autovec/libmvec-pow-vla.c       |  20 ++
 17 files changed, 627 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/simd-L-vls.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/simd-Ls-vls.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/simd-M-vls.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/simd-R-vls.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/simd-Rs-vls.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/simd-U-vls.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/simd-Us-vls.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/simd-l-vls.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/simd-ls-vls.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/simd-u-vls.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/simd-v-vls.C
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/libmvec-exp-vls.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/libmvec-log-vla.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/libmvec-pow-vla.c

-- 
2.25.1

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