I'm seeing lra ICEs on the CI, are you able to reproduce them? If so, maybe there is still an oversight in lra handling?
-- Regards Robin
- [PATCH v1 0/3] Support RVV register overlap for v[sz]ext.vf2 pan2 . li
- [PATCH v1 1/3] RISC-V: Allow RVV register overlap for v[sz... pan2 . li
- [PATCH v1 2/3] RISC-V: Add test cases for vsext.vf2 reg ov... pan2 . li
- [PATCH v1 3/3] RISC-V: Add test cases for vzext.vf2 reg ov... pan2 . li
- Re: [PATCH v1 0/3] Support RVV register overlap for v[sz]e... Robin Dapp
