From: Pan Li <[email protected]>
Like v[sz]ext.vf2, allow the rvv register overlap
for v[sz]ext.vf4.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (is_frac_vlmul_p): Add new func
decl to predicate frac vlmul for a mode.
* config/riscv/riscv-v.cc (is_frac_vlmul_p): Add new func impl
for above.
(riscv_v_widen_constraint_ok): Add Source and Dest lmul less
and equal 1 handling.
* config/riscv/vector.md: Leverage widen constraint Wvr.
Signed-off-by: Pan Li <[email protected]>
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 26 +++++++++++++++++++++++++-
gcc/config/riscv/vector.md | 16 ++++++++--------
3 files changed, 34 insertions(+), 9 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index e7bce0db7a3..b72d660f37e 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -642,6 +642,7 @@ void emit_nonvlmax_insn (unsigned, unsigned, rtx *, rtx);
void emit_avltype_insn (unsigned, unsigned, rtx *, avl_type, rtx = nullptr);
void emit_vlmax_insn_lra (unsigned, unsigned, rtx *, rtx);
enum vlmul_type get_vlmul (machine_mode);
+bool is_frac_vlmul_p (machine_mode);
rtx get_vlmax_rtx (machine_mode);
unsigned int get_ratio (machine_mode);
unsigned int get_nf (machine_mode);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 48cc56ea3d9..c4e62cfc372 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2054,6 +2054,27 @@ get_vlmul (machine_mode mode)
return mode_vtype_infos.vlmul[mode];
}
+bool
+is_frac_vlmul_p (machine_mode mode)
+{
+ switch (get_vlmul (mode))
+ {
+ case LMUL_1:
+ case LMUL_2:
+ case LMUL_4:
+ case LMUL_8:
+ return false;
+ case LMUL_F8:
+ case LMUL_F4:
+ case LMUL_F2:
+ return true;
+ default:
+ break;
+ }
+
+ gcc_unreachable ();
+}
+
/* Return the VLMAX rtx of vector mode MODE. */
rtx
get_vlmax_rtx (machine_mode mode)
@@ -6505,7 +6526,7 @@ riscv_v_widen_constraint_ok (unsigned int regno,
machine_mode mode,
unsigned int wide_nregs = riscv_hard_regno_nregs (wide_regno, wide_mode);
unsigned int nregs = riscv_hard_regno_nregs (regno, mode);
- if (wide_nregs == nregs) /* Source LMUL < 1. */
+ if (wide_nregs == nregs) /* Dest LMUL <= 1. */
{
gcc_checking_assert (nregs == 1);
@@ -6519,6 +6540,9 @@ riscv_v_widen_constraint_ok (unsigned int regno,
machine_mode mode,
if (regno + nregs <= wide_regno || wide_regno + wide_nregs <= regno)
return true;
+ if (is_frac_vlmul_p (mode)) /* Source LMUL < 1. */
+ return false;
+
unsigned int highest_num = wide_nregs - nregs;
return (regno % wide_nregs) == highest_num;
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 5d22edb0f3f..a5ebc85b764 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -4110,19 +4110,19 @@ (define_insn "@pred_<optab><mode>_vf2"
;; Vector Quad-Widening Sign-extend and Zero-extend.
(define_insn "@pred_<optab><mode>_vf4"
- [(set (match_operand:VQEXTI 0 "register_operand" "=&vr,&vr")
+ [(set (match_operand:VQEXTI 0 "register_operand" "=vr, vr, vd,
vd")
(if_then_else:VQEXTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rvl, rvl")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "Wc1, Wc1, vm,
vm")
+ (match_operand 4 "vector_length_operand" "rvl, rvl, rvl,
rvl")
+ (match_operand 5 "const_int_operand" " i, i, i,
i")
+ (match_operand 6 "const_int_operand" " i, i, i,
i")
+ (match_operand 7 "const_int_operand" " i, i, i,
i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_extend:VQEXTI
- (match_operand:<V_QUAD_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VQEXTI 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<V_QUAD_TRUNC> 3 "register_operand" "Wvr, Wvr, Wvr,
Wvr"))
+ (match_operand:VQEXTI 2 "vector_merge_operand" " vu, 0, vu,
0")))]
"TARGET_VECTOR && !TARGET_XTHEADVECTOR"
"v<sz>ext.vf4\t%0,%3%p1"
[(set_attr "type" "vext")
--
2.43.0
