Hi Andrew! On 2026-07-06T09:13:17+0000, Andrew Stubbs <[email protected]> wrote: > The TImode vector vec_set instructions were missing, leading to an ICE > compiling testcase gcc.dg/pr78526.c (although it only shows with other patches > not yet committed).
No, in fact we've had that ICE for a long time already: <https://inbox.sourceware.org/[email protected]> "Re: [committed] amdgcn: minimal V64TImode vector support". ..., and I confirm that it's now gone. (The other ICEs mentioned in my 2023 email had already gotten resolved.) Grüße Thomas > gcc/ChangeLog: > > * config/gcn/gcn-valu.md (*vec_set<mode>): Ad TImode instruction. > --- > gcc/config/gcn/gcn-valu.md | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) > > diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md > index 253d13279c0..edd5bf1f1d2 100644 > --- a/gcc/config/gcn/gcn-valu.md > +++ b/gcc/config/gcn/gcn-valu.md > @@ -697,8 +697,6 @@ (define_insn "*vec_set<mode>" > (set_attr "exec" "none") > (set_attr "laneselect" "write")]) > > -; FIXME: 64bit operations really should be splitters, but I am not sure how > -; to represent vertical subregs. > (define_insn "*vec_set<mode>" > [(set (match_operand:V_2REG 0 "register_operand" "= v") > (vec_merge:V_2REG > @@ -714,6 +712,21 @@ (define_insn "*vec_set<mode>" > (set_attr "exec" "none") > (set_attr "laneselect" "write")]) > > +(define_insn "*vec_set<mode>" > + [(set (match_operand:V_4REG 0 "register_operand" "= v") > + (vec_merge:V_4REG > + (vec_duplicate:V_4REG > + (match_operand:<SCALAR_MODE> 1 "register_operand" " Sv")) > + (match_operand:V_4REG 3 "gcn_register_or_unspec_operand" " U0") > + (ashift (const_int 1) > + (match_operand:SI 2 "gcn_alu_operand" "SvB"))))] > + "" > + "v_writelane_b32 %L0, %L1, %2\;v_writelane_b32 %H0, %H1, > %2\;v_writelane_b32 %J0, %J1, %2\;v_writelane_b32 %K0, %K1, %2" > + [(set_attr "type" "vmult") > + (set_attr "length" "32") > + (set_attr "exec" "none") > + (set_attr "laneselect" "write")]) > + > (define_expand "vec_set<mode>" > [(set (match_operand:V_MOV 0 "register_operand") > (vec_merge:V_MOV > -- > 2.54.0
