On 7/9/2026 10:08 AM, Andrew Stubbs wrote:
The ISA has only one way to load vectors*: a vector of absolute
addresses goes in, and a vector of data comes out. The address vector
needs to be in the VGPR_REGS register class.
Sounds fairly painful :-)
But, the compiler doesn't generate address vectors when it does stack
spills and reloads, so we also support the more normal base address
style of addressing, and then convert it later using a split. In that
case the base address needs to be in class SGPR_REGS (or else the
vec_duplicate instruction won't work).
You probably already explored the secondary register class path to get
the right register class. That's traditionally been the way to do
handle this. I don't remember the interfaces off the top of my head,
but I think you get an operand (which may be another reg, MEM, whatever)
and a register class. If you require an extra register to implement
that move, then you return the class you need and you'll get another
reg. Then you hack up your movXX or reload_* patterns to make use of it.
You can't tell which variety of address is in use just by looking at
the mode and address space by themselves (which is all we have in the
regular hook): it could be DImode or V64DImode. By looking at the
whole MEM we can see the whole picture. Actually all we need to see
is the mode of the address expression.
This is one of those cases were I think I'm missing something. If you
have the MEM, then you have the mode of the address, though perhaps not
the full computation of the address. And it looks like the address is
always Pmode on GCN. I must be mis-understanding your requirements.
jeff
