PR target/115042 was a [14/15] regression: a valgrind DSP test
(none/tests/arm/v6media.c) failed to compile on armv7 in Thumb state at
-O0 with "asm operand has impossible constraints or there are not enough
registers". The failing inline asm clobbers r0-r3 while also requiring
two early-clobber outputs and four inputs.
This was fixed on trunk by r16-7879 ("Postpone processing of new reload
insns, 2nd variant", an LRA fix -- lra.cc / lra-constraints.cc; an
earlier attempt, r16-7745, was reverted). That commit intentionally
carried no testcase: the original translation unit is ~300KB and two
days of cvise only reduced it to 100KB. Add the reporter's reduced
smlaltt inline asm as a small gcc.target/arm regression test to guard
the LRA fix. The bug remains tracked for a releases/gcc-14 backport
decision, so this test is a trunk-side guard, not a close-out.
gcc/testsuite/ChangeLog:
PR target/115042
* gcc.target/arm/pr115042.c: New test.
Signed-off-by: Dominic P <[email protected]>
---
PR115042 is formally tracked as a [14/15/16/17] regression. The fixing
commit on trunk is r16-7879 (V. Makarov, LRA -- the earlier r16-7745 was
reverted); it shipped without a testcase because the original reproducer
was too large to reduce, which is the gap this test fills. The
substantive fix is in LRA, not the arm backend -- this test is only the
guard. The PR should stay open for the release managers' gcc-14 branch
backport decision; this test does not close it.
This patch was prepared with the assistance of an AI coding tool. Every line of
code, every test and every measurement was written, reviewed and verified by the
author, who takes responsibility for the patch; the Signed-off-by above
certifies
the Developer Certificate of Origin.
gcc/testsuite/gcc.target/arm/pr115042.c | 42 +++++++++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/arm/pr115042.c
diff --git a/gcc/testsuite/gcc.target/arm/pr115042.c
b/gcc/testsuite/gcc.target/arm/pr115042.c
new file mode 100644
index 000000000..20489b651
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr115042.c
@@ -0,0 +1,42 @@
+/* PR target/115042: a valgrind DSP test (none/tests/arm/v6media.c) stopped
+ compiling on armv7 Thumb at -O0. The inline asm below clobbers r0-r3 and
+ also needs two early-clobber outputs plus four inputs; GCC 14/15 rejected it
+ with "asm operand has impossible constraints or there are not enough
+ registers" in Thumb state at -O0. It must compile. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-require-effective-target arm_dsp } */
+/* { dg-options "-O0 -mthumb" } */
+
+extern int printf (const char *, ...);
+
+static unsigned int gen_cin (int x) { return x ? (1u << 29) : 0; }
+
+#define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, carryin) \
+{ \
+ unsigned int out; \
+ unsigned int cpsr; \
+ __asm__ volatile( \
+ "msr cpsr_fs, %5;" \
+ "mov " #RM ",%2;" \
+ "mov " #RN ",%3;" \
+ "mov " #RS ",%4;" \
+ instruction ";" \
+ "mov %0," #RD ";" \
+ "mrs %1,cpsr;" \
+ : "=&r" (out), "=&r" (cpsr) \
+ : "r" (RMval), "r" (RNval), "r" (RSval), "r" (gen_cin(carryin)) \
+ : #RD, #RM, #RN, #RS, "cc", "memory" \
+ ); \
+ printf("%08x %08x\n", out, cpsr); \
+}
+
+void
+foo (void)
+{
+ TESTINST4 ("smlaltt r0, r1, r2, r3",
+ 0x11111111, 0x22222222, 0x33333333, r0, r1, r2, r3, 0);
+}
+
+/* { dg-final { scan-assembler "smlaltt" } } */
--
2.55.0
