Ping. I'll also submit a PR. This was broken since GCC 15 and I'd like it to be backported.
Michiel ________________________________ From: Michiel Derhaeg <[email protected]> Sent: Tuesday, June 16, 2026 9:29 PM To: [email protected] <[email protected]> Cc: [email protected] <[email protected]> Subject: [PATCH] arc: Don't advertise optab for unsupported vector modes From: Michiel Derhaeg <[email protected]> <voptab>v2si3 advertised V2SImode optabs (mul/div/smin/smax) whenever the scalar op existed, but V2SImode is only a supported vector mode under TARGET_PLUS_QMACW. On such cores the middle-end kept the operation vectorized, the operands degraded to DImode, and it was expanded as a double-word scalar op. Require TARGET_PLUS_QMACW so the optab matches arc_vector_mode_supported_p. No tests added because this is covered already by tests that started failing after 485ab50. gcc/ChangeLog: * config/arc/simdext.md (<voptab>v2si3): Require TARGET_PLUS_QMACW. Signed-off-by: Michiel Derhaeg <[email protected]> --- gcc/config/arc/simdext.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md index 94ea0884b726..a3ac8d77713c 100644 --- a/gcc/config/arc/simdext.md +++ b/gcc/config/arc/simdext.md @@ -2007,7 +2007,7 @@ [(set (match_operand:V2SI 0 "register_operand" "=r") (EMUVEC:V2SI (match_operand:V2SI 1 "register_operand" "r") (match_operand:V2SI 2 "nonmemory_operand" "ri")))] - "" + "TARGET_PLUS_QMACW" "#" "reload_completed" [(const_int 0)] -- 2.47.3 GF Confidential – Need to know
