On Wed, Jul 8, 2026 at 4:48 PM Andrew Stubbs <[email protected]> wrote: > > Hi all, > > This patch series implements the "MEMs with address vectors" feature > that I want to use in AMD GCN, and have previously discussed on gcc@. > The motivation is to simplify a new back-end optimization pass I'm > working on and plan to post in the coming weeks. > > The first patch, in this series, is the middle-end enablement and > documentation changes. > > The second patch converts the amdgcn back-end to use the new scheme, > without adding any real new features. It depends on the > INSN_BASE_REG_CLASS patch I posted last week (still in review) to run > correctly. > > The third and final patch demonstrates how I can use the new MEM to > extend my machine description without writing whole new insns for the > vector modes, just for them to evaluate to the same assembler code in > the end. > > I have not yet finished testing the patches, so these might not be quite > the final form, but I'm not expecting big changes to the middle-end > portion. (I can self-approve the amdgcn parts, once the other is > committed, but comments are welcome.) > > OK for mainline? (Pending test results.)
I think this exposes what GCN does in a natural way. I'm not sure the advantage (exposing former gather/scatter as move) is not also its disadvantage (moves are special!), and I somewhat question the benefit over using some UNSPEC for this. For example I would assume that you side-step RTL alias/dependence analysis, meaning these are barriers for optimization and scheduling? The proposed semantics (overlap has undefined behavior) does not match up with usual vector ISA scatter semantics (left-to-right), so the representation isn't universally useable (if we solve the masking issue). That said, my overall hunch is that we're extending general RTL semantics in a somewhat ad-hoc (and incomplete?) way. Not that I have a better idea here. Thanks, Richard. > > Thanks > > Andrew Stubbs (3): > rtl: Allow "(mem:<vecmode> (reg:<vecmode>))" > amdgcn: Implement "(mem (reg:<vecmode>))" > amdgcn: Add vector atomics > > gcc/config/gcn/constraints.md | 49 ++- > gcc/config/gcn/gcn-protos.h | 10 +- > gcc/config/gcn/gcn-valu.md | 745 ++++++++++++---------------------- > gcc/config/gcn/gcn.cc | 529 +++++++++++++----------- > gcc/config/gcn/gcn.h | 1 + > gcc/config/gcn/gcn.md | 123 +++--- > gcc/doc/rtl.texi | 8 + > gcc/doc/tm.texi | 13 +- > gcc/emit-rtl.cc | 30 +- > gcc/explow.cc | 12 +- > gcc/recog.cc | 4 +- > gcc/rtl.h | 2 +- > gcc/rtlanal.cc | 4 +- > gcc/simplify-rtx.cc | 5 +- > gcc/target.def | 13 +- > gcc/targhooks.cc | 4 +- > gcc/targhooks.h | 3 +- > 17 files changed, 768 insertions(+), 787 deletions(-) > > -- > 2.54.0 >
