Hi Richard,
> On 31 May 2026, at 13:16, ricbal02 via Sourceware Forge
> <[email protected]> wrote:
>
> From: Richard Ball <[email protected]>
>
> This patch adds support for new intrinsics which make use of
> the conversion instructions introduced in SVE2p3/SME2p3.
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-sve-builtins-sve2.cc
> (class svcvtt_impl): New function impl.
> (class svcvtb_impl): Likewise.
> (FUNCTION): Likewise.
> * config/aarch64/aarch64-sve-builtins-sve2.def
> (REQUIRED_EXTENSIONS): List new functions.
> (svdot): Moved to correct location.
> (svdot_lane): Likewise.
> (svcvtn): New function.
> (svcvtt): Likewise.
> (svcvtb): Likewise.
> * config/aarch64/aarch64-sve-builtins-sve2.h: Likewise.
> * config/aarch64/aarch64-sve-builtins.cc
> (TYPES_cvtzn): New function types.
> (TYPES_cvttb): Likewise.
> (cvtzn): Likewise.
> (cvttb): Likewise.
> * config/aarch64/aarch64-sve2.md
> (@aarch64_sve2_scvtfb<mode>): New pattern.
> (@aarch64_sve2_scvtflt<mode>): Likewise.
> (@aarch64_sve2_ucvtfb<mode>): Likewise.
> (@aarch64_sve2_ucvtflt<mode>): Likewise.
> (@aarch64_sve2_fcvtzsn<mode>): Likewise.
> (@aarch64_sve2_fcvtzun<mode>): Likewise.
> * config/aarch64/iterators.md
> (b): Ventype changes.
> (VNx16HF): Likewise.
> (VNx16QI): Likewise.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/aarch64/sme2/acle-asm/cvtb_f16_s8.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtb_f16_u8.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtb_f32_s16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtb_f32_u16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtb_f64_s32.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtb_f64_u32.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtn_s16_f32_x2.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtn_s32_f64_x2.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtn_s8_f16_x2.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtn_u16_f32_x2.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtn_u32_f64_x2.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtn_u8_f16_x2.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtt_f16_s8.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtt_f16_u8.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtt_f32_s16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtt_f32_u16.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtt_f64_s32.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/cvtt_f64_u32.c: New test.
> ---
> .../aarch64/aarch64-sve-builtins-sve2.cc | 38 +++++++++-
> .../aarch64/aarch64-sve-builtins-sve2.def | 13 ++--
> .../aarch64/aarch64-sve-builtins-sve2.h | 2 +
> gcc/config/aarch64/aarch64-sve-builtins.cc | 18 +++++
> gcc/config/aarch64/aarch64-sve2.md | 75 +++++++++++++++++++
> gcc/config/aarch64/iterators.md | 16 +++-
> .../aarch64/sme2/acle-asm/cvtb_f16_s8.c | 22 ++++++
> .../aarch64/sme2/acle-asm/cvtb_f16_u8.c | 22 ++++++
> .../aarch64/sme2/acle-asm/cvtb_f32_s16.c | 22 ++++++
> .../aarch64/sme2/acle-asm/cvtb_f32_u16.c | 22 ++++++
> .../aarch64/sme2/acle-asm/cvtb_f64_s32.c | 22 ++++++
> .../aarch64/sme2/acle-asm/cvtb_f64_u32.c | 22 ++++++
> .../aarch64/sme2/acle-asm/cvtn_s16_f32_x2.c | 51 +++++++++++++
> .../aarch64/sme2/acle-asm/cvtn_s32_f64_x2.c | 51 +++++++++++++
> .../aarch64/sme2/acle-asm/cvtn_s8_f16_x2.c | 51 +++++++++++++
> .../aarch64/sme2/acle-asm/cvtn_u16_f32_x2.c | 51 +++++++++++++
> .../aarch64/sme2/acle-asm/cvtn_u32_f64_x2.c | 51 +++++++++++++
> .../aarch64/sme2/acle-asm/cvtn_u8_f16_x2.c | 51 +++++++++++++
> .../aarch64/sme2/acle-asm/cvtt_f16_s8.c | 22 ++++++
> .../aarch64/sme2/acle-asm/cvtt_f16_u8.c | 22 ++++++
> .../aarch64/sme2/acle-asm/cvtt_f32_s16.c | 22 ++++++
> .../aarch64/sme2/acle-asm/cvtt_f32_u16.c | 22 ++++++
> .../aarch64/sme2/acle-asm/cvtt_f64_s32.c | 22 ++++++
> .../aarch64/sme2/acle-asm/cvtt_f64_u32.c | 22 ++++++
> 24 files changed, 725 insertions(+), 7 deletions(-)
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_s8.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_u8.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_s16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_u16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_s32.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_u32.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s16_f32_x2.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s32_f64_x2.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s8_f16_x2.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u16_f32_x2.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u32_f64_x2.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u8_f16_x2.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_s8.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_u8.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_s16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_u16.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_s32.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_u32.c
>
> diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
> b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
> index 5ea08056ae3d..174d9cac381f 100644
> --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
> +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
> @@ -246,8 +246,42 @@ public:
> insn_code icode;
> if (e.fpm_mode == FPM_set)
> icode = code_for_aarch64_sve2_fp8_cvtn (GET_MODE (e.args[0]));
> - else
> + else if (e.type_suffix (0).float_p)
> icode = code_for_aarch64_sve_cvtn (e.result_mode ());
> + else if (e.type_suffix (0).unsigned_p)
> + icode = code_for_aarch64_sve2_fcvtzun (e.result_mode ());
> + else
> + icode = code_for_aarch64_sve2_fcvtzsn (e.result_mode ());
> + return e.use_exact_insn (icode);
> + }
> +};
> +
> +class svcvtt_impl : public function_base
> +{
> +public:
> + rtx
> + expand (function_expander &e) const override
> + {
> + insn_code icode;
> + if (e.type_suffix (1).unsigned_p)
> + icode = code_for_aarch64_sve2_ucvtflt (e.result_mode ());
> + else
> + icode = code_for_aarch64_sve2_scvtflt (e.result_mode ());
> + return e.use_exact_insn (icode);
> + }
> +};
> +
> +class svcvtb_impl : public function_base
> +{
> +public:
> + rtx
> + expand (function_expander &e) const override
> + {
> + insn_code icode;
> + if (e.type_suffix (1).unsigned_p)
> + icode = code_for_aarch64_sve2_ucvtfb (e.result_mode ());
> + else
> + icode = code_for_aarch64_sve2_scvtfb (e.result_mode ());
> return e.use_exact_insn (icode);
> }
> };
> @@ -1076,6 +1110,8 @@ FUNCTION (svcvtn, svcvtn_impl,)
> FUNCTION (svcvtnb, fixed_insn_function,
> (CODE_FOR_aarch64_sve2_fp8_cvtnbvnx16qi))
> FUNCTION (svcvtx, unspec_based_function, (-1, -1, UNSPEC_COND_FCVTX))
> FUNCTION (svcvtxnt, NARROWING_TOP_CONVERT1 (aarch64_sve2_cvtxnt),)
> +FUNCTION (svcvtt, svcvtt_impl,)
> +FUNCTION (svcvtb, svcvtb_impl,)
> FUNCTION (svdup_laneq, svdup_laneq_impl,)
> FUNCTION (sveor3, CODE_FOR_MODE0 (aarch64_sve2_eor3),)
> FUNCTION (sveorbt, unspec_based_function, (UNSPEC_EORBT, UNSPEC_EORBT, -1))
> diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
> b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
> index 63c1c27074ce..ab528cb92bea 100644
> --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
> +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
> @@ -314,6 +314,14 @@ DEF_SVE_FUNCTION (svrint64x, unary, sd_float, mxz)
> DEF_SVE_FUNCTION (svrint64z, unary, sd_float, mxz)
> #undef REQUIRED_EXTENSIONS
>
> +#define REQUIRED_EXTENSIONS sve_and_sme (AARCH64_FL_SVE2p3,
> AARCH64_FL_SME2p3)
> +DEF_SVE_FUNCTION (svdot, ternary_qq_opt_n_or_011, s_narrow_fsu_sve2p3, none)
> +DEF_SVE_FUNCTION (svdot_lane, ternary_qq_or_011_lane, s_narrow_fsu_sve2p3,
> none)
> +DEF_SVE_FUNCTION_GS (svcvtn, unary_convertxn, cvtzn, x2, none)
> +DEF_SVE_FUNCTION (svcvtt, unary_convert, cvttb, none)
> +DEF_SVE_FUNCTION (svcvtb, unary_convert, cvttb, none)
> +#undef REQUIRED_EXTENSIONS
> +
> #define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2)
> DEF_SVE_FUNCTION_GS (svadd, binary_single, all_integer, x24, none)
> DEF_SVE_FUNCTION_GS (svclamp, clamp, all_arith, x24, none)
> @@ -463,11 +471,6 @@ DEF_SVE_FUNCTION_GS_FPM (svmmla, mmla, h_float_mf8,
> none, none, set)
> DEF_SVE_FUNCTION_GS_FPM (svmmla, mmla, s_float_mf8, none, none, set)
> #undef REQUIRED_EXTENSIONS
>
> -#define REQUIRED_EXTENSIONS sve_and_sme (AARCH64_FL_SVE2p3,
> AARCH64_FL_SME2p3)
> -DEF_SVE_FUNCTION (svdot, ternary_qq_opt_n_or_011, s_narrow_fsu_sve2p3, none)
> -DEF_SVE_FUNCTION (svdot_lane, ternary_qq_or_011_lane, s_narrow_fsu_sve2p3,
> none)
> -#undef REQUIRED_EXTENSIONS
> -
> #define REQUIRED_EXTENSIONS nonstreaming_sve (AARCH64_FL_SVE_F16F32MM)
> DEF_SVE_FUNCTION (svmmla, mmla, cvt_f32_f16, none)
> #undef REQUIRED_EXTENSIONS
> diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
> b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
> index b2f2698b8802..45061ff6eabb 100644
> --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
> +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
> @@ -70,6 +70,8 @@ namespace aarch64_sve
> extern const function_base *const svcvtlt1;
> extern const function_base *const svcvtlt2;
> extern const function_base *const svcvtn;
> + extern const function_base *const svcvtt;
> + extern const function_base *const svcvtb;
> extern const function_base *const svcvtnb;
> extern const function_base *const svcvtnt;
> extern const function_base *const svcvtx;
> diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc
> b/gcc/config/aarch64/aarch64-sve-builtins.cc
> index 04d7500845e3..85b30150c867 100644
> --- a/gcc/config/aarch64/aarch64-sve-builtins.cc
> +++ b/gcc/config/aarch64/aarch64-sve-builtins.cc
> @@ -514,6 +514,22 @@ CONSTEXPR const group_suffix_info group_suffixes[] = {
> #define TYPES_cvtnx_mf8(S, D, T) \
> D (mf8, f32)
>
> +#define TYPES_cvtzn(S, D, T) \
> + D (s8, f16), \
> + D (u8, f16), \
> + D (s16, f32), \
> + D (u16, f32), \
> + D (s32, f64), \
> + D (u32, f64)
> +
> +#define TYPES_cvttb(S, D, T) \
> + D (f16, s8), \
> + D (f16, u8), \
> + D (f32, s16), \
> + D (f32, u16), \
> + D (f64, s32), \
> + D (f64, u32)
> +
> /* { _s32 _s64 } x { _b8 _b16 _b32 _b64 }
> { _u32 _u64 }. */
> #define TYPES_inc_dec_n1(D, A) \
> @@ -860,6 +876,8 @@ DEF_SVE_TYPES_ARRAY (cvt_narrow);
> DEF_SVE_TYPES_ARRAY (cvt_s_s);
> DEF_SVE_TYPES_ARRAY (cvtn_mf8);
> DEF_SVE_TYPES_ARRAY (cvtnx_mf8);
> +DEF_SVE_TYPES_ARRAY (cvtzn);
> +DEF_SVE_TYPES_ARRAY (cvttb);
> DEF_SVE_TYPES_ARRAY (inc_dec_n);
> DEF_SVE_TYPES_ARRAY (qcvt_x2);
> DEF_SVE_TYPES_ARRAY (qcvt_x4);
> diff --git a/gcc/config/aarch64/aarch64-sve2.md
> b/gcc/config/aarch64/aarch64-sve2.md
> index 521029136fa9..a498e7ef4d0c 100644
> --- a/gcc/config/aarch64/aarch64-sve2.md
> +++ b/gcc/config/aarch64/aarch64-sve2.md
> @@ -105,6 +105,7 @@
> ;; == Conversions
> ;; ---- [FP<-FP] Widening conversions
> ;; ---- [FP<-FP] Narrowing conversions
> +;; ---- [FP<-INT] Widening conversions
> ;; ---- [FP<-FP] Multi-vector widening conversions
> ;; ---- [FP<-FP] Multi-vector narrowing conversions
> ;; ---- [FP<-INT] Multi-vector conversions
> @@ -3783,6 +3784,58 @@
> )
>
>
> +;; -------------------------------------------------------------------------
> +;; ---- [FP<-INT] Widening conversions
> +;; -------------------------------------------------------------------------
> +;; Includes:
> +;; - SCVTF (SME_2p3)
> +;; - SCVTFLT (SME_2p3)
> +;; - UCVTF (SME_2p3)
> +;; - UCVTFLT (SME_2p3)
> +;; -------------------------------------------------------------------------
> +
> +(define_insn "@aarch64_sve2_scvtfb<mode>"
> + [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w")
> + (unspec:SVE_FULL_F
> + [(match_operand:<CVTTB_SRC> 1 "register_operand" "w")]
> + UNSPEC_SCVTFB))]
> + "TARGET_SVE2p3_OR_SME2p3"
> + "scvtf\t%0.<Vetype>, %1.<Ventype>"
> + [(set_attr "sve_type" "sve_fp_cvt")]
> +)
> +
> +(define_insn "@aarch64_sve2_scvtflt<mode>"
> + [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w")
> + (unspec:SVE_FULL_F
> + [(match_operand:<CVTTB_SRC> 1 "register_operand" "w")]
> + UNSPEC_SCVTFLT))]
> + "TARGET_SVE2p3_OR_SME2p3"
> + "scvtflt\t%0.<Vetype>, %1.<Ventype>"
> + [(set_attr "sve_type" "sve_fp_cvt")]
> +)
> +
> +(define_insn "@aarch64_sve2_ucvtfb<mode>"
> + [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w")
> + (unspec:SVE_FULL_F
> + [(match_operand:<CVTTB_SRC> 1 "register_operand" "w")]
> + UNSPEC_UCVTFB))]
> + "TARGET_SVE2p3_OR_SME2p3"
> + "ucvtf\t%0.<Vetype>, %1.<Ventype>"
> + [(set_attr "sve_type" "sve_fp_cvt")]
> +)
> +
> +(define_insn "@aarch64_sve2_ucvtflt<mode>"
> + [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w")
> + (unspec:SVE_FULL_F
> + [(match_operand:<CVTTB_SRC> 1 "register_operand" "w")]
> + UNSPEC_UCVTFLT))]
> + "TARGET_SVE2p3_OR_SME2p3"
> + "ucvtflt\t%0.<Vetype>, %1.<Ventype>"
> + [(set_attr "sve_type" "sve_fp_cvt")]
> +)
> +
> +
> +
> ;; -------------------------------------------------------------------------
> ;; ---- [FP<-FP] Multi-vector widening conversions
> ;; -------------------------------------------------------------------------
> @@ -3918,6 +3971,8 @@
> ;; Includes the multi-register forms of:
> ;; - FCVTZS (SME2)
> ;; - FCVTZU (SME2)
> +;; - FCVTZSN (SME2p3)
> +;; - FCVTZUN (SME2p3)
> ;; -------------------------------------------------------------------------
>
> (define_insn "<optab><mode><v_int_equiv>2"
> @@ -3929,6 +3984,26 @@
> [(set_attr "sve_type" "sve_fp_cvt")]
> )
>
> +(define_insn "@aarch64_sve2_fcvtzsn<mode>"
> + [(set (match_operand:SVE_FULL_BHSI 0 "register_operand" "=w")
> + (unspec:SVE_FULL_BHSI
> + [(match_operand:<FCVTZN_SRC> 1 "aligned_register_operand" "Uw2")]
> + UNSPEC_FCVTZSN))]
> + "TARGET_SVE2p3_OR_SME2p3"
> + "fcvtzsn\t%0.<Vetype>, %1"
> + [(set_attr "sve_type" "sve_fp_cvt")]
> +)
> +
> +(define_insn "@aarch64_sve2_fcvtzun<mode>"
> + [(set (match_operand:SVE_FULL_BHSI 0 "register_operand" "=w")
> + (unspec:SVE_FULL_BHSI
> + [(match_operand:<FCVTZN_SRC> 1 "aligned_register_operand" "Uw2")]
> + UNSPEC_FCVTZUN))]
> + "TARGET_SVE2p3_OR_SME2p3"
> + "fcvtzun\t%0.<Vetype>, %1"
> + [(set_attr "sve_type" "sve_fp_cvt")]
> +)
> +
> ;; =========================================================================
> ;; == Other arithmetic
> ;; =========================================================================
> diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
> index 37f819ce6493..64363665c60a 100644
> --- a/gcc/config/aarch64/iterators.md
> +++ b/gcc/config/aarch64/iterators.md
> @@ -1117,6 +1117,12 @@
> UNSPEC_COND_FCVTNT ; Used in aarch64-sve2.md.
> UNSPEC_COND_FCVTX ; Used in aarch64-sve2.md.
> UNSPEC_COND_FCVTXNT ; Used in aarch64-sve2.md.
> + UNSPEC_FCVTZSN ; Used in aarch64-sve2.md.
> + UNSPEC_FCVTZUN ; Used in aarch64-sve2.md.
> + UNSPEC_SCVTFB ; Used in aarch64-sve2.md.
> + UNSPEC_SCVTFLT ; Used in aarch64-sve2.md.
> + UNSPEC_UCVTFB ; Used in aarch64-sve2.md.
> + UNSPEC_UCVTFLT ; Used in aarch64-sve2.md.
> UNSPEC_COND_FLOGB ; Used in aarch64-sve2.md.
> UNSPEC_DOT_FP8 ; Used in aarch64-sve2.md.
> UNSPEC_DOT_LANE_FP8 ; Used in aarch64-sve2.md.
> @@ -2262,7 +2268,7 @@
> (V8HI "4s") (V4SI "2d")])
>
> ;; SVE vector after narrowing.
> -(define_mode_attr Ventype [(VNx8HI "b")
> +(define_mode_attr Ventype [(VNx8HI "b") (VNx8HF "b")
> (VNx4SI "h") (VNx4SF "h")
> (VNx2DI "s") (VNx2DF "s")
> (VNx8SI "h") (VNx16SI "b")
> @@ -2890,6 +2896,14 @@
> (V4HF "<Vetype>[%4]") (V8HF "<Vetype>[%4]")
> ])
>
> +(define_mode_attr FCVTZN_SRC [(VNx16QI "VNx16HF")
> + (VNx8HI "VNx8SF")
> + (VNx4SI "VNx4DF")])
> +
> +(define_mode_attr CVTTB_SRC [(VNx8HF "VNx16QI")
> + (VNx4SF "VNx8HI")
> + (VNx2DF "VNx4SI")])
> +
> (define_mode_attr za16_offset_range [(VNx16QI "0_to_14_step_2")
> (VNx32QI "0_to_6_step_2")
> (VNx64QI "0_to_6_step_2")])
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_s8.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_s8.c
> new file mode 100644
> index 000000000000..2d0a9bf434f3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_s8.c
> @@ -0,0 +1,22 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
Do we need effective target checks for sme2p3 assembler support?
Ok otherwise.
Thanks,
Kyrill
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtb_untied:
> +** scvtf z0\.h, z4\.b
> +** ret
> +*/
> +TEST_DUAL_Z (cvtb_untied, svfloat16_t, svint8_t,
> + z0 = svcvtb_f16_s8 (z4),
> + z0 = svcvtb_f16 (z4))
> +
> +/*
> +** cvtb_tied:
> +** scvtf z0\.h, z0\.b
> +** ret
> +*/
> +TEST_DUAL_Z_REV (cvtb_tied, svfloat16_t, svint8_t,
> + z0_res = svcvtb_f16_s8 (z0),
> + z0_res = svcvtb_f16 (z0))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_u8.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_u8.c
> new file mode 100644
> index 000000000000..670ab5153a1d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_u8.c
> @@ -0,0 +1,22 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtb_untied:
> +** ucvtf z0\.h, z4\.b
> +** ret
> +*/
> +TEST_DUAL_Z (cvtb_untied, svfloat16_t, svuint8_t,
> + z0 = svcvtb_f16_u8 (z4),
> + z0 = svcvtb_f16 (z4))
> +
> +/*
> +** cvtb_tied:
> +** ucvtf z0\.h, z0\.b
> +** ret
> +*/
> +TEST_DUAL_Z_REV (cvtb_tied, svfloat16_t, svuint8_t,
> + z0_res = svcvtb_f16_u8 (z0),
> + z0_res = svcvtb_f16 (z0))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_s16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_s16.c
> new file mode 100644
> index 000000000000..b51880b1364c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_s16.c
> @@ -0,0 +1,22 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtb_untied:
> +** scvtf z0\.s, z4\.h
> +** ret
> +*/
> +TEST_DUAL_Z (cvtb_untied, svfloat32_t, svint16_t,
> + z0 = svcvtb_f32_s16 (z4),
> + z0 = svcvtb_f32 (z4))
> +
> +/*
> +** cvtb_tied:
> +** scvtf z0\.s, z0\.h
> +** ret
> +*/
> +TEST_DUAL_Z_REV (cvtb_tied, svfloat32_t, svint16_t,
> + z0_res = svcvtb_f32_s16 (z0),
> + z0_res = svcvtb_f32 (z0))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_u16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_u16.c
> new file mode 100644
> index 000000000000..5a16e4a62463
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_u16.c
> @@ -0,0 +1,22 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtb_untied:
> +** ucvtf z0\.s, z4\.h
> +** ret
> +*/
> +TEST_DUAL_Z (cvtb_untied, svfloat32_t, svuint16_t,
> + z0 = svcvtb_f32_u16 (z4),
> + z0 = svcvtb_f32 (z4))
> +
> +/*
> +** cvtb_tied:
> +** ucvtf z0\.s, z0\.h
> +** ret
> +*/
> +TEST_DUAL_Z_REV (cvtb_tied, svfloat32_t, svuint16_t,
> + z0_res = svcvtb_f32_u16 (z0),
> + z0_res = svcvtb_f32 (z0))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_s32.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_s32.c
> new file mode 100644
> index 000000000000..6aafc5792efa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_s32.c
> @@ -0,0 +1,22 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtb_untied:
> +** scvtf z0\.d, z4\.s
> +** ret
> +*/
> +TEST_DUAL_Z (cvtb_untied, svfloat64_t, svint32_t,
> + z0 = svcvtb_f64_s32 (z4),
> + z0 = svcvtb_f64 (z4))
> +
> +/*
> +** cvtb_tied:
> +** scvtf z0\.d, z0\.s
> +** ret
> +*/
> +TEST_DUAL_Z_REV (cvtb_tied, svfloat64_t, svint32_t,
> + z0_res = svcvtb_f64_s32 (z0),
> + z0_res = svcvtb_f64 (z0))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_u32.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_u32.c
> new file mode 100644
> index 000000000000..7ee9a2157ecf
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_u32.c
> @@ -0,0 +1,22 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtb_untied:
> +** ucvtf z0\.d, z4\.s
> +** ret
> +*/
> +TEST_DUAL_Z (cvtb_untied, svfloat64_t, svuint32_t,
> + z0 = svcvtb_f64_u32 (z4),
> + z0 = svcvtb_f64 (z4))
> +
> +/*
> +** cvtb_tied:
> +** ucvtf z0\.d, z0\.s
> +** ret
> +*/
> +TEST_DUAL_Z_REV (cvtb_tied, svfloat64_t, svuint32_t,
> + z0_res = svcvtb_f64_u32 (z0),
> + z0_res = svcvtb_f64 (z0))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s16_f32_x2.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s16_f32_x2.c
> new file mode 100644
> index 000000000000..67015f58873a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s16_f32_x2.c
> @@ -0,0 +1,51 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtn_z0_z0:
> +** fcvtzsn z0\.h, {z0\.s - z1\.s}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z0, svfloat32x2_t, svint16_t,
> + z0_res = svcvtn_s16_f32_x2 (z0),
> + z0_res = svcvtn_s16 (z0))
> +
> +/*
> +** cvtn_z0_z6:
> +** fcvtzsn z0\.h, {z6\.s - z7\.s}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z6, svfloat32x2_t, svint16_t,
> + z0_res = svcvtn_s16_f32_x2 (z6),
> + z0_res = svcvtn_s16 (z6))
> +
> +/*
> +** cvtn_z0_z29:
> +** mov [^\n]+
> +** mov [^\n]+
> +** fcvtzsn z0\.h, [^\n]+
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z29, svfloat32x2_t, svint16_t,
> + z0_res = svcvtn_s16_f32_x2 (z29),
> + z0_res = svcvtn_s16 (z29))
> +
> +/*
> +** cvtn_z5_z0:
> +** fcvtzsn z5\.h, {z0\.s - z1\.s}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z5_z0, svfloat32x2_t, svint16_t,
> + z5 = svcvtn_s16_f32_x2 (z0),
> + z5 = svcvtn_s16 (z0))
> +
> +/*
> +** cvtn_z22_z16:
> +** fcvtzsn z22\.h, {z16\.s - z17\.s}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z22_z16, svfloat32x2_t, svint16_t,
> + z22 = svcvtn_s16_f32_x2 (z16),
> + z22 = svcvtn_s16 (z16))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s32_f64_x2.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s32_f64_x2.c
> new file mode 100644
> index 000000000000..67b3d0819b8b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s32_f64_x2.c
> @@ -0,0 +1,51 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtn_z0_z0:
> +** fcvtzsn z0\.s, {z0\.d - z1\.d}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z0, svfloat64x2_t, svint32_t,
> + z0_res = svcvtn_s32_f64_x2 (z0),
> + z0_res = svcvtn_s32 (z0))
> +
> +/*
> +** cvtn_z0_z6:
> +** fcvtzsn z0\.s, {z6\.d - z7\.d}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z6, svfloat64x2_t, svint32_t,
> + z0_res = svcvtn_s32_f64_x2 (z6),
> + z0_res = svcvtn_s32 (z6))
> +
> +/*
> +** cvtn_z0_z29:
> +** mov [^\n]+
> +** mov [^\n]+
> +** fcvtzsn z0\.s, [^\n]+
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z29, svfloat64x2_t, svint32_t,
> + z0_res = svcvtn_s32_f64_x2 (z29),
> + z0_res = svcvtn_s32 (z29))
> +
> +/*
> +** cvtn_z5_z0:
> +** fcvtzsn z5\.s, {z0\.d - z1\.d}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z5_z0, svfloat64x2_t, svint32_t,
> + z5 = svcvtn_s32_f64_x2 (z0),
> + z5 = svcvtn_s32 (z0))
> +
> +/*
> +** cvtn_z22_z16:
> +** fcvtzsn z22\.s, {z16\.d - z17\.d}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z22_z16, svfloat64x2_t, svint32_t,
> + z22 = svcvtn_s32_f64_x2 (z16),
> + z22 = svcvtn_s32 (z16))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s8_f16_x2.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s8_f16_x2.c
> new file mode 100644
> index 000000000000..97e013bb0d3f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_s8_f16_x2.c
> @@ -0,0 +1,51 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtn_z0_z0:
> +** fcvtzsn z0\.b, {z0\.h - z1\.h}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z0, svfloat16x2_t, svint8_t,
> + z0_res = svcvtn_s8_f16_x2 (z0),
> + z0_res = svcvtn_s8 (z0))
> +
> +/*
> +** cvtn_z0_z6:
> +** fcvtzsn z0\.b, {z6\.h - z7\.h}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z6, svfloat16x2_t, svint8_t,
> + z0_res = svcvtn_s8_f16_x2 (z6),
> + z0_res = svcvtn_s8 (z6))
> +
> +/*
> +** cvtn_z0_z29:
> +** mov [^\n]+
> +** mov [^\n]+
> +** fcvtzsn z0\.b, [^\n]+
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z29, svfloat16x2_t, svint8_t,
> + z0_res = svcvtn_s8_f16_x2 (z29),
> + z0_res = svcvtn_s8 (z29))
> +
> +/*
> +** cvtn_z5_z0:
> +** fcvtzsn z5\.b, {z0\.h - z1\.h}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z5_z0, svfloat16x2_t, svint8_t,
> + z5 = svcvtn_s8_f16_x2 (z0),
> + z5 = svcvtn_s8 (z0))
> +
> +/*
> +** cvtn_z22_z16:
> +** fcvtzsn z22\.b, {z16\.h - z17\.h}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z22_z16, svfloat16x2_t, svint8_t,
> + z22 = svcvtn_s8_f16_x2 (z16),
> + z22 = svcvtn_s8 (z16))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u16_f32_x2.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u16_f32_x2.c
> new file mode 100644
> index 000000000000..1da513781b13
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u16_f32_x2.c
> @@ -0,0 +1,51 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtn_z0_z0:
> +** fcvtzun z0\.h, {z0\.s - z1\.s}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z0, svfloat32x2_t, svuint16_t,
> + z0_res = svcvtn_u16_f32_x2 (z0),
> + z0_res = svcvtn_u16 (z0))
> +
> +/*
> +** cvtn_z0_z6:
> +** fcvtzun z0\.h, {z6\.s - z7\.s}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z6, svfloat32x2_t, svuint16_t,
> + z0_res = svcvtn_u16_f32_x2 (z6),
> + z0_res = svcvtn_u16 (z6))
> +
> +/*
> +** cvtn_z0_z29:
> +** mov [^\n]+
> +** mov [^\n]+
> +** fcvtzun z0\.h, [^\n]+
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z29, svfloat32x2_t, svuint16_t,
> + z0_res = svcvtn_u16_f32_x2 (z29),
> + z0_res = svcvtn_u16 (z29))
> +
> +/*
> +** cvtn_z5_z0:
> +** fcvtzun z5\.h, {z0\.s - z1\.s}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z5_z0, svfloat32x2_t, svuint16_t,
> + z5 = svcvtn_u16_f32_x2 (z0),
> + z5 = svcvtn_u16 (z0))
> +
> +/*
> +** cvtn_z22_z16:
> +** fcvtzun z22\.h, {z16\.s - z17\.s}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z22_z16, svfloat32x2_t, svuint16_t,
> + z22 = svcvtn_u16_f32_x2 (z16),
> + z22 = svcvtn_u16 (z16))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u32_f64_x2.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u32_f64_x2.c
> new file mode 100644
> index 000000000000..051820c74e26
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u32_f64_x2.c
> @@ -0,0 +1,51 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtn_z0_z0:
> +** fcvtzun z0\.s, {z0\.d - z1\.d}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z0, svfloat64x2_t, svuint32_t,
> + z0_res = svcvtn_u32_f64_x2 (z0),
> + z0_res = svcvtn_u32 (z0))
> +
> +/*
> +** cvtn_z0_z6:
> +** fcvtzun z0\.s, {z6\.d - z7\.d}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z6, svfloat64x2_t, svuint32_t,
> + z0_res = svcvtn_u32_f64_x2 (z6),
> + z0_res = svcvtn_u32 (z6))
> +
> +/*
> +** cvtn_z0_z29:
> +** mov [^\n]+
> +** mov [^\n]+
> +** fcvtzun z0\.s, [^\n]+
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z29, svfloat64x2_t, svuint32_t,
> + z0_res = svcvtn_u32_f64_x2 (z29),
> + z0_res = svcvtn_u32 (z29))
> +
> +/*
> +** cvtn_z5_z0:
> +** fcvtzun z5\.s, {z0\.d - z1\.d}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z5_z0, svfloat64x2_t, svuint32_t,
> + z5 = svcvtn_u32_f64_x2 (z0),
> + z5 = svcvtn_u32 (z0))
> +
> +/*
> +** cvtn_z22_z16:
> +** fcvtzun z22\.s, {z16\.d - z17\.d}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z22_z16, svfloat64x2_t, svuint32_t,
> + z22 = svcvtn_u32_f64_x2 (z16),
> + z22 = svcvtn_u32 (z16))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u8_f16_x2.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u8_f16_x2.c
> new file mode 100644
> index 000000000000..4a95ec6ee76c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_u8_f16_x2.c
> @@ -0,0 +1,51 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtn_z0_z0:
> +** fcvtzun z0\.b, {z0\.h - z1\.h}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z0, svfloat16x2_t, svuint8_t,
> + z0_res = svcvtn_u8_f16_x2 (z0),
> + z0_res = svcvtn_u8 (z0))
> +
> +/*
> +** cvtn_z0_z6:
> +** fcvtzun z0\.b, {z6\.h - z7\.h}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z6, svfloat16x2_t, svuint8_t,
> + z0_res = svcvtn_u8_f16_x2 (z6),
> + z0_res = svcvtn_u8 (z6))
> +
> +/*
> +** cvtn_z0_z29:
> +** mov [^\n]+
> +** mov [^\n]+
> +** fcvtzun z0\.b, [^\n]+
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z0_z29, svfloat16x2_t, svuint8_t,
> + z0_res = svcvtn_u8_f16_x2 (z29),
> + z0_res = svcvtn_u8 (z29))
> +
> +/*
> +** cvtn_z5_z0:
> +** fcvtzun z5\.b, {z0\.h - z1\.h}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z5_z0, svfloat16x2_t, svuint8_t,
> + z5 = svcvtn_u8_f16_x2 (z0),
> + z5 = svcvtn_u8 (z0))
> +
> +/*
> +** cvtn_z22_z16:
> +** fcvtzun z22\.b, {z16\.h - z17\.h}
> +** ret
> +*/
> +TEST_X2_NARROW (cvtn_z22_z16, svfloat16x2_t, svuint8_t,
> + z22 = svcvtn_u8_f16_x2 (z16),
> + z22 = svcvtn_u8 (z16))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_s8.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_s8.c
> new file mode 100644
> index 000000000000..4352e484bf00
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_s8.c
> @@ -0,0 +1,22 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtt_untied:
> +** scvtflt z0\.h, z4\.b
> +** ret
> +*/
> +TEST_DUAL_Z (cvtt_untied, svfloat16_t, svint8_t,
> + z0 = svcvtt_f16_s8 (z4),
> + z0 = svcvtt_f16 (z4))
> +
> +/*
> +** cvtt_tied:
> +** scvtflt z0\.h, z0\.b
> +** ret
> +*/
> +TEST_DUAL_Z_REV (cvtt_tied, svfloat16_t, svint8_t,
> + z0_res = svcvtt_f16_s8 (z0),
> + z0_res = svcvtt_f16 (z0))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_u8.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_u8.c
> new file mode 100644
> index 000000000000..546a8c432d55
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_u8.c
> @@ -0,0 +1,22 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtt_untied:
> +** ucvtflt z0\.h, z4\.b
> +** ret
> +*/
> +TEST_DUAL_Z (cvtt_untied, svfloat16_t, svuint8_t,
> + z0 = svcvtt_f16_u8 (z4),
> + z0 = svcvtt_f16 (z4))
> +
> +/*
> +** cvtt_tied:
> +** ucvtflt z0\.h, z0\.b
> +** ret
> +*/
> +TEST_DUAL_Z_REV (cvtt_tied, svfloat16_t, svuint8_t,
> + z0_res = svcvtt_f16_u8 (z0),
> + z0_res = svcvtt_f16 (z0))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_s16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_s16.c
> new file mode 100644
> index 000000000000..c1b856af0fda
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_s16.c
> @@ -0,0 +1,22 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtt_untied:
> +** scvtflt z0\.s, z4\.h
> +** ret
> +*/
> +TEST_DUAL_Z (cvtt_untied, svfloat32_t, svint16_t,
> + z0 = svcvtt_f32_s16 (z4),
> + z0 = svcvtt_f32 (z4))
> +
> +/*
> +** cvtt_tied:
> +** scvtflt z0\.s, z0\.h
> +** ret
> +*/
> +TEST_DUAL_Z_REV (cvtt_tied, svfloat32_t, svint16_t,
> + z0_res = svcvtt_f32_s16 (z0),
> + z0_res = svcvtt_f32 (z0))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_u16.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_u16.c
> new file mode 100644
> index 000000000000..7701d97eb4ff
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_u16.c
> @@ -0,0 +1,22 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtt_untied:
> +** ucvtflt z0\.s, z4\.h
> +** ret
> +*/
> +TEST_DUAL_Z (cvtt_untied, svfloat32_t, svuint16_t,
> + z0 = svcvtt_f32_u16 (z4),
> + z0 = svcvtt_f32 (z4))
> +
> +/*
> +** cvtt_tied:
> +** ucvtflt z0\.s, z0\.h
> +** ret
> +*/
> +TEST_DUAL_Z_REV (cvtt_tied, svfloat32_t, svuint16_t,
> + z0_res = svcvtt_f32_u16 (z0),
> + z0_res = svcvtt_f32 (z0))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_s32.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_s32.c
> new file mode 100644
> index 000000000000..e18734d0c8b6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_s32.c
> @@ -0,0 +1,22 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtt_untied:
> +** scvtflt z0\.d, z4\.s
> +** ret
> +*/
> +TEST_DUAL_Z (cvtt_untied, svfloat64_t, svint32_t,
> + z0 = svcvtt_f64_s32 (z4),
> + z0 = svcvtt_f64 (z4))
> +
> +/*
> +** cvtt_tied:
> +** scvtflt z0\.d, z0\.s
> +** ret
> +*/
> +TEST_DUAL_Z_REV (cvtt_tied, svfloat64_t, svint32_t,
> + z0_res = svcvtt_f64_s32 (z0),
> + z0_res = svcvtt_f64 (z0))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_u32.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_u32.c
> new file mode 100644
> index 000000000000..b0078952ed5d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_u32.c
> @@ -0,0 +1,22 @@
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** cvtt_untied:
> +** ucvtflt z0\.d, z4\.s
> +** ret
> +*/
> +TEST_DUAL_Z (cvtt_untied, svfloat64_t, svuint32_t,
> + z0 = svcvtt_f64_u32 (z4),
> + z0 = svcvtt_f64 (z4))
> +
> +/*
> +** cvtt_tied:
> +** ucvtflt z0\.d, z0\.s
> +** ret
> +*/
> +TEST_DUAL_Z_REV (cvtt_tied, svfloat64_t, svuint32_t,
> + z0_res = svcvtt_f64_u32 (z0),
> + z0_res = svcvtt_f64 (z0))
> --
> 2.54.0
>
