On Tue, Jul 21, 2026 at 06:44:17AM +0800, H.J. Lu wrote:
> --- a/gcc/config/i386/sync.md
> +++ b/gcc/config/i386/sync.md
> @@ -388,6 +388,55 @@ (define_insn "storedi_via_sse"
> [(set_attr "type" "ssemov")
> (set_attr "mode" "DI")])
>
> +(define_expand "atomic_loadti"
> + [(set (match_operand:TI 0 "nonimmediate_operand")
> + (unspec:TI [(match_operand:TI 1 "memory_operand")
> + (match_operand:SI 2 "const_int_operand")]
> + UNSPEC_LDA))]
> + "TARGET_64BIT && TARGET_SSE2 && ix86_128bit_atomic"
Shouldn't these all use TARGET_AVX instead of TARGET_SSE2, so that
a VEX or EVEX encoded insn is used, because the guarantees cover only
AVX capable CPUs?
Jakub
