This is a summary of discussions relative to the merge request created by
Torbjörn Svensson (azoff) <[email protected]> titled
testsuite: require cortex-a53 in reg_equal_test.c test
since its creation.
Description: Changes since v1:
- Removed `dg-additional-options "-mpure-code" { target arm_cortex_m }`
- Removed `dg-skip-if "" { ! { arm_thumb2_ok || arm_thumb1_movt_ok } }`
- Added `dg-require-effective-target arm_cpu_cortex_a53_ok`
- Added `dg-add-options arm_cpu_cortex_a53`
Ok for trunk, releases/gcc-16 and releases/gcc-15?
--
gcc/testsuite/ChangeLog:
* gcc.target/arm/reg_equal_test.c: Add require effective target
cortex-a53 for test.
Signed-off-by: Torbjörn SVENSSON <[email protected]>
--
CC: [email protected]
The full and up to date discussion can be found at
https://forge.sourceware.org/gcc/gcc/pulls/198
The merge request has been closed without being merged directly on the forge
repository.
On 2026-07-21 09:48:27+00:00, Richard Earnshaw (rearnsha) wrote:
commit 62082d278d suggests that this is expected to work as is for any target
that has movw/movt. So has this regressed at some point? Or are there some
CPU/arch options that are still causing this to fail. I wonder if this is a
costing issue somewhere, but I'm missing the details of which targets are
causing problems.
On 2026-07-21 12:22:39+00:00, Torbjörn Svensson (azoff) wrote:
@rearnsha wrote in
https://forge.sourceware.org/gcc/gcc/pulls/198#issuecomment-6816:
> commit [`62082d278d`](/gcc/gcc/commit/62082d278d) suggests that this is
> expected to work as is for any target that has movw/movt. So has this
> regressed at some point? Or are there some CPU/arch options that are still
> causing this to fail. I wonder if this is a costing issue somewhere, but I'm
> missing the details of which targets are causing problems.
I don't think it ever worked across all targets. When you did that change, I
think it only worked for Cortex-A.
Below are the different target flags that I use and the resulting RTL.
I copied the content from
https://gcc.gnu.org/pipermail/gcc-patches/2026-April/711963.html, so the RTL
might be different with HEAD compared to r16-8253-geb50d28a9353e9 that was used
to produce these.
thumb/arch=armv7ve+nofp/tune=cortex-a7/float-abi=soft/fpu=auto
```
;; Function x (x, funcdef_no=0, decl_uid=4706, cgraph_uid=1, symbol_order=0)
;; Generating RTL for gimple basic block 2
try_optimize_cfg iteration 1
Merging block 3 into block 2...
Merged blocks 2 and 3.
Merged 2 and 3 without moving.
Merging block 4 into block 2...
Merged blocks 2 and 4.
Merged 2 and 4 without moving.
try_optimize_cfg iteration 2
;;
;; Full RTL generated for this function:
;;
(note 1 0 3 NOTE_INSN_DELETED)
(note 3 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note 2 3 5 2 NOTE_INSN_FUNCTION_BEG)
(insn 5 2 6 2 (set (reg/v:SI 94 [ d ])
(const_int 19294 [0x4b5e])) -1
(nil))
(insn 6 5 0 2 (set (zero_extract:SI (reg/v:SI 94 [ d ])
(const_int 16 [0x10])
(const_int 16 [0x10]))
(const_int 51154 [0xc7d2])) -1
(expr_list:REG_EQUAL (const_int -942519458 [0xffffffffc7d24b5e])
(nil)))
```
---
thumb/arch=armv7ve+neon/tune=cortex-a7/float-abi=hard/fpu=auto
```
;; Function x (x, funcdef_no=0, decl_uid=7770, cgraph_uid=1, symbol_order=0)
;; Generating RTL for gimple basic block 2
try_optimize_cfg iteration 1
Merging block 3 into block 2...
Merged blocks 2 and 3.
Merged 2 and 3 without moving.
Merging block 4 into block 2...
Merged blocks 2 and 4.
Merged 2 and 4 without moving.
try_optimize_cfg iteration 2
;;
;; Full RTL generated for this function:
;;
(note 1 0 3 NOTE_INSN_DELETED)
(note 3 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note 2 3 5 2 NOTE_INSN_FUNCTION_BEG)
(insn 5 2 6 2 (set (reg/v:SI 94 [ d ])
(const_int 19294 [0x4b5e])) -1
(nil))
(insn 6 5 0 2 (set (zero_extract:SI (reg/v:SI 94 [ d ])
(const_int 16 [0x10])
(const_int 16 [0x10]))
(const_int 51154 [0xc7d2])) -1
(expr_list:REG_EQUAL (const_int -942519458 [0xffffffffc7d24b5e])
(nil)))
```
---
thumb/arch=armv7e-m+fp/tune=cortex-m4/float-abi=hard/fpu=auto
thumb/arch=armv7e-m+fp.dp/tune=cortex-m7/float-abi=hard/fpu=auto
thumb/arch=armv8-m.main+dsp+fp/tune=cortex-m33/float-abi=hard/fpu=auto
```
;; Function x (x, funcdef_no=0, decl_uid=7770, cgraph_uid=1, symbol_order=0)
;; Generating RTL for gimple basic block 2
try_optimize_cfg iteration 1
Merging block 3 into block 2...
Merged blocks 2 and 3.
Merged 2 and 3 without moving.
Merging block 4 into block 2...
Merged blocks 2 and 4.
Merged 2 and 4 without moving.
try_optimize_cfg iteration 2
;;
;; Full RTL generated for this function:
;;
(note 1 0 3 NOTE_INSN_DELETED)
(note 3 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note 2 3 5 2 NOTE_INSN_FUNCTION_BEG)
(insn 5 2 0 2 (set (reg/v:SI 94 [ d ])
(const_int -942519458 [0xffffffffc7d24b5e])) -1
(nil))
```
---
thumb/arch=armv6s-m/tune=cortex-m0/float-abi=soft/fpu=auto (unsupported by { !
{ arm_thumb2_ok || arm_thumb1_movt_ok } }, but included anyway for completeness)
```
thumb/arch=armv7-m/tune=cortex-m3/float-abi=soft/fpu=auto
thumb/arch=armv7e-m+nofp/tune=cortex-m4/float-abi=soft/fpu=auto
thumb/arch=armv7e-m+nofp/tune=cortex-m7/float-abi=soft/fpu=auto
thumb/arch=armv8-m.main+dsp+nofp/tune=cortex-m33/float-abi=soft/fpu=auto
thumb/arch=armv8.1-m.main+mve+nofp/tune=cortex-m55/float-abi=soft/fpu=auto
thumb/arch=armv8.1-m.main+mve+pacbti+nofp/tune=cortex-m85/float-abi=soft/fpu=auto
;; Function x (x, funcdef_no=0, decl_uid=4706, cgraph_uid=1, symbol_order=0)
;; Generating RTL for gimple basic block 2
try_optimize_cfg iteration 1
Merging block 3 into block 2...
Merged blocks 2 and 3.
Merged 2 and 3 without moving.
Merging block 4 into block 2...
Merged blocks 2 and 4.
Merged 2 and 4 without moving.
try_optimize_cfg iteration 2
;;
;; Full RTL generated for this function:
;;
(note 1 0 3 NOTE_INSN_DELETED)
(note 3 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note 2 3 5 2 NOTE_INSN_FUNCTION_BEG)
(insn 5 2 0 2 (set (reg/v:SI 94 [ d ])
(const_int -942519458 [0xffffffffc7d24b5e])) -1
(nil))
```
---
thumb/arch=armv8.1-m.main+mve.fp+fp.dp/tune=cortex-m55/float-abi=hard/fpu=auto
thumb/arch=armv8.1-m.main+mve.fp+pacbti+fp.dp/tune=cortex-m85/float-abi=hard/fpu=auto
```
;; Function x (x, funcdef_no=0, decl_uid=7944, cgraph_uid=1, symbol_order=0)
;; Generating RTL for gimple basic block 2
try_optimize_cfg iteration 1
Merging block 3 into block 2...
Merged blocks 2 and 3.
Merged 2 and 3 without moving.
Merging block 4 into block 2...
Merged blocks 2 and 4.
Merged 2 and 4 without moving.
try_optimize_cfg iteration 2
;;
;; Full RTL generated for this function:
;;
(note 1 0 3 NOTE_INSN_DELETED)
(note 3 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note 2 3 5 2 NOTE_INSN_FUNCTION_BEG)
(insn 5 2 0 2 (set (reg/v:SI 94 [ d ])
(const_int -942519458 [0xffffffffc7d24b5e])) -1
(nil))
```
On 2026-07-21 15:15:40+00:00, Richard Earnshaw (rearnsha) wrote:
Digging into this case I see
```
if (TARGET_USE_MOVT)
arm_emit_movpair (target, GEN_INT (val));
else
emit_set_insn (target, GEN_INT (val));
```
at the point where we decide whether or not to use MOVW/MOVT. But
`TARGET_USE_MOVT` is dependent on the CPU tuning property
`prefer_constant_pool`, which is dependent on the CPU tuning tables. However,
this is ignored when literal pools are disabled.
So while your patch will address the problem for m-profile devices, it doesn't
really solve the problem everywhere in a reliable manner.
Looking back at the history of this test, I see it was originally added to
check that _when_ we emit a mov-pair sequence we emit a note on the sequence
with the REG_EQUAL of the final value.
I don't think it really matters that we test this for every CPU that supports
mov-pair; we just want to assert the above property. So I'm now thinking we
should change the test to force the pre-conditions to be true by requiring a
CPU that has these properties and then applying the options needed to achieve
this. A suitable cpu target would be cortex-a53, for which we already have
support in target-supports.exp.
On 2026-07-21 15:20:39+00:00, Richard Earnshaw (rearnsha) wrote:
Note that if we require cortex-a53 we can then remove the skip-if rule, making
the test more widely applicable. So there are additional advantages to this
approach.
On 2026-07-22 09:28:57+00:00, Richard Earnshaw (rearnsha) <[email protected]>
approved the changes:
Please make sure the commit message contains a brief summary of why this is
considered to be the right change (see my analysis yesterday).
OK otherwise.
On 2026-07-22 10:26:48+00:00, Torbjörn Svensson (azoff) wrote:
Pushed as r17-2614-g8d16b075796e77, r16-9368-gaea86c8697b968 and
r15-11408-g26bb36f81b68ef with an updated commit message.
