[PATCH v1 4/4] RISC-V: Add one more test case for vwsub.wv

[pan2 . li]

From: Pan Li <pan2...@intel.com>

For csrr not asm check when enable overlap enabled.

gcc/testsuite/ChangeLog:

        * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-15.c: New test.

Signed-off-by: Pan Li <pan2...@intel.com>
---
 .../costmodel/riscv/rvv/dynamic-lmul8-15.c    | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-15.c

diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-15.c 
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-15.c
new file mode 100644
index 00000000000..dfaca768ba9
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-15.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize 
-mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
+
+#include <stdint-gcc.h>
+
+void foo2 (int64_t *__restrict a,
+          int32_t *__restrict b,
+          int32_t *__restrict c,
+          int32_t *__restrict a2,
+          int32_t *__restrict b2,
+          int32_t *__restrict c2,
+          int32_t *__restrict a3,
+          int32_t *__restrict b3,
+          int32_t *__restrict c3,
+          int32_t *__restrict a4,
+          int32_t *__restrict b4,
+          int32_t *__restrict c4,
+          int64_t *__restrict a5,
+          int32_t *__restrict b5,
+          int32_t *__restrict c5,
+          int n)
+{
+    for (int i = 0; i < n; i++){
+      a[i] = b[i] - c[i];
+      b5[i] = b[i] - c[i];
+      a2[i] = b2[i] - c2[i];
+      a3[i] = b3[i] - c3[i];
+      a4[i] = b4[i] - c4[i];
+      a5[i] = a[i] - a4[i];
+      a[i] = a5[i] - b5[i] - a[i];
+
+      a[i] = a[i] - c[i];
+      b5[i] = a[i] - c[i];
+      a2[i] = a[i] - c2[i];
+      a3[i] = a[i] - c3[i];
+      a4[i] = a[i] - c4[i];
+      a5[i] = a[i] - a4[i];
+      a[i] = a[i] - b5[i] - a[i];
+    }
+}
+
+/* { dg-final { scan-assembler {e64,m8} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "Preferring smaller LMUL loop because it 
has unexpected spills" "vect" } } */
+/* { dg-final { scan-tree-dump-times "Maximum lmul = 8" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Maximum lmul = 4" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Maximum lmul = 2" 1 "vect" } } */
-- 
2.43.0