> From: Dipesh Sharma <[email protected]>
> Sent: Monday, July 27, 2026 5:38 PM
>
LGTM with two minor issues in patterns.
> diff --git a/gcc/config/i386/avx10v2auxintrin.h
> b/gcc/config/i386/avx10v2auxintrin.h
> index a862f3173eb..05e9d90ec37 100644
> --- a/gcc/config/i386/avx10v2auxintrin.h
> +++ b/gcc/config/i386/avx10v2auxintrin.h
> @@ -1195,6 +1195,145 @@ _mm512_maskz_cvthf8_ps (__mmask16 __U,
> __m128i __A)
> (__mmask16) __U);
> }
>
> +// VCVTBF82BF4S
> +
> +extern __inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cvts_bf8_bf4 (__m128i __A)
> +{
> + return (__m128i) __builtin_ia32_vcvtbf82bf4s128 ((__v16qi) __A);
> +}
> +
> +extern __inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_cvts_bf8_bf4 (__m256i __A)
> +{
> + return (__m128i) __builtin_ia32_vcvtbf82bf4s256 ((__v32qi) __A);
> +}
> +
> +extern __inline __m256i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_cvts_bf8_bf4 (__m512i __A)
> +{
> + return (__m256i) __builtin_ia32_vcvtbf82bf4s512 ((__v64qi) __A);
> +}
> +
> +// VCVTHF82BF4S
> +
> +extern __inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cvts_hf8_bf4 (__m128i __A)
> +{
> + return (__m128i) __builtin_ia32_vcvthf82bf4s128 ((__v16qi) __A);
> +}
> +
> +extern __inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_cvts_hf8_bf4 (__m256i __A)
> +{
> + return (__m128i) __builtin_ia32_vcvthf82bf4s256 ((__v32qi) __A);
> +}
> +
> +extern __inline __m256i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_cvts_hf8_bf4 (__m512i __A)
> +{
> + return (__m256i) __builtin_ia32_vcvthf82bf4s512 ((__v64qi) __A);
> +}
> +
> +// VCVTBF42HF8 - 128-bit
> +
> +extern __inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_cvtbf4_hf8 (__m128i __A)
> +{
> + return (__m128i) __builtin_ia32_vcvtbf42hf8128_mask ((__v16qi) __A,
> + (__v16qi)
> + _mm_undefined_si128 (),
> + (__mmask16) -1);
> +}
> +
> +extern __inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_mask_cvtbf4_hf8 (__m128i __W, __mmask16 __U, __m128i __A)
> +{
> + return (__m128i) __builtin_ia32_vcvtbf42hf8128_mask ((__v16qi) __A,
> + (__v16qi) __W,
> + (__mmask16) __U);
> +}
> +
> +extern __inline __m128i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_maskz_cvtbf4_hf8 (__mmask16 __U, __m128i __A)
> +{
> + return (__m128i) __builtin_ia32_vcvtbf42hf8128_mask ((__v16qi) __A,
> + (__v16qi)
> + _mm_setzero_si128 (),
> + (__mmask16) __U);
> +}
> +
> +// VCVTBF42HF8 - 256-bit
> +
> +extern __inline __m256i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_cvtbf4_hf8 (__m128i __A)
> +{
> + return (__m256i) __builtin_ia32_vcvtbf42hf8256_mask ((__v16qi) __A,
> + (__v32qi)
> +
> _mm256_undefined_si256 (),
> + (__mmask32) -1);
> +}
> +
> +extern __inline __m256i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_mask_cvtbf4_hf8 (__m256i __W, __mmask32 __U, __m128i __A)
> +{
> + return (__m256i) __builtin_ia32_vcvtbf42hf8256_mask ((__v16qi) __A,
> + (__v32qi) __W,
> + (__mmask32) __U);
> +}
> +
> +extern __inline __m256i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_maskz_cvtbf4_hf8 (__mmask32 __U, __m128i __A)
> +{
> + return (__m256i) __builtin_ia32_vcvtbf42hf8256_mask ((__v16qi) __A,
> + (__v32qi)
> + _mm256_setzero_si256
> (),
> + (__mmask32) __U);
> +}
> +
> +// VCVTBF42HF8 - 512-bit
> +
> +extern __inline __m512i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_cvtbf4_hf8 (__m256i __A)
> +{
> + return (__m512i) __builtin_ia32_vcvtbf42hf8512_mask ((__v32qi) __A,
> + (__v64qi)
> +
> _mm512_undefined_si512 (),
> + (__mmask64) -1);
> +}
> +
> +extern __inline __m512i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_mask_cvtbf4_hf8 (__m512i __W, __mmask64 __U, __m256i __A)
> +{
> + return (__m512i) __builtin_ia32_vcvtbf42hf8512_mask ((__v32qi) __A,
> + (__v64qi) __W,
> + (__mmask64) __U);
> +}
> +
> +extern __inline __m512i
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_maskz_cvtbf4_hf8 (__mmask64 __U, __m256i __A)
> +{
> + return (__m512i) __builtin_ia32_vcvtbf42hf8512_mask ((__v32qi) __A,
> + (__v64qi)
> + _mm512_setzero_si512
> (),
> + (__mmask64) __U);
> +}
> +
> #ifdef __DISABLE_AVX10V2AUX__
> #undef __DISABLE_AVX10V2AUX__
> #pragma GCC pop_options
> diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-
> builtin-types.def
> index 20078ba295e..ade9b3a67e2 100644
> --- a/gcc/config/i386/i386-builtin-types.def
> +++ b/gcc/config/i386/i386-builtin-types.def
> @@ -1484,6 +1484,10 @@ DEF_FUNCTION_TYPE (V16QI, V16SI, V16SF,
> V16QI, UHI)
> DEF_FUNCTION_TYPE (V4SF, V16QI, V4SF, UQI)
> DEF_FUNCTION_TYPE (V8SF, V16QI, V8SF, UQI)
> DEF_FUNCTION_TYPE (V16SF, V16QI, V16SF, UHI)
> +DEF_FUNCTION_TYPE (V16QI, V32QI)
> +DEF_FUNCTION_TYPE (V32QI, V64QI)
> +DEF_FUNCTION_TYPE (V64QI, V32QI, V64QI, UDI)
> +
>
> # SM4 builtins
> DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI)
> diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-
> builtin.def
> index 07a80e28598..900f9ff9503 100644
> --- a/gcc/config/i386/i386-builtin.def
> +++ b/gcc/config/i386/i386-builtin.def
> @@ -3406,6 +3406,15 @@ BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
> CODE_FOR_vcvtbf82psv16sf_mask, "__builtin
> BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
> CODE_FOR_vcvthf82psv4sf_mask, "__builtin_ia32_vcvthf82ps128_mask",
> IX86_BUILTIN_VCVTHF82PS128_MASK, UNKNOWN, (int)
> V4SF_FTYPE_V16QI_V4SF_UQI)
> BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
> CODE_FOR_vcvthf82psv8sf_mask, "__builtin_ia32_vcvthf82ps256_mask",
> IX86_BUILTIN_VCVTHF82PS256_MASK, UNKNOWN, (int)
> V8SF_FTYPE_V16QI_V8SF_UQI)
> BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
> CODE_FOR_vcvthf82psv16sf_mask, "__builtin_ia32_vcvthf82ps512_mask",
> IX86_BUILTIN_VCVTHF82PS512_MASK, UNKNOWN, (int)
> V16SF_FTYPE_V16QI_V16SF_UHI)
> +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
> CODE_FOR_vcvtbf82bf4sv16qi, "__builtin_ia32_vcvtbf82bf4s128",
> IX86_BUILTIN_VCVTBF82BF4S128, UNKNOWN, (int) V16QI_FTYPE_V16QI)
> +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
> CODE_FOR_vcvtbf82bf4sv32qi, "__builtin_ia32_vcvtbf82bf4s256",
> IX86_BUILTIN_VCVTBF82BF4S256, UNKNOWN, (int) V16QI_FTYPE_V32QI)
> +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
> CODE_FOR_vcvtbf82bf4sv64qi, "__builtin_ia32_vcvtbf82bf4s512",
> IX86_BUILTIN_VCVTBF82BF4S512, UNKNOWN, (int) V32QI_FTYPE_V64QI)
> +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
> CODE_FOR_vcvthf82bf4sv16qi, "__builtin_ia32_vcvthf82bf4s128",
> IX86_BUILTIN_VCVTHF82BF4S128, UNKNOWN, (int) V16QI_FTYPE_V16QI)
> +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
> CODE_FOR_vcvthf82bf4sv32qi, "__builtin_ia32_vcvthf82bf4s256",
> IX86_BUILTIN_VCVTHF82BF4S256, UNKNOWN, (int) V16QI_FTYPE_V32QI)
> +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
> CODE_FOR_vcvthf82bf4sv64qi, "__builtin_ia32_vcvthf82bf4s512",
> IX86_BUILTIN_VCVTHF82BF4S512, UNKNOWN, (int) V32QI_FTYPE_V64QI)
> +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
> CODE_FOR_vcvtbf42hf8v16qi_mask,
> "__builtin_ia32_vcvtbf42hf8128_mask",
> IX86_BUILTIN_VCVTBF42HF8128_MASK, UNKNOWN, (int)
> V16QI_FTYPE_V16QI_V16QI_UHI)
> +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
> CODE_FOR_vcvtbf42hf8v32qi_mask,
> "__builtin_ia32_vcvtbf42hf8256_mask",
> IX86_BUILTIN_VCVTBF42HF8256_MASK, UNKNOWN, (int)
> V32QI_FTYPE_V16QI_V32QI_USI)
> +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
> CODE_FOR_vcvtbf42hf8v64qi_mask,
> "__builtin_ia32_vcvtbf42hf8512_mask",
> IX86_BUILTIN_VCVTBF42HF8512_MASK, UNKNOWN, (int)
> V64QI_FTYPE_V32QI_V64QI_UDI)
>
> /* Builtins with rounding support. */
> BDESC_END (ARGS, ROUND_ARGS)
> diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
> index 787d7e11c2f..b82a4913b4e 100644
> --- a/gcc/config/i386/i386-expand.cc
> +++ b/gcc/config/i386/i386-expand.cc
> @@ -12684,6 +12684,8 @@ ix86_expand_args_builtin (const struct
> builtin_description *d,
> case V16BF_FTYPE_V16SF:
> case V8BF_FTYPE_V8SF:
> case V8BF_FTYPE_V4SF:
> + case V16QI_FTYPE_V32QI:
> + case V32QI_FTYPE_V64QI:
> nargs = 1;
> break;
> case V4SF_FTYPE_V4SF_VEC_MERGE:
> @@ -13064,6 +13066,7 @@ ix86_expand_args_builtin (const struct
> builtin_description *d,
> case V4SF_FTYPE_V16QI_V4SF_UQI:
> case V8SF_FTYPE_V16QI_V8SF_UQI:
> case V16SF_FTYPE_V16QI_V16SF_UHI:
> + case V64QI_FTYPE_V32QI_V64QI_UDI:
> nargs = 3;
> break;
> case V32QI_FTYPE_V32QI_V32QI_INT:
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 4719ce191f0..ab9711b89e7 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -272,6 +272,9 @@
> UNSPEC_VCVTBIASPS2HF8S
> UNSPEC_VCVTBF82PS
> UNSPEC_VCVTHF82PS
> + UNSPEC_VCVTBF82BF4S
> + UNSPEC_VCVTHF82BF4S
> + UNSPEC_VCVTBF42HF8
> ])
>
> (define_c_enum "unspecv" [
> @@ -34541,3 +34544,61 @@
> [(set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
>
> +;; FP8 to FP4 converts (VCVTBF82BF4S, VCVTHF82BF4S) - no masking
> +
> +(define_int_iterator UNSPEC_CONVERTFP82BF4S
> + [UNSPEC_VCVTBF82BF4S UNSPEC_VCVTHF82BF4S])
> +
> +(define_int_attr convertfp82bf4s
> + [(UNSPEC_VCVTBF82BF4S "bf82bf4s")
> + (UNSPEC_VCVTHF82BF4S "hf82bf4s")])
> +
> +(define_expand "vcvt<convertfp82bf4s>v16qi"
> + [(set (match_operand:V16QI 0 "register_operand")
It should be nonimmediate_operand ...
> + (vec_concat:V16QI
> + (unspec:V8QI
> + [(match_operand:V16QI 1 "register_operand")]
> + UNSPEC_CONVERTFP82BF4S)
> + (match_dup 2)))]
> + "TARGET_AVX10V2AUX"
> + "operands[2] = CONST0_RTX (V8QImode);")
> +
> +(define_insn "*vcvt<convertfp82bf4s>v16qi"
> + [(set (match_operand:V16QI 0 "register_operand" "=v")
... and also with =vm here to address memory. Similar for
upcoming pattern.
> + (vec_concat:V16QI
> + (unspec:V8QI
> + [(match_operand:V16QI 1 "register_operand" "v")]
> + UNSPEC_CONVERTFP82BF4S)
> + (match_operand:V8QI 2 "const0_operand")))]
> + "TARGET_AVX10V2AUX"
> + "vcvt<convertfp82bf4s>\t{%1, %0|%0, %1}"
> + [(set_attr "prefix" "evex")
> + (set_attr "mode" "TI")])
> +
> +(define_insn "vcvt<convertfp82bf4s><mode>"
> + [(set (match_operand:<ssehalfvecmode> 0 "register_operand" "=v")
> + (unspec:<ssehalfvecmode>
> + [(match_operand:VI1_AVX512_3264 1 "register_operand" "v")]
> + UNSPEC_CONVERTFP82BF4S))]
> + "TARGET_AVX10V2AUX"
> + "vcvt<convertfp82bf4s>\t{%1, %0|%0, %1}"
> + [(set_attr "prefix" "evex")
> + (set_attr "mode" "<sseinsnmode>")])
> +
> +;; FP4 to FP8 converts (VCVTBF42HF8) with masking
> +
> +(define_mode_attr ssebvecmode_3
> + [(V16QI "V16QI") (V32QI "V16QI") (V64QI "V32QI")])
> +
> +(define_mode_attr iptrssebvec_4
> + [(V16QI "q") (V32QI "") (V64QI "")])
> +
> +(define_insn "vcvtbf42hf8<mode><mask_name>"
> + [(set (match_operand:VI1_AVX512VL 0 "register_operand" "=v")
> + (unspec:VI1_AVX512VL
> + [(match_operand:<ssebvecmode_3> 1 "nonimmediate_operand"
Maybe we could combine it with ssebvecmode_2 since they are the size
to size relation is similar.
Thx,
Haochen
> "vm")]
> + UNSPEC_VCVTBF42HF8))]
> + "TARGET_AVX10V2AUX"
> +
> "vcvtbf42hf8\t{%1, %0<mask_operand2>|%0<mask_operand2>, %<iptrsseb
> vec_4>1}"
> + [(set_attr "prefix" "evex")
> + (set_attr "mode" "<sseinsnmode>")])
> diff --git a/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1e.c
> b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1e.c
> new file mode 100644
> index 00000000000..cddd046e030
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1e.c
> @@ -0,0 +1,30 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx10v2aux -O2 -fno-fuse-ops-with-volatile-access" } */
> +/* { dg-final { scan-assembler-times "vcvtbf82bf4s\[ \\t\]*%xmm\[0-
> 9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vcvtbf82bf4s\[ \\t\]*%ymm\[0-
> 9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vcvtbf82bf4s\[ \\t\]*%zmm\[0-
> 9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vcvthf82bf4s\[ \\t\]*%xmm\[0-
> 9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vcvthf82bf4s\[ \\t\]*%ymm\[0-
> 9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vcvthf82bf4s\[ \\t\]*%zmm\[0-
> 9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +
> +#include <immintrin.h>
> +
> +volatile __m128i x128i;
> +volatile __m256i x256i;
> +volatile __m512i x512i;
> +
> +void extern
> +avx10v2aux_vcvtbf82bf4s_test (void)
> +{
> + x128i = _mm_cvts_bf8_bf4 (x128i);
> + x128i = _mm256_cvts_bf8_bf4 (x256i);
> + x256i = _mm512_cvts_bf8_bf4 (x512i);
> +}
> +
> +void extern
> +avx10v2aux_vcvthf82bf4s_test (void)
> +{
> + x128i = _mm_cvts_hf8_bf4 (x128i);
> + x128i = _mm256_cvts_hf8_bf4 (x256i);
> + x256i = _mm512_cvts_hf8_bf4 (x512i);
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1f.c
> b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1f.c
> new file mode 100644
> index 00000000000..afed68f8ec6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1f.c
> @@ -0,0 +1,36 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx10v2aux -O2 -fno-fuse-ops-with-volatile-access" } */
> +/* { dg-final { scan-assembler-times "vcvtbf42hf8\[ \\t\]*%xmm\[0-
> 9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vcvtbf42hf8\[ \\t\]*%xmm\[0-
> 9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vcvtbf42hf8\[ \\t\]*%xmm\[0-
> 9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vcvtbf42hf8\[ \\t\]*%xmm\[0-
> 9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vcvtbf42hf8\[ \\t\]*%xmm\[0-
> 9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vcvtbf42hf8\[ \\t\]*%xmm\[0-
> 9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vcvtbf42hf8\[ \\t\]*%ymm\[0-
> 9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vcvtbf42hf8\[ \\t\]*%ymm\[0-
> 9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vcvtbf42hf8\[ \\t\]*%ymm\[0-
> 9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
> +
> +#include <immintrin.h>
> +
> +volatile __m128i x128i;
> +volatile __m256i x256i;
> +volatile __m512i x512i;
> +volatile __mmask16 m16;
> +volatile __mmask32 m32;
> +volatile __mmask64 m64;
> +
> +void extern
> +avx10v2aux_vcvtbf42hf8_test (void)
> +{
> + x128i = _mm_cvtbf4_hf8 (x128i);
> + x128i = _mm_mask_cvtbf4_hf8 (x128i, m16, x128i);
> + x128i = _mm_maskz_cvtbf4_hf8 (m16, x128i);
> +
> + x256i = _mm256_cvtbf4_hf8 (x128i);
> + x256i = _mm256_mask_cvtbf4_hf8 (x256i, m32, x128i);
> + x256i = _mm256_maskz_cvtbf4_hf8 (m32, x128i);
> +
> + x512i = _mm512_cvtbf4_hf8 (x256i);
> + x512i = _mm512_mask_cvtbf4_hf8 (x512i, m64, x256i);
> + x512i = _mm512_maskz_cvtbf4_hf8 (m64, x256i);
> +}
> --
> 2.34.1
