Christophe Lyon (clyon) <[email protected]>) commented on the code:
> +++ gcc/config/arm/neon.md > @@ -3549,0 +3580,4 @@ > +; There isn't an intrinsic for this, but the compiler can generate it > +; idomatically from other operations. > +(define_insn_and_split "neon_vdupq_lane<mode>_internal" > + [(set (match_operand:VQ2BF 0 "s_register_operand" "=w,w") Doesn't this overlap with the previous pattern? VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF] VQ2BF [V16QI V8HI V8HF (V8BF "TARGET_BF16_SIMD") V4SI V4SF] > +++ gcc/config/arm/neon.md > @@ -3535,0 +3531,4 @@ > + (vec_duplicate:VDQW > + (vec_select:<V_elem> > + (match_operand:<V_double_vector_mode> 1 "s_register_operand" "w,r") > + (parallel [(match_operand:SI 2 "immediate_operand" "i,i")])))) Why is there a 'parallel' here? -- https://forge.sourceware.org/gcc/gcc/pulls/208#issuecomment-7019
