Add param for controlling HSSR code generation.
Adds this to relevant tests that would otherwise break due to later added
extra versioning or use of HSSR.
gcc/ChangeLog:
* params.opt: New param.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/noeffect11.c: Add --param=vect-hssr-usage=0
* gcc.target/aarch64/sve/peel_ind_1.c: Ditto.
* gcc.target/aarch64/sve/peel_ind_12.c: Ditto.
* gcc.target/aarch64/sve/peel_ind_13.c: Ditto.
* gcc.target/aarch64/sve/peel_ind_14.c: Ditto.
* gcc.target/aarch64/sve/peel_ind_15.c: Ditto.
* gcc.target/aarch64/sve/peel_ind_16.c: Ditto.
* gcc.target/aarch64/sve/peel_ind_17.c: Ditto.
* gcc.target/aarch64/sve/peel_ind_2.c: Ditto.
* gcc.target/aarch64/sve/peel_ind_3.c: Ditto.
* gcc.target/aarch64/sve/peel_ind_4.c: Ditto.
* gcc.target/aarch64/sve/peel_ind_5.c: Ditto.
* gcc.target/aarch64/sve/peel_ind_6.c: Ditto.
* gcc.target/aarch64/sve/peel_ind_7.c: Ditto.
* gcc.target/aarch64/sve/peel_ind_8.c: Ditto.
* gcc.target/aarch64/sve/peel_ind_9.c: Ditto.
* gcc.target/aarch64/sve/peeled.c: Ditto.
* gcc.target/aarch64/sve/peeled1.c: Ditto.
* gcc.target/aarch64/sve/peeled2.c: Ditto.
* gcc.target/aarch64/sve/peeled3.c: Ditto.
---
gcc/params.opt | 4 ++++
gcc/testsuite/gcc.target/aarch64/sve/noeffect11.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peel_ind_1.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peel_ind_12.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peel_ind_13.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peel_ind_14.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peel_ind_15.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peel_ind_16.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peel_ind_17.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peel_ind_3.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peel_ind_4.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peel_ind_5.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peel_ind_6.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peel_ind_7.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peel_ind_8.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peel_ind_9.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peeled.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peeled1.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peeled2.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peeled3.c | 2 +-
21 files changed, 24 insertions(+), 20 deletions(-)
diff --git a/gcc/params.opt b/gcc/params.opt
index 044c4a10bc4..881efa2d02b 100644
--- a/gcc/params.opt
+++ b/gcc/params.opt
@@ -1291,6 +1291,10 @@ Bound on number of runtime checks inserted by the
vectorizer's loop versioning f
Common Joined UInteger Var(param_vect_partial_vector_usage) Init(2)
IntegerRange(0, 2) Param Optimization NoOffload
Controls how loop vectorizer uses partial vectors. 0 means never, 1 means
only for loops whose need to iterate can be removed, 2 means for all loops.
The default value is 2.
+-param=vect-hssr-usage=
+Common Joined UInteger Var(param_vect_hssr_usage) Init(0) IntegerRange(0, 2)
Param Optimization NoOffload
+Controls how loop vectorizer uses hardware safe speculative loads. 0 means
never, 1 means only when profitable, 2 means whenever possible. The default
value is 2.
+
-param=vect-inner-loop-cost-factor=
Common Joined UInteger Var(param_vect_inner_loop_cost_factor) Init(50)
IntegerRange(1, 10000) Param Optimization NoOffload
The maximum factor which the loop vectorizer applies to the cost of statements
in an inner loop relative to the loop being vectorized.
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/noeffect11.c
b/gcc/testsuite/gcc.target/aarch64/sve/noeffect11.c
index 5c8c3565da6..0f781496fad 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/noeffect11.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/noeffect11.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O3 -march=armv8-a+sve
--param=aarch64-autovec-preference=sve-only -msve-vector-bits=scalable" } */
+/* { dg-options "-O3 -march=armv8-a+sve
--param=aarch64-autovec-preference=sve-only -msve-vector-bits=scalable
--param=vect-hssr-usage=0" } */
/* { dg-final { check-function-bodies "**" "" "" } } */
/*
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_1.c
index e9afc2047e4..ed454669ab2 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_1.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* Pick an arbitrary target for which unaligned accesses are more
expensive. */
-/* { dg-options "-O3 -msve-vector-bits=256 -mtune=thunderx" } */
+/* { dg-options "-O3 -msve-vector-bits=256 -mtune=thunderx
--param=vect-hssr-usage=0" } */
#define N 512
#define START 1
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_12.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_12.c
index e3ed63afb05..2eaa374cae7 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_12.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_12.c
@@ -1,6 +1,6 @@
/* Peeling for alignment with masking together with versioning in VLA modes.
*/
/* { dg-do compile } */
-/* { dg-options "-Ofast -msve-vector-bits=scalable --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
+/* { dg-options "-Ofast -msve-vector-bits=scalable --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details
--param=vect-hssr-usage=0" } */
#define START 5
#define END 509
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_13.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_13.c
index 730e33ed8f7..e733bd05e06 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_13.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_13.c
@@ -1,6 +1,6 @@
/* Known inbounds DR in VLA modes. */
/* { dg-do compile } */
-/* { dg-options "-Ofast -msve-vector-bits=scalable --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
+/* { dg-options "-Ofast -msve-vector-bits=scalable --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details
--param=vect-hssr-usage=0" } */
#define N 512
#define START 5
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_14.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_14.c
index b2f4650bb2c..6a7a4bafc88 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_14.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_14.c
@@ -1,6 +1,6 @@
/* Fix for PR123089 alignment peeling with vectors and VLS and overflows. */
/* { dg-do compile } */
-/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only
-fdump-tree-vect-details" } */
+/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only
-fdump-tree-vect-details --param=vect-hssr-usage=0" } */
/* { dg-additional-options "-msve-vector-bits=256" { target aarch64_sve256_hw
} } */
/* { dg-additional-options "-msve-vector-bits=128" { target aarch64_sve128_hw
} } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_15.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_15.c
index b2f4650bb2c..6a7a4bafc88 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_15.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_15.c
@@ -1,6 +1,6 @@
/* Fix for PR123089 alignment peeling with vectors and VLS and overflows. */
/* { dg-do compile } */
-/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only
-fdump-tree-vect-details" } */
+/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only
-fdump-tree-vect-details --param=vect-hssr-usage=0" } */
/* { dg-additional-options "-msve-vector-bits=256" { target aarch64_sve256_hw
} } */
/* { dg-additional-options "-msve-vector-bits=128" { target aarch64_sve128_hw
} } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_16.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_16.c
index b2f4650bb2c..6a7a4bafc88 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_16.c
@@ -1,6 +1,6 @@
/* Fix for PR123089 alignment peeling with vectors and VLS and overflows. */
/* { dg-do compile } */
-/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only
-fdump-tree-vect-details" } */
+/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only
-fdump-tree-vect-details --param=vect-hssr-usage=0" } */
/* { dg-additional-options "-msve-vector-bits=256" { target aarch64_sve256_hw
} } */
/* { dg-additional-options "-msve-vector-bits=128" { target aarch64_sve128_hw
} } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_17.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_17.c
index 5395a759c61..08623e8f379 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_17.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_17.c
@@ -1,6 +1,6 @@
/* Fix for PR123089 alignment peeling with vectors and VLS and overflows. */
/* { dg-do compile } */
-/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only
-fdump-tree-vect-details" } */
+/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only
-fdump-tree-vect-details --param=vect-hssr-usage=0" } */
/* { dg-additional-options "-msve-vector-bits=256" { target aarch64_sve256_hw
} } */
/* { dg-additional-options "-msve-vector-bits=128" { target aarch64_sve128_hw
} } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c
index f07900b2f0a..cb0a1e8cf88 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* Pick an arbitrary target for which unaligned accesses are more
expensive. */
-/* { dg-options "-O3 -msve-vector-bits=256 -mtune=thunderx
-fno-vect-cost-model" } */
+/* { dg-options "-O3 -msve-vector-bits=256 -mtune=thunderx
-fno-vect-cost-model --param=vect-hssr-usage=0" } */
#define N 512
#define START 7
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_3.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_3.c
index 15da5a7e696..5f014e568e1 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_3.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* Pick an arbitrary target for which unaligned accesses are more
expensive. */
-/* { dg-options "-O3 -msve-vector-bits=256 -mtune=thunderx
-fno-vect-cost-model" } */
+/* { dg-options "-O3 -msve-vector-bits=256 -mtune=thunderx
-fno-vect-cost-model --param=vect-hssr-usage=0" } */
#define N 32
#define MAX_START 8
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_4.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_4.c
index 5b5d88ad521..ad9ed058a48 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_4.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* Pick an arbitrary target for which unaligned accesses are more
expensive. */
-/* { dg-options "-Ofast -msve-vector-bits=256 -mtune=thunderx
-fno-vect-cost-model" } */
+/* { dg-options "-Ofast -msve-vector-bits=256 -mtune=thunderx
-fno-vect-cost-model --param=vect-hssr-usage=0" } */
#define START 1
#define END 505
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_5.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_5.c
index 1977bf3af2d..ac448ed1db4 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_5.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_5.c
@@ -1,6 +1,6 @@
/* Fix for PR119351 alignment peeling with vectors and VLS. */
/* { dg-do compile } */
-/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
+/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details
--param=vect-hssr-usage=0" } */
#define N 512
#define START 2
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_6.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_6.c
index 0b40d26ae2a..d725f636117 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_6.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_6.c
@@ -1,6 +1,6 @@
/* Fix for PR119351 alignment peeling with vectors and VLS. */
/* { dg-do compile } */
-/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
+/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details
--param=vect-hssr-usage=0" } */
#define N 512
#define START 1
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_7.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_7.c
index 7a24d689e95..c7da8828313 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_7.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_7.c
@@ -1,6 +1,6 @@
/* Fix for PR119351 alignment peeling with vectors and VLS. */
/* { dg-do compile } */
-/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
+/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details
--param=vect-hssr-usage=0" } */
#define N 512
#define START 1
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_8.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_8.c
index 043348b55d0..58e36d1fcb1 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_8.c
@@ -1,6 +1,6 @@
/* Fix for PR119351 alignment peeling with vectors and VLS. */
/* { dg-do compile } */
-/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
+/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details
--param=vect-hssr-usage=0" } */
#define N 512
#define START 1
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_9.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_9.c
index 136d18c2ea8..a08d4aa5be5 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_9.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_9.c
@@ -1,6 +1,6 @@
/* Fix for PR119351 alignment peeling with vectors and VLS. */
/* { dg-do compile } */
-/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
+/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details
--param=vect-hssr-usage=0" } */
#define N 512
#define START 1
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peeled.c
b/gcc/testsuite/gcc.target/aarch64/sve/peeled.c
index f40ffc8f0bc..60c6c7877b1 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peeled.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peeled.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -mautovec-preference=sve-only -msve-vector-bits=scalable"
} */
+/* { dg-options "-O3 -mautovec-preference=sve-only -msve-vector-bits=scalable
--param=vect-hssr-usage=0" } */
char b[100];
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peeled1.c
b/gcc/testsuite/gcc.target/aarch64/sve/peeled1.c
index 92e5bca44c4..5a5e398ad5d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peeled1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peeled1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -mautovec-preference=sve-only -msve-vector-bits=scalable"
} */
+/* { dg-options "-O3 -mautovec-preference=sve-only -msve-vector-bits=scalable
--param=vect-hssr-usage=0" } */
char b[100];
char e[100];
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peeled2.c
b/gcc/testsuite/gcc.target/aarch64/sve/peeled2.c
index c29dab4b553..4620e9965e1 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peeled2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peeled2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -mautovec-preference=sve-only -msve-vector-bits=scalable"
} */
+/* { dg-options "-O3 -mautovec-preference=sve-only -msve-vector-bits=scalable
--param=vect-hssr-usage=0" } */
char b[100];
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peeled3.c
b/gcc/testsuite/gcc.target/aarch64/sve/peeled3.c
index 8d82828b770..e629b0898d3 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peeled3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peeled3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -mautovec-preference=sve-only -msve-vector-bits=scalable
-fdump-tree-vect-details" } */
+/* { dg-options "-O3 -mautovec-preference=sve-only -msve-vector-bits=scalable
-fdump-tree-vect-details --param=vect-hssr-usage=0" } */
int __attribute__ ((noipa))
c (int *restrict x, int *restrict y, int n)
--
2.43.0
