From: Pan Li <[email protected]>
Like vwmacc[u].vv, allow the rvv register overlap for the dual
widen ternary vv insn vwmaccsu.vv, which has the mixed signed
and unsigned narrowed sources.
gcc/ChangeLog:
* config/riscv/vector.md: Leverage Wvr constraint.
Signed-off-by: Pan Li <[email protected]>
---
gcc/config/riscv/vector.md | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index c2d5bf31296..3ce8e874587 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -6120,23 +6120,23 @@ (define_insn "@pred_widen_mul_plus<su><mode>_scalar"
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
(define_insn "@pred_widen_mul_plussu<mode>"
- [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
+ [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vd")
(if_then_else:VWEXTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rvl")
- (match_operand 6 "const_int_operand" " i")
- (match_operand 7 "const_int_operand" " i")
- (match_operand 8 "const_int_operand" " i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "Wc1, vm")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
+ (match_operand 8 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus:VWEXTI
(mult:VWEXTI
(sign_extend:VWEXTI
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
+ (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "Wvr,
Wvr"))
(zero_extend:VWEXTI
- (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
- (match_operand:VWEXTI 2 "register_operand" " 0"))
+ (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "Wvr,
Wvr")))
+ (match_operand:VWEXTI 2 "register_operand" " 0,
0"))
(match_dup 2)))]
"TARGET_VECTOR"
"vwmaccsu.vv\t%0,%3,%4%p1"
--
2.43.0
