gcc/ChangeLog:
* config/i386/i386.cc (regclass_map): Add tmm.
(debugger64_register_map): Ditto.
(debugger_register_map): Ditto. Also fix for APX r16-31.
(svr4_debugger_register_map): Ditto.
(ix86_conditional_register_usage): Enable tmm only when AMX
or ACE exists.
* config/i386/i386.h (FIXED_REGISTERS): Ditto.
(CALL_USED_REGISTERS): Ditto.
(REG_ALLOC_ORDER): Ditto.
(HI_REGISTER_NAMES): Ditto.
* config/i386/i386.md: Ditto.
---
gcc/config/i386/i386.cc | 30 +++++++++++++++++++++++++++---
gcc/config/i386/i386.h | 13 +++++++++----
gcc/config/i386/i386.md | 3 ++-
3 files changed, 38 insertions(+), 8 deletions(-)
diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index dcfe4531f11..cc41006b291 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -179,6 +179,8 @@ enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
+ /* TMM fake register placeholder */
+ NO_REGS,
};
/* The "default" register map used in 32bit mode. */
@@ -209,7 +211,14 @@ unsigned int const
debugger_register_map[FIRST_PSEUDO_REGISTER] =
INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM,
INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM,
/* Mask registers */
- 93, 94, 95, 96, 97, 98, 99, 100
+ 93, 94, 95, 96, 97, 98, 99, 100,
+ /* APX r16-r31 */
+ INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM,
+ INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM,
+ INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM,
+ INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM,
+ /* TMM fake register placeholder */
+ INVALID_REGNUM,
};
/* The "default" register map used in 64bit mode. */
@@ -239,7 +248,9 @@ unsigned int const
debugger64_register_map[FIRST_PSEUDO_REGISTER] =
118, 119, 120, 121, 122, 123, 124, 125,
/* rex2 extend integer registers */
130, 131, 132, 133, 134, 135, 136, 137,
- 138, 139, 140, 141, 142, 143, 144, 145
+ 138, 139, 140, 141, 142, 143, 144, 145,
+ /* tmm fake register placeholder */
+ IGNORED_DWARF_REGNUM,
};
/* Define the register numbers to be used in Dwarf debugging information.
@@ -322,7 +333,14 @@ unsigned int const
svr4_debugger_register_map[FIRST_PSEUDO_REGISTER] =
INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM,
INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM,
/* Mask registers */
- 93, 94, 95, 96, 97, 98, 99, 100
+ 93, 94, 95, 96, 97, 98, 99, 100,
+ /* APX r16-r31 */
+ INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM,
+ INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM,
+ INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM,
+ INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM,
+ /* TMM fake register placeholder */
+ INVALID_REGNUM,
};
/* Define parameter passing and return registers. */
@@ -564,6 +582,12 @@ ix86_conditional_register_usage (void)
for (i = FIRST_REX2_INT_REG; i <= LAST_REX2_INT_REG; i++)
CLEAR_HARD_REG_BIT (accessible_reg_set, i);
}
+
+ /* If AMX-TILE or ACEV1 is disabled, disable tmm registers. */
+ if (! (TARGET_AMX_TILE || TARGET_ACEV1))
+ {
+ CLEAR_HARD_REG_BIT (accessible_reg_set, TMM_REGNUM);
+ }
}
/* Canonicalize a comparison from one we don't have to one we do have. */
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 26c3b73a50f..f1bc63ab981 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1025,7 +1025,9 @@ extern const char *host_detect_local_cpu (int argc, const
char **argv);
/* r16, r17, r18, r19, r20, r21, r22, r23*/ \
0, 0, 0, 0, 0, 0, 0, 0, \
/* r24, r25, r26, r27, r28, r29, r30, r31*/ \
- 0, 0, 0, 0, 0, 0, 0, 0} \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+/* tmm*/ \
+ 1} \
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
@@ -1066,7 +1068,9 @@ extern const char *host_detect_local_cpu (int argc, const
char **argv);
/* r16, r17, r18, r19, r20, r21, r22, r23*/ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* r24, r25, r26, r27, r28, r29, r30, r31*/ \
- 1, 1, 1, 1, 1, 1, 1, 1} \
+ 1, 1, 1, 1, 1, 1, 1, 1, \
+/* tmm*/ \
+ 1} \
/* Order in which to allocate registers. Each register must be
listed once, even those in FIXED_REGISTERS. List frame pointer
@@ -1083,7 +1087,7 @@ extern const char *host_detect_local_cpu (int argc, const
char **argv);
32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
- 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91}
+ 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92}
/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
to be rearranged based on a particular function. When using sse math,
@@ -2105,7 +2109,8 @@ do {
\
"xmm28", "xmm29", "xmm30", "xmm31", \
"k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", \
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
- "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" }
+ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
+ "tmm"}
#define REGISTER_NAMES HI_REGISTER_NAMES
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 4e18797743f..28f55fc07e2 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -508,7 +508,8 @@
(R29_REG 89)
(R30_REG 90)
(R31_REG 91)
- (FIRST_PSEUDO_REG 92)
+ (TMM_REGNUM 92)
+ (FIRST_PSEUDO_REG 93)
])
;; Insn callee abi index.
--
2.31.1
