Hi Kyrill,
+(define_expand "ctz<mode>2"
+ [(set (match_operand:VB 0 "register_operand")
+ (ctz:VB (match_operand:VB 1 "register_operand")))]
+ "TARGET_SIMD"
+ {
+ emit_insn (gen_aarch64_rbit<mode> (operands[0], operands[1]));
+ emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+ DONE;
+ }
+)
So this works, but why not generalize the above to vectors of HI, SI and DI?
The aarch64_rbit pattern can include the bswap for the wider modes.
LLVM emits the faster bswap/rbit/clz sequence for 16-bit, so it seems odd to
not improve that too.
There is an issue in that __builtin_bitreverseN does not get vectorized at any
size
by GCC, while LLVM vectorizes it for 8/16/32 and 64 bit.
Cheers,
Wilco
