[PATCH v1 1/7] RISC-V: Allow RVV register overlap for vw{add, sub, mul}[u].vx

[pan2 . li]

From: Pan Li <pan2...@intel.com>

Like vw{add,sub,mul}[u].vv, allow the rvv register overlap for the dual
widen vx insns, aka vwadd[u].vx, vwsub[u].vx and vwmul[u].vx.

gcc/ChangeLog:

        * config/riscv/vector.md: Leverage Wvr constraint.

Signed-off-by: Pan Li <pan2...@intel.com>
---
 gcc/config/riscv/vector.md | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 3ce8e874587..891561bebb7 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -4172,23 +4172,23 @@ (define_insn 
"@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>"
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
 
 (define_insn 
"@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>_scalar"
-  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr,&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                 "=vr, vr, 
vd, vd")
        (if_then_else:VWEXTI
          (unspec:<VM>
-           [(match_operand:<VM> 1 "vector_mask_operand"           
"vmWc1,vmWc1")
-            (match_operand 5 "vector_length_operand"              "  rvl,  
rvl")
-            (match_operand 6 "const_int_operand"                  "    i,    
i")
-            (match_operand 7 "const_int_operand"                  "    i,    
i")
-            (match_operand 8 "const_int_operand"                  "    i,    
i")
+           [(match_operand:<VM> 1 "vector_mask_operand"           "Wc1,Wc1, 
vm, vm")
+            (match_operand 5 "vector_length_operand"              
"rvl,rvl,rvl,rvl")
+            (match_operand 6 "const_int_operand"                  "  i,  i,  
i,  i")
+            (match_operand 7 "const_int_operand"                  "  i,  i,  
i,  i")
+            (match_operand 8 "const_int_operand"                  "  i,  i,  
i,  i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (any_widen_binop:VWEXTI
            (any_extend:VWEXTI
-             (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   
vr"))
+             (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" 
"Wvr,Wvr,Wvr,Wvr"))
            (any_extend:VWEXTI
              (vec_duplicate:<V_DOUBLE_TRUNC>
-               (match_operand:<VSUBEL> 4 "reg_or_0_operand"       "   rJ,   
rJ"))))
-         (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    
0")))]
+               (match_operand:<VSUBEL> 4 "reg_or_0_operand"       " rJ, rJ, 
rJ, rJ"))))
+         (match_operand:VWEXTI 2 "vector_merge_operand"           " vu,  0, 
vu,  0")))]
   "TARGET_VECTOR"
   "vw<any_widen_binop:insn><any_extend:u>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "vi<widen_binop_insn_type>")
-- 
2.43.0