Double unaligned load store cost for V2QImode and V2HImode when SSE is
enabled and SSE4.1, which improved support for QImode and HImode, is
disabled to avoid using inefficient SSE2 instructions to access vector
elements in V2QImode and V2HImode so that for
extern char *var1;
extern int var2;
void
func (void)
{
var2 = var1[1] + var1[0];
}
we generate
movq var1(%rip), %rdx
movsbl 1(%rdx), %eax
movsbl (%rdx), %edx
addl %edx, %eax
movl %eax, var2(%rip)
instead of
movq var1(%rip), %rax
pxor %xmm1, %xmm1
pinsrw $0, (%rax), %xmm0
pcmpgtb %xmm0, %xmm1
punpcklbw %xmm1, %xmm0
movdqa %xmm0, %xmm1
psraw $15, %xmm1
punpcklwd %xmm1, %xmm0
movd %xmm0, %edx
pshufd $0xe5, %xmm0, %xmm2
movd %xmm2, %eax
addl %edx, %eax
movl %eax, var2(%rip)
with -O2 -march=x86-64. With SSE4.1 enabled, we generate
movq var1(%rip), %rax
pinsrw $0, (%rax), %xmm0
pmovsxbd %xmm0, %xmm0
movd %xmm0, %edx
pextrd $1, %xmm0, %eax
addl %edx, %eax
movl %eax, var2(%rip)
Compile PR 125100 tests with -mno-sse since unaligned V2QImode load is no
longer generated when SSE is enabled without SSE4.1.
gcc/
PR target/126802
* config/i386/i386.cc (sse_adjust_unaligned_load_cost): New.
(ix86_default_vector_cost): Call sse_adjust_unaligned_load_cost
for unaligned load to adjust unaligned load cost.
testsuite/
PR target/126802
* gcc.target/i386/pr125100-1.c: Add -mno-sse.
* gcc.target/i386/pr125100-2.c: Likewise.
* gcc.target/i386/pr125100-3.c: Likewise.
* gcc.target/i386/pr126802-1a.c: New test.
* gcc.target/i386/pr126802-1b.c: Likewise.
* gcc.target/i386/pr126802-1c.c: Likewise.
* gcc.target/i386/pr126802-2a.c: Likewise.
* gcc.target/i386/pr126802-2b.c: Likewise.
* gcc.target/i386/pr126802-2c.c: Likewise.
* gcc.target/i386/pr126802-3a.c: Likewise.
* gcc.target/i386/pr126802-3b.c: Likewise.
* gcc.target/i386/pr126802-3c.c: Likewise.
* gcc.target/i386/pr126802-4a.c: Likewise.
* gcc.target/i386/pr126802-4b.c: Likewise.
* gcc.target/i386/pr126802-4c.c: Likewise.
--
H.J.
From 89ee2dd884ad4a1bebd047fabbc8de9e29673966 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <[email protected]>
Date: Wed, 12 Aug 2026 06:57:32 +0800
Subject: [PATCH v2] x86: Double unaligned load cost for V2QImode and V2HImode
Double unaligned load store cost for V2QImode and V2HImode when SSE is
enabled and SSE4.1, which improved support for QImode and HImode, is
disabled to avoid using inefficient SSE2 instructions to access vector
elements in V2QImode and V2HImode so that for
extern char *var1;
extern int var2;
void
func (void)
{
var2 = var1[1] + var1[0];
}
we generate
movq var1(%rip), %rdx
movsbl 1(%rdx), %eax
movsbl (%rdx), %edx
addl %edx, %eax
movl %eax, var2(%rip)
instead of
movq var1(%rip), %rax
pxor %xmm1, %xmm1
pinsrw $0, (%rax), %xmm0
pcmpgtb %xmm0, %xmm1
punpcklbw %xmm1, %xmm0
movdqa %xmm0, %xmm1
psraw $15, %xmm1
punpcklwd %xmm1, %xmm0
movd %xmm0, %edx
pshufd $0xe5, %xmm0, %xmm2
movd %xmm2, %eax
addl %edx, %eax
movl %eax, var2(%rip)
with -O2 -march=x86-64. With SSE4.1 enabled, we generate
movq var1(%rip), %rax
pinsrw $0, (%rax), %xmm0
pmovsxbd %xmm0, %xmm0
movd %xmm0, %edx
pextrd $1, %xmm0, %eax
addl %edx, %eax
movl %eax, var2(%rip)
Compile PR 125100 tests with -mno-sse since unaligned V2QImode load is no
longer generated when SSE is enabled without SSE4.1.
gcc/
PR target/126802
* config/i386/i386.cc (sse_adjust_unaligned_load_cost): New.
(ix86_default_vector_cost): Call sse_adjust_unaligned_load_cost
for unaligned load to adjust unaligned load cost.
testsuite/
PR target/126802
* gcc.target/i386/pr125100-1.c: Add -mno-sse.
* gcc.target/i386/pr125100-2.c: Likewise.
* gcc.target/i386/pr125100-3.c: Likewise.
* gcc.target/i386/pr126802-1a.c: New test.
* gcc.target/i386/pr126802-1b.c: Likewise.
* gcc.target/i386/pr126802-1c.c: Likewise.
* gcc.target/i386/pr126802-2a.c: Likewise.
* gcc.target/i386/pr126802-2b.c: Likewise.
* gcc.target/i386/pr126802-2c.c: Likewise.
* gcc.target/i386/pr126802-3a.c: Likewise.
* gcc.target/i386/pr126802-3b.c: Likewise.
* gcc.target/i386/pr126802-3c.c: Likewise.
* gcc.target/i386/pr126802-4a.c: Likewise.
* gcc.target/i386/pr126802-4b.c: Likewise.
* gcc.target/i386/pr126802-4c.c: Likewise.
Signed-off-by: H.J. Lu <[email protected]>
---
gcc/config/i386/i386.cc | 19 ++++++++++-
gcc/testsuite/gcc.target/i386/pr125100-1.c | 2 +-
gcc/testsuite/gcc.target/i386/pr125100-2.c | 2 +-
gcc/testsuite/gcc.target/i386/pr125100-3.c | 2 +-
gcc/testsuite/gcc.target/i386/pr126802-1a.c | 26 +++++++++++++++
gcc/testsuite/gcc.target/i386/pr126802-1b.c | 21 ++++++++++++
gcc/testsuite/gcc.target/i386/pr126802-1c.c | 21 ++++++++++++
gcc/testsuite/gcc.target/i386/pr126802-2a.c | 26 +++++++++++++++
gcc/testsuite/gcc.target/i386/pr126802-2b.c | 21 ++++++++++++
gcc/testsuite/gcc.target/i386/pr126802-2c.c | 21 ++++++++++++
gcc/testsuite/gcc.target/i386/pr126802-3a.c | 25 ++++++++++++++
gcc/testsuite/gcc.target/i386/pr126802-3b.c | 18 +++++++++++
gcc/testsuite/gcc.target/i386/pr126802-3c.c | 18 +++++++++++
gcc/testsuite/gcc.target/i386/pr126802-4a.c | 36 +++++++++++++++++++++
gcc/testsuite/gcc.target/i386/pr126802-4b.c | 23 +++++++++++++
gcc/testsuite/gcc.target/i386/pr126802-4c.c | 21 ++++++++++++
16 files changed, 298 insertions(+), 4 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr126802-1a.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr126802-1b.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr126802-1c.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr126802-2a.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr126802-2b.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr126802-2c.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr126802-3a.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr126802-3b.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr126802-3c.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr126802-4a.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr126802-4b.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr126802-4c.c
diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index 540de87a41d..64097067114 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -21577,6 +21577,21 @@ sse_store_index (machine_mode mode)
}
}
+/* Adjust unaligned load store cost. */
+
+static inline int
+sse_adjust_unaligned_load_cost (int cost, machine_mode mode)
+{
+ /* PR 126802 - Double unaligned load and store cost for V2QImode and
+ V2HImode when SSE is enabled and SSE4.1, which improved support
+ for QImode and HImode, is disabled. */
+ if (TARGET_SSE
+ && !TARGET_SSE4_1
+ && (mode == V2QImode || mode == V2HImode))
+ cost += cost;
+ return cost;
+}
+
/* Return the cost of moving data of mode M between a
register and memory. A value of 2 is the default; this cost is
relative to those in `REGISTER_MOVE_COST'.
@@ -26053,7 +26068,9 @@ ix86_default_vector_cost (enum vect_cost_for_stmt type_of_cost,
/* See PR82713 - we may end up being called on non-vector type. */
if (index < 0)
index = 2;
- return COSTS_N_INSNS (ix86_cost->sse_unaligned_load[index]) / 2;
+ return sse_adjust_unaligned_load_cost
+ (COSTS_N_INSNS (ix86_cost->sse_unaligned_load[index]) / 2,
+ mode);
case unaligned_store:
index = sse_store_index (mode);
diff --git a/gcc/testsuite/gcc.target/i386/pr125100-1.c b/gcc/testsuite/gcc.target/i386/pr125100-1.c
index 21765a5843e..d1f537e981b 100644
--- a/gcc/testsuite/gcc.target/i386/pr125100-1.c
+++ b/gcc/testsuite/gcc.target/i386/pr125100-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target fpic } } */
-/* { dg-options "-mtune=generic -O2 -fPIC" } */
+/* { dg-options "-mtune=generic -mno-sse -O2 -fPIC" } */
/* { dg-additional-options "-march=pentiumpro" { target ia32 } } */
struct desc {
diff --git a/gcc/testsuite/gcc.target/i386/pr125100-2.c b/gcc/testsuite/gcc.target/i386/pr125100-2.c
index d179c3f4050..23ca7d9a7a6 100644
--- a/gcc/testsuite/gcc.target/i386/pr125100-2.c
+++ b/gcc/testsuite/gcc.target/i386/pr125100-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target fpic } } */
-/* { dg-options "-mtune=generic -O2 -fPIC" } */
+/* { dg-options "-mtune=generic -mno-sse -O2 -fPIC" } */
/* { dg-additional-options "-march=pentiumpro" { target ia32 } } */
struct desc {
diff --git a/gcc/testsuite/gcc.target/i386/pr125100-3.c b/gcc/testsuite/gcc.target/i386/pr125100-3.c
index 2015ee819b3..0727086a578 100644
--- a/gcc/testsuite/gcc.target/i386/pr125100-3.c
+++ b/gcc/testsuite/gcc.target/i386/pr125100-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target fpic } } */
-/* { dg-options "-mtune=generic -O2 -fPIC" } */
+/* { dg-options "-mtune=generic -mno-sse -O2 -fPIC" } */
/* { dg-additional-options "-march=pentiumpro" { target ia32 } } */
struct desc {
diff --git a/gcc/testsuite/gcc.target/i386/pr126802-1a.c b/gcc/testsuite/gcc.target/i386/pr126802-1a.c
new file mode 100644
index 00000000000..37b9918f48f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr126802-1a.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64" } */
+/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */
+/* { dg-final { check-function-bodies "**" "" "" { target { *-*-linux* && lp64 } } {^\t?\.} } } */
+
+/*
+**func:
+**.LFB0:
+** .cfi_startproc
+** movq var1\(%rip\), %rdx
+** movsbl 1\(%rdx\), %eax
+** movsbl \(%rdx\), %edx
+** addl %edx, %eax
+** movl %eax, var2\(%rip\)
+** ret
+**...
+*/
+
+extern char *var1;
+extern int var2;
+
+void
+func (void)
+{
+ var2 = var1[1] + var1[0];
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr126802-1b.c b/gcc/testsuite/gcc.target/i386/pr126802-1b.c
new file mode 100644
index 00000000000..51e4d65d7e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr126802-1b.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64-v2" } */
+/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */
+/* { dg-final { check-function-bodies "**" "" "" { target { *-*-linux* && lp64 } } {^\t?\.} } } */
+
+/*
+**func:
+**.LFB0:
+** .cfi_startproc
+** movq var1\(%rip\), %rax
+** pinsrw \$0, \(%rax\), %xmm0
+** pmovsxbd %xmm0, %xmm0
+** movd %xmm0, %edx
+** pextrd \$1, %xmm0, %eax
+** addl %edx, %eax
+** movl %eax, var2\(%rip\)
+** ret
+**...
+*/
+
+#include "pr126802-1a.c"
diff --git a/gcc/testsuite/gcc.target/i386/pr126802-1c.c b/gcc/testsuite/gcc.target/i386/pr126802-1c.c
new file mode 100644
index 00000000000..2bdbae0e416
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr126802-1c.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64-v4" } */
+/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */
+/* { dg-final { check-function-bodies "**" "" "" { target { *-*-linux* && lp64 } } {^\t?\.} } } */
+
+/*
+**func:
+**.LFB0:
+** .cfi_startproc
+** movq var1\(%rip\), %rax
+** vpinsrw \$0, \(%rax\), %xmm0, %xmm0
+** vpmovsxbd %xmm0, %xmm0
+** vmovd %xmm0, %edx
+** vpextrd \$1, %xmm0, %eax
+** addl %edx, %eax
+** movl %eax, var2\(%rip\)
+** ret
+**...
+*/
+
+#include "pr126802-1a.c"
diff --git a/gcc/testsuite/gcc.target/i386/pr126802-2a.c b/gcc/testsuite/gcc.target/i386/pr126802-2a.c
new file mode 100644
index 00000000000..cd833388530
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr126802-2a.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64" } */
+/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */
+/* { dg-final { check-function-bodies "**" "" "" { target { *-*-linux* && lp64 } } {^\t?\.} } } */
+
+/*
+**func:
+**.LFB0:
+** .cfi_startproc
+** movq var1\(%rip\), %rdx
+** movswl 2\(%rdx\), %eax
+** movswl \(%rdx\), %edx
+** addl %edx, %eax
+** movl %eax, var2\(%rip\)
+** ret
+**...
+*/
+
+extern short *var1;
+extern int var2;
+
+void
+func (void)
+{
+ var2 = var1[1] + var1[0];
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr126802-2b.c b/gcc/testsuite/gcc.target/i386/pr126802-2b.c
new file mode 100644
index 00000000000..545e4372513
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr126802-2b.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64-v2" } */
+/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */
+/* { dg-final { check-function-bodies "**" "" "" { target { *-*-linux* && lp64 } } {^\t?\.} } } */
+
+/*
+**func:
+**.LFB0:
+** .cfi_startproc
+** movq var1\(%rip\), %rax
+** movd \(%rax\), %xmm0
+** pmovsxwd %xmm0, %xmm0
+** movd %xmm0, %edx
+** pextrd \$1, %xmm0, %eax
+** addl %edx, %eax
+** movl %eax, var2\(%rip\)
+** ret
+**...
+*/
+
+#include "pr126802-2a.c"
diff --git a/gcc/testsuite/gcc.target/i386/pr126802-2c.c b/gcc/testsuite/gcc.target/i386/pr126802-2c.c
new file mode 100644
index 00000000000..abbd7d4d9a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr126802-2c.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64-v4" } */
+/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */
+/* { dg-final { check-function-bodies "**" "" "" { target { *-*-linux* && lp64 } } {^\t?\.} } } */
+
+/*
+**func:
+**.LFB0:
+** .cfi_startproc
+** movq var1\(%rip\), %rax
+** vmovd \(%rax\), %xmm0
+** vpmovsxwd %xmm0, %xmm0
+** vmovd %xmm0, %edx
+** vpextrd \$1, %xmm0, %eax
+** addl %edx, %eax
+** movl %eax, var2\(%rip\)
+** ret
+**...
+*/
+
+#include "pr126802-2a.c"
diff --git a/gcc/testsuite/gcc.target/i386/pr126802-3a.c b/gcc/testsuite/gcc.target/i386/pr126802-3a.c
new file mode 100644
index 00000000000..b2fd9b5e03e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr126802-3a.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64" } */
+/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */
+/* { dg-final { check-function-bodies "**" "" "" { target { *-*-linux* && lp64 } } {^\t?\.} } } */
+
+/*
+**func:
+**.LFB0:
+** .cfi_startproc
+** movq var1\(%rip\), %rdx
+** movl 4\(%rdx\), %eax
+** addl \(%rdx\), %eax
+** movl %eax, var2\(%rip\)
+** ret
+**...
+*/
+
+extern int *var1;
+extern int var2;
+
+void
+func (void)
+{
+ var2 = var1[1] + var1[0];
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr126802-3b.c b/gcc/testsuite/gcc.target/i386/pr126802-3b.c
new file mode 100644
index 00000000000..ca183819894
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr126802-3b.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64-v2" } */
+/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */
+/* { dg-final { check-function-bodies "**" "" "" { target { *-*-linux* && lp64 } } {^\t?\.} } } */
+
+/*
+**func:
+**.LFB0:
+** .cfi_startproc
+** movq var1\(%rip\), %rdx
+** movl 4\(%rdx\), %eax
+** addl \(%rdx\), %eax
+** movl %eax, var2\(%rip\)
+** ret
+**...
+*/
+
+#include "pr126802-3a.c"
diff --git a/gcc/testsuite/gcc.target/i386/pr126802-3c.c b/gcc/testsuite/gcc.target/i386/pr126802-3c.c
new file mode 100644
index 00000000000..4c9c9d6f137
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr126802-3c.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64-v4" } */
+/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */
+/* { dg-final { check-function-bodies "**" "" "" { target { *-*-linux* && lp64 } } {^\t?\.} } } */
+
+/*
+**func:
+**.LFB0:
+** .cfi_startproc
+** movq var1\(%rip\), %rdx
+** movl 4\(%rdx\), %eax
+** addl \(%rdx\), %eax
+** movl %eax, var2\(%rip\)
+** ret
+**...
+*/
+
+#include "pr126802-3a.c"
diff --git a/gcc/testsuite/gcc.target/i386/pr126802-4a.c b/gcc/testsuite/gcc.target/i386/pr126802-4a.c
new file mode 100644
index 00000000000..6461fdfbc0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr126802-4a.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64" } */
+/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */
+/* { dg-final { check-function-bodies "**" "" "" { target { *-*-linux* && lp64 } } {^\t?\.} } } */
+
+/*
+**func:
+**.LFB0:
+** .cfi_startproc
+** movq var1\(%rip\), %rax
+** pxor %xmm1, %xmm1
+** movd \(%rax\), %xmm0
+** pcmpgtb %xmm0, %xmm1
+** punpcklbw %xmm1, %xmm0
+** movdqa %xmm0, %xmm1
+** psraw \$15, %xmm1
+** punpcklwd %xmm1, %xmm0
+** movdqa %xmm0, %xmm1
+** psrldq \$8, %xmm1
+** paddd %xmm1, %xmm0
+** movdqa %xmm0, %xmm1
+** psrldq \$4, %xmm1
+** paddd %xmm1, %xmm0
+** movd %xmm0, var2\(%rip\)
+** ret
+**...
+*/
+
+extern char *var1;
+extern int var2;
+
+void
+func (void)
+{
+ var2 = var1[1] + var1[0] + var1[2] + var1[3];
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr126802-4b.c b/gcc/testsuite/gcc.target/i386/pr126802-4b.c
new file mode 100644
index 00000000000..04710ec9c6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr126802-4b.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64-v2" } */
+/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */
+/* { dg-final { check-function-bodies "**" "" "" { target { *-*-linux* && lp64 } } {^\t?\.} } } */
+
+/*
+**func:
+**.LFB0:
+** .cfi_startproc
+** movq var1\(%rip\), %rax
+** pmovsxbd \(%rax\), %xmm0
+** movdqa %xmm0, %xmm1
+** psrldq \$8, %xmm1
+** paddd %xmm1, %xmm0
+** movdqa %xmm0, %xmm1
+** psrldq \$4, %xmm1
+** paddd %xmm1, %xmm0
+** movd %xmm0, var2\(%rip\)
+** ret
+**...
+*/
+
+#include "pr126802-4a.c"
diff --git a/gcc/testsuite/gcc.target/i386/pr126802-4c.c b/gcc/testsuite/gcc.target/i386/pr126802-4c.c
new file mode 100644
index 00000000000..f4257eec135
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr126802-4c.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64-v4" } */
+/* Keep labels and directives ('.cfi_startproc', '.cfi_endproc'). */
+/* { dg-final { check-function-bodies "**" "" "" { target { *-*-linux* && lp64 } } {^\t?\.} } } */
+
+/*
+**func:
+**.LFB0:
+** .cfi_startproc
+** movq var1\(%rip\), %rax
+** vpmovsxbd \(%rax\), %xmm0
+** vpsrldq \$8, %xmm0, %xmm1
+** vpaddd %xmm1, %xmm0, %xmm0
+** vpsrldq \$4, %xmm0, %xmm1
+** vpaddd %xmm1, %xmm0, %xmm0
+** vmovd %xmm0, var2\(%rip\)
+** ret
+**...
+*/
+
+#include "pr126802-4a.c"
--
2.55.0
