Backport Arrow Lake and Arrow Lake-S CPU detection and target option plumbing to GCC 13 i386/x86_64 frontend and driver paths.
The patch updates CPU name handling, ISA mappings, cpuid exposure, and x86 option parsing so that -march=arrowlake, -march=arrowlake-s, -mtune=arrowlake and -mtune=arrowlake-s are accepted and wired consistently with GCC 14 behavior. Tests added for target selection and function multiversioning coverage on i386. Signed-off-by: Jakit Liang <[email protected]> --- contrib/verify-arrowlake-backport.sh | 53 +++++++++++++++++++ gcc/common/config/i386/cpuinfo.h | 26 +++++++++ gcc/common/config/i386/i386-common.cc | 8 +++ gcc/common/config/i386/i386-cpuinfo.h | 6 +++ gcc/common/config/i386/i386-isas.h | 5 ++ gcc/config/i386/cpuid.h | 20 +++++++ gcc/config/i386/driver-i386.cc | 9 +++- gcc/config/i386/i386-c.cc | 22 ++++++++ gcc/config/i386/i386-isa.def | 4 ++ gcc/config/i386/i386-options.cc | 5 ++ gcc/config/i386/i386.h | 6 +++ gcc/config/i386/i386.opt | 20 +++++++ gcc/doc/invoke.texi | 18 +++++++ gcc/testsuite/g++.target/i386/mv16.C | 12 +++++ gcc/testsuite/gcc.target/i386/arrowlake-1.c | 24 +++++++++ gcc/testsuite/gcc.target/i386/arrowlake-2.c | 36 +++++++++++++ gcc/testsuite/gcc.target/i386/arrowlake-3.c | 16 ++++++ .../gcc.target/i386/builtin_target.c | 14 +++++ 18 files changed, 303 insertions(+), 1 deletion(-) create mode 100755 contrib/verify-arrowlake-backport.sh create mode 100644 gcc/testsuite/gcc.target/i386/arrowlake-1.c create mode 100644 gcc/testsuite/gcc.target/i386/arrowlake-2.c create mode 100644 gcc/testsuite/gcc.target/i386/arrowlake-3.c diff --git a/contrib/verify-arrowlake-backport.sh b/contrib/verify-arrowlake-backport.sh new file mode 100755 index 00000000000..a627bf7387d --- /dev/null +++ b/contrib/verify-arrowlake-backport.sh @@ -0,0 +1,53 @@ +#!/usr/bin/env bash +set -euo pipefail + +if [[ $# -lt 1 ]]; then + echo "usage: $0 <build-dir>" + echo "example: $0 /home/jakit/Repos/gcc/build-gcc-13.4-arrowlake" + exit 2 +fi + +BUILD_DIR="$1" +SRC_ROOT="$(cd "$(dirname "$0")/.." && pwd)" +TS_DIR="$SRC_ROOT/gcc/testsuite" +STDCPP_LIB="$BUILD_DIR/x86_64-pc-linux-gnu/libstdc++-v3/src/.libs" + +XGCC="$BUILD_DIR/gcc/xgcc" +XGXX="$BUILD_DIR/gcc/xg++" + +if [[ ! -x "$XGCC" || ! -x "$XGXX" ]]; then + echo "error: xgcc/xg++ not found in $BUILD_DIR/gcc" + exit 3 +fi + +if [[ ! -d "$STDCPP_LIB" ]]; then + echo "error: libstdc++ build directory missing: $STDCPP_LIB" + echo "hint: run make all-target-libstdc++-v3 in build dir" + exit 4 +fi + +echo "[1/5] compile gcc.target/i386/arrowlake-1.c" +"$XGCC" -B"$BUILD_DIR/gcc/" -mabi=sysv -march=arrowlake \ + -c "$TS_DIR/gcc.target/i386/arrowlake-1.c" -o /tmp/arrowlake-1.o + +echo "[2/5] compile gcc.target/i386/arrowlake-2.c" +"$XGCC" -B"$BUILD_DIR/gcc/" -mabi=sysv -march=arrowlake-s \ + -c "$TS_DIR/gcc.target/i386/arrowlake-2.c" -o /tmp/arrowlake-2.o + +echo "[3/5] compile gcc.target/i386/arrowlake-3.c" +"$XGCC" -B"$BUILD_DIR/gcc/" -mabi=sysv -mtune=arrowlake-s -march=x86-64-v3 \ + -c "$TS_DIR/gcc.target/i386/arrowlake-3.c" -o /tmp/arrowlake-3.o + +echo "[4/5] run gcc.target/i386/builtin_target.c" +"$XGCC" -B"$BUILD_DIR/gcc/" -O2 \ + "$TS_DIR/gcc.target/i386/builtin_target.c" -o /tmp/builtin_target +/tmp/builtin_target + +echo "[5/5] run g++.target/i386/mv16.C" +"$XGXX" -B"$BUILD_DIR/gcc/" -O2 \ + "$TS_DIR/g++.target/i386/mv16.C" \ + -L"$STDCPP_LIB" -Wl,-rpath,"$STDCPP_LIB" \ + -o /tmp/mv16 +/tmp/mv16 + +echo "ALL PASS: Arrow Lake backport targeted verification succeeded" diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index a2e28e47a7d..f58eec5ffb1 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -606,6 +606,24 @@ get_intel_cpu (struct __processor_model *cpu_model, CHECK___builtin_cpu_is ("grandridge"); cpu_model->__cpu_type = INTEL_GRANDRIDGE; break; + case 0xb5: + case 0xc5: + /* Arrow Lake. */ + cpu = "arrowlake"; + CHECK___builtin_cpu_is ("corei7"); + CHECK___builtin_cpu_is ("arrowlake"); + cpu_model->__cpu_type = INTEL_COREI7; + cpu_model->__cpu_subtype = INTEL_COREI7_ARROWLAKE; + break; + case 0xc6: + case 0xbd: + /* Arrow Lake S / Lunar Lake. */ + cpu = "arrowlake-s"; + CHECK___builtin_cpu_is ("corei7"); + CHECK___builtin_cpu_is ("arrowlake-s"); + cpu_model->__cpu_type = INTEL_COREI7; + cpu_model->__cpu_subtype = INTEL_COREI7_ARROWLAKE_S; + break; case 0x17: case 0x1d: /* Penryn. */ @@ -899,6 +917,14 @@ get_available_features (struct __processor_model *cpu_model, set_feature (FEATURE_AVXVNNIINT8); if (edx & bit_AVXNECONVERT) set_feature (FEATURE_AVXNECONVERT); + if (edx & bit_AVXVNNIINT16) + set_feature (FEATURE_AVXVNNIINT16); + if (eax & bit_SM3) + set_feature (FEATURE_SM3); + if (eax & bit_SHA512) + set_feature (FEATURE_SHA512); + if (eax & bit_SM4) + set_feature (FEATURE_SM4); } if (avx512_usable) { diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index f3610155807..2a51fa01224 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -1967,6 +1967,8 @@ const char *const processor_names[] = "rocketlake", "graniterapids", "graniterapids-d", + "arrowlake", + "arrowlake-s", "intel", "lujiazui", "geode", @@ -2094,6 +2096,12 @@ const pta processor_alias_table[] = {"graniterapids-d", PROCESSOR_GRANITERAPIDS_D, CPU_HASWELL, PTA_GRANITERAPIDS_D, M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS_D), P_PROC_AVX512F}, + {"arrowlake", PROCESSOR_ARROWLAKE, CPU_HASWELL, PTA_ARROWLAKE, + M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE), P_PROC_AVX2}, + {"arrowlake-s", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S, + M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2}, + {"lunarlake", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S, + M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2}, {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL, M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3}, {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL, diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index 77db97e36b3..3bab4831cc4 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -100,6 +100,8 @@ enum processor_subtypes AMDFAM19H_ZNVER4, INTEL_COREI7_GRANITERAPIDS, INTEL_COREI7_GRANITERAPIDS_D, + INTEL_COREI7_ARROWLAKE, + INTEL_COREI7_ARROWLAKE_S, AMDFAM1AH_ZNVER5, CPU_SUBTYPE_MAX }; @@ -257,6 +259,10 @@ enum processor_features FEATURE_PREFETCHI, FEATURE_RAOINT, FEATURE_AMX_COMPLEX, + FEATURE_AVXVNNIINT16, + FEATURE_SM3, + FEATURE_SHA512, + FEATURE_SM4, CPU_FEATURE_MAX }; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index d4b0b23b417..2297903a45e 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -186,4 +186,9 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("raoint", FEATURE_RAOINT, P_NONE, "-mraoint") ISA_NAMES_TABLE_ENTRY("amx-complex", FEATURE_AMX_COMPLEX, P_NONE, "-mamx-complex") + ISA_NAMES_TABLE_ENTRY("avxvnniint16", FEATURE_AVXVNNIINT16, + P_NONE, "-mavxvnniint16") + ISA_NAMES_TABLE_ENTRY("sm3", FEATURE_SM3, P_NONE, "-msm3") + ISA_NAMES_TABLE_ENTRY("sha512", FEATURE_SHA512, P_NONE, "-msha512") + ISA_NAMES_TABLE_ENTRY("sm4", FEATURE_SM4, P_NONE, "-msm4") ISA_NAMES_TABLE_END diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index e1d6d2ff77c..cdccbb80ea6 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -143,6 +143,26 @@ #define bit_AMX_INT8 (1 << 25) #define bit_AMX_COMPLEX (1 << 8) +/* Extended Features Sub-leaf (%eax == 7, %ecx == 1) */ +/* %eax */ +#define bit_SHA512 (1 << 0) +#define bit_SM3 (1 << 1) +#define bit_SM4 (1 << 2) +#define bit_RAOINT (1 << 3) +#define bit_AVXVNNI (1 << 4) +#define bit_AVX512BF16 (1 << 5) +#define bit_CMPCCXADD (1 << 7) +#define bit_AMX_FP16 (1 << 21) +#define bit_HRESET (1 << 22) +#define bit_AVXIFMA (1 << 23) + +/* %edx */ +#define bit_AVXVNNIINT8 (1 << 4) +#define bit_AVXNECONVERT (1 << 5) +#define bit_AVXVNNIINT16 (1 << 10) +#define bit_PREFETCHI (1 << 14) +#define bit_USER_MSR (1 << 15) + /* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */ #define bit_XSAVEOPT (1 << 0) #define bit_XSAVEC (1 << 1) diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc index f4eee496924..544dfa3c296 100644 --- a/gcc/config/i386/driver-i386.cc +++ b/gcc/config/i386/driver-i386.cc @@ -599,9 +599,16 @@ const char *host_detect_local_cpu (int argc, const char **argv) /* Assume Granite Rapids. */ else if (has_feature (FEATURE_AMX_FP16)) cpu = "graniterapids"; + /* Assume Arrow Lake S / Lunar Lake. */ + else if (has_feature (FEATURE_SM3) + && has_feature (FEATURE_AVXVNNIINT16)) + cpu = "arrowlake-s"; /* Assume Sierra Forest. */ - else if (has_feature (FEATURE_AVXVNNIINT8)) + else if (has_feature (FEATURE_CLDEMOTE)) cpu = "sierraforest"; + /* Assume Arrow Lake. */ + else if (has_feature (FEATURE_AVXVNNIINT8)) + cpu = "arrowlake"; /* Assume Tiger Lake */ else if (has_feature (FEATURE_AVX512VP2INTERSECT)) cpu = "tigerlake"; diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index bbefb66e194..b5fd02be2c2 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -266,6 +266,14 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__graniterapids_d"); def_or_undef (parse_in, "__graniterapids_d__"); break; + case PROCESSOR_ARROWLAKE: + def_or_undef (parse_in, "__arrowlake"); + def_or_undef (parse_in, "__arrowlake__"); + break; + case PROCESSOR_ARROWLAKE_S: + def_or_undef (parse_in, "__arrowlake_s"); + def_or_undef (parse_in, "__arrowlake_s__"); + break; case PROCESSOR_ALDERLAKE: def_or_undef (parse_in, "__alderlake"); def_or_undef (parse_in, "__alderlake__"); @@ -461,6 +469,12 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, case PROCESSOR_GRANITERAPIDS_D: def_or_undef (parse_in, "__tune_graniterapids_d__"); break; + case PROCESSOR_ARROWLAKE: + def_or_undef (parse_in, "__tune_arrowlake__"); + break; + case PROCESSOR_ARROWLAKE_S: + def_or_undef (parse_in, "__tune_arrowlake_s__"); + break; case PROCESSOR_INTEL: case PROCESSOR_GENERIC: break; @@ -691,6 +705,14 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__RAOINT__"); if (isa_flag2 & OPTION_MASK_ISA2_AMX_COMPLEX) def_or_undef (parse_in, "__AMX_COMPLEX__"); + if (isa_flag2 & OPTION_MASK_ISA2_AVXVNNIINT16) + def_or_undef (parse_in, "__AVXVNNIINT16__"); + if (isa_flag2 & OPTION_MASK_ISA2_SM3) + def_or_undef (parse_in, "__SM3__"); + if (isa_flag2 & OPTION_MASK_ISA2_SHA512) + def_or_undef (parse_in, "__SHA512__"); + if (isa_flag2 & OPTION_MASK_ISA2_SM4) + def_or_undef (parse_in, "__SM4__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def index 0634c6f5bac..aeafcf870ac 100644 --- a/gcc/config/i386/i386-isa.def +++ b/gcc/config/i386/i386-isa.def @@ -117,3 +117,7 @@ DEF_PTA(AMX_FP16) DEF_PTA(PREFETCHI) DEF_PTA(RAOINT) DEF_PTA(AMX_COMPLEX) +DEF_PTA(AVXVNNIINT16) +DEF_PTA(SM3) +DEF_PTA(SHA512) +DEF_PTA(SM4) diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 368b98098a4..19fb641f69d 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -129,12 +129,15 @@ along with GCC; see the file COPYING3. If not see #define m_ROCKETLAKE (HOST_WIDE_INT_1U<<PROCESSOR_ROCKETLAKE) #define m_GRANITERAPIDS (HOST_WIDE_INT_1U<<PROCESSOR_GRANITERAPIDS) #define m_GRANITERAPIDS_D (HOST_WIDE_INT_1U<<PROCESSOR_GRANITERAPIDS_D) +#define m_ARROWLAKE (HOST_WIDE_INT_1U<<PROCESSOR_ARROWLAKE) +#define m_ARROWLAKE_S (HOST_WIDE_INT_1U<<PROCESSOR_ARROWLAKE_S) #define m_CORE_AVX512 (m_SKYLAKE_AVX512 | m_CANNONLAKE \ | m_ICELAKE_CLIENT | m_ICELAKE_SERVER | m_CASCADELAKE \ | m_TIGERLAKE | m_COOPERLAKE | m_SAPPHIRERAPIDS \ | m_ROCKETLAKE | m_GRANITERAPIDS | m_GRANITERAPIDS_D) #define m_CORE_AVX2 (m_HASWELL | m_SKYLAKE | m_CORE_AVX512) #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2) +#define m_CORE_HYBRID (m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S) #define m_GOLDMONT (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT) #define m_GOLDMONT_PLUS (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT_PLUS) #define m_TREMONT (HOST_WIDE_INT_1U<<PROCESSOR_TREMONT) @@ -775,6 +778,8 @@ static const struct processor_costs *processor_cost_table[] = &icelake_cost, &icelake_cost, &icelake_cost, + &alderlake_cost, + &alderlake_cost, &intel_cost, &lujiazui_cost, &geode_cost, diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index d147d373e8c..12bd1221758 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2258,6 +2258,8 @@ enum processor_type PROCESSOR_ROCKETLAKE, PROCESSOR_GRANITERAPIDS, PROCESSOR_GRANITERAPIDS_D, + PROCESSOR_ARROWLAKE, + PROCESSOR_ARROWLAKE_S, PROCESSOR_INTEL, PROCESSOR_LUJIAZUI, PROCESSOR_GEODE, @@ -2375,6 +2377,10 @@ constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS | PTA_AMX_FP16 constexpr wide_int_bitmask PTA_GRANITERAPIDS_D = PTA_GRANITERAPIDS | PTA_AMX_COMPLEX; constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST; +constexpr wide_int_bitmask PTA_ARROWLAKE = PTA_ALDERLAKE | PTA_AVXIFMA + | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD | PTA_UINTR; +constexpr wide_int_bitmask PTA_ARROWLAKE_S = PTA_ARROWLAKE | PTA_AVXVNNIINT16 + | PTA_SHA512 | PTA_SM3 | PTA_SM4; constexpr wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ; constexpr wide_int_bitmask PTA_ZNVER1 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 401acb20107..936d201c3b5 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1279,6 +1279,26 @@ mamx-complex Target Mask(ISA2_AMX_COMPLEX) Var(ix86_isa_flags2) Save Support AMX-COMPLEX built-in functions and code generation. +mavxvnniint16 +Target Mask(ISA2_AVXVNNIINT16) Var(ix86_isa_flags2) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and +AVXVNNIINT16 built-in functions and code generation. + +msm3 +Target Mask(ISA2_SM3) Var(ix86_isa_flags2) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and +SM3 built-in functions and code generation. + +msha512 +Target Mask(ISA2_SHA512) Var(ix86_isa_flags2) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and +SHA512 built-in functions and code generation. + +msm4 +Target Mask(ISA2_SM4) Var(ix86_isa_flags2) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and +SM4 built-in functions and code generation. + mgather Target Alias(mtune-ctrl=, use_gather, ^use_gather) Enable vectorization for gather instruction. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 0a90521d3d7..6c4c7dd0dc5 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -32576,6 +32576,24 @@ GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL and AVX-VNNI instruction set support. +@item arrowlake +Intel Arrow Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, +SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, +XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, +MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, +VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, UINTR, AVXIFMA, +AVXVNNIINT8, AVXNECONVERT and CMPCCXADD instruction set support. + +@item arrowlake-s +@itemx lunarlake +Intel Arrow Lake S/Lunar Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, +SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, +XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, +MOVDIRI, MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, +PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, UINTR, +AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3 and +SM4 instruction set support. + @item sapphirerapids @itemx emeraldrapids Intel Sapphire Rapids/Emerald Rapids CPU with 64-bit extensions, MMX, SSE, diff --git a/gcc/testsuite/g++.target/i386/mv16.C b/gcc/testsuite/g++.target/i386/mv16.C index 2158d58a94e..07f4a2a89df 100644 --- a/gcc/testsuite/g++.target/i386/mv16.C +++ b/gcc/testsuite/g++.target/i386/mv16.C @@ -108,6 +108,14 @@ int __attribute__ ((target("arch=graniterapids-d"))) foo () { return 28; } +int __attribute__ ((target("arch=arrowlake"))) foo () { + return 29; +} + +int __attribute__ ((target("arch=arrowlake-s"))) foo () { + return 30; +} + int main () { int val = foo (); @@ -154,6 +162,10 @@ int main () assert (val == 27); else if (__builtin_cpu_is ("graniterapids-d")) assert (val == 28); + else if (__builtin_cpu_is ("arrowlake")) + assert (val == 29); + else if (__builtin_cpu_is ("arrowlake-s")) + assert (val == 30); else assert (val == 0); diff --git a/gcc/testsuite/gcc.target/i386/arrowlake-1.c b/gcc/testsuite/gcc.target/i386/arrowlake-1.c new file mode 100644 index 00000000000..d6faeed40e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/arrowlake-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mabi=sysv -march=arrowlake" } */ + +/* Verify predefined macros and ISA bits for -march=arrowlake. */ + +#ifndef __arrowlake__ +# error __arrowlake__ is not defined +#endif + +#ifndef __tune_arrowlake__ +# error __tune_arrowlake__ is not defined +#endif + +#ifdef __arrowlake_s__ +# error __arrowlake_s__ is defined +#endif + +#ifndef __AVXIFMA__ +# error __AVXIFMA__ is not defined +#endif + +#ifdef __AVXVNNIINT16__ +# error __AVXVNNIINT16__ is defined +#endif diff --git a/gcc/testsuite/gcc.target/i386/arrowlake-2.c b/gcc/testsuite/gcc.target/i386/arrowlake-2.c new file mode 100644 index 00000000000..1850624b091 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/arrowlake-2.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mabi=sysv -march=arrowlake-s" } */ + +/* Verify predefined macros and ISA bits for -march=arrowlake-s. */ + +#ifndef __arrowlake_s__ +# error __arrowlake_s__ is not defined +#endif + +#ifndef __tune_arrowlake_s__ +# error __tune_arrowlake_s__ is not defined +#endif + +#ifdef __arrowlake__ +# error __arrowlake__ is defined +#endif + +#ifndef __AVXIFMA__ +# error __AVXIFMA__ is not defined +#endif + +#ifndef __AVXVNNIINT16__ +# error __AVXVNNIINT16__ is not defined +#endif + +#ifndef __SM3__ +# error __SM3__ is not defined +#endif + +#ifndef __SHA512__ +# error __SHA512__ is not defined +#endif + +#ifndef __SM4__ +# error __SM4__ is not defined +#endif diff --git a/gcc/testsuite/gcc.target/i386/arrowlake-3.c b/gcc/testsuite/gcc.target/i386/arrowlake-3.c new file mode 100644 index 00000000000..70598cdeb90 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/arrowlake-3.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mabi=sysv -mtune=arrowlake-s -march=x86-64-v3" } */ + +/* Check that tuning can be selected independently from architecture. */ + +#ifndef __tune_arrowlake_s__ +# error __tune_arrowlake_s__ is not defined +#endif + +#ifdef __arrowlake_s__ +# error __arrowlake_s__ is defined +#endif + +#ifdef __arrowlake__ +# error __arrowlake__ is defined +#endif diff --git a/gcc/testsuite/gcc.target/i386/builtin_target.c b/gcc/testsuite/gcc.target/i386/builtin_target.c index fff643c13b0..f5de262f324 100644 --- a/gcc/testsuite/gcc.target/i386/builtin_target.c +++ b/gcc/testsuite/gcc.target/i386/builtin_target.c @@ -95,6 +95,16 @@ quick_check () assert (__builtin_cpu_supports ("avx512vpopcntdq") >= 0); + assert (__builtin_cpu_supports ("avxifma") >= 0); + + assert (__builtin_cpu_supports ("avxvnniint16") >= 0); + + assert (__builtin_cpu_supports ("sm3") >= 0); + + assert (__builtin_cpu_supports ("sha512") >= 0); + + assert (__builtin_cpu_supports ("sm4") >= 0); + assert (__builtin_cpu_supports ("x86-64") >= 0); assert (__builtin_cpu_supports ("x86-64-v2") >= 0); assert (__builtin_cpu_supports ("x86-64-v3") >= 0); @@ -131,6 +141,10 @@ quick_check () assert (__builtin_cpu_is ("bdver2") >= 0); + assert (__builtin_cpu_is ("arrowlake") >= 0); + + assert (__builtin_cpu_is ("arrowlake-s") >= 0); + return 0; } -- 2.47.3
