To date, the aarch64 backend has been using the `size` iterator to denote the suffix letter of both [su]xt and ldr/str instructions. The value of this iterator for 32-bit modes is set to "w", which is correct for extends (uxtw/sxtw are valid mnemonics), but not for loads and stores (ldrw/strw do not exist). This hasn't caused a problem yet because the "ldr<size>" output string has never been used for 32-bit modes.
Some already existing variants of aarch64_combinez patterns, as well as more upcoming ones, as in [0], feature both ldr and uxt alternatives for some 32-bit modes (namely, V2BF and V2HF). To properly support that, we need two separate iterators, which would expand to "" and "w", respectively. This patch creates the `extsize` iterator which agrees with the values for `size` except for 32-bit modes, and updates all references to the latter in insn patterns as necessary. Bootstrapped and regtested on aarch64-linux-gnu. [0] https://gcc.gnu.org/pipermail/gcc-patches/2026-August/729125.html gcc/ChangeLog: * config/aarch64/aarch64.md (*extend<SHORT:mode><GPI:mode>2_aarch64): Use extsize instead of size. (*adds_<optab><ALLX:mode>_<GPI:mode>): Likewise. (*subs_<optab><ALLX:mode>_<GPI:mode>): Likewise. (*adds_<optab><ALLX:mode>_shift_<GPI:mode>): Likewise. (*subs_<optab><ALLX:mode>_shift_<GPI:mode>): Likewise. (*add_<optab><ALLX:mode>_<GPI:mode>): Likewise. (*add_<optab><SHORT:mode>_si_uxtw): Likewise. (*add_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise. (*add_<optab><SHORT:mode>_shft_si_uxtw): Likewise. (*sub_<optab><ALLX:mode>_<GPI:mode>): Likewise. (*sub_<optab><SHORT:mode>_si_uxtw): Likewise. (*sub_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise. (*sub_<optab><SHORT:mode>_shft_si_uxtw): Likewise. (*cmp_swp_<optab><ALLX:mode>_reg<GPI:mode>): Likewise. (*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise. * config/aarch64/aarch64-simd.md (*aarch64_combinez<mode>): Likewise. (*aarch64_combinez_be<mode>): Likewise. * config/aarch64/atomics.md (*aarch64_atomic_load<ALLX:mode>_rcpc_sext): Likewise. * config/aarch64/iterators.md (size): Yield empty string for SI. (extsize): New iterator. --- gcc/config/aarch64/aarch64-simd.md | 4 ++-- gcc/config/aarch64/aarch64.md | 32 +++++++++++++++--------------- gcc/config/aarch64/atomics.md | 2 +- gcc/config/aarch64/iterators.md | 9 +++++++-- 4 files changed, 26 insertions(+), 21 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index f9b2fd6b2db..12dcabb7a15 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -5099,7 +5099,7 @@ (match_operand:VSSUB32_I 2 "aarch64_simd_or_scalar_imm_zero")))] "TARGET_FLOAT && !BYTES_BIG_ENDIAN" {@ [ cons: =0 , 1 ; attrs: type ] - [ r , r ; mov_reg ] uxt<size>\t%w0, %w1 + [ r , r ; mov_reg ] uxt<extsize>\t%w0, %w1 [ r , m ; load_4 ] ldr<size>\t%<single_wx>0, %1 } ) @@ -5139,7 +5139,7 @@ (match_operand:VSSUB32_I 1 "nonimmediate_operand")))] "TARGET_FLOAT && BYTES_BIG_ENDIAN" {@ [ cons: =0 , 1 ; attrs: type ] - [ r , r ; mov_reg ] uxt<size>\t%w0, %w1 + [ r , r ; mov_reg ] uxt<extsize>\t%w0, %w1 [ r , m ; load_4 ] ldr<size>\t%<single_wx>0, %1 } ) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 3f304c79366..4ae5c074cd1 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2667,8 +2667,8 @@ (sign_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand")))] "" {@ [ cons: =0 , 1 ; attrs: type , arch ] - [ r , r ; extend , * ] sxt<SHORT:size>\t%<GPI:w>0, %w1 - [ r , m ; load_4 , * ] ldrs<SHORT:size>\t%<GPI:w>0, %1 + [ r , r ; extend , * ] sxt<SHORT:extsize>\t%<GPI:w>0, %w1 + [ r , m ; load_4 , * ] ldrs<SHORT:extsize>\t%<GPI:w>0, %1 [ r , w ; neon_to_gp , fp ] smov\t%<GPI:w>0, %1.<SHORT:size>[0] } ) @@ -3192,7 +3192,7 @@ (set (match_operand:GPI 0 "register_operand" "=r") (plus:GPI (ANY_EXTEND:GPI (match_dup 1)) (match_dup 2)))] "" - "adds\\t%<GPI:w>0, %<GPI:w>2, %w1, <su>xt<ALLX:size>" + "adds\\t%<GPI:w>0, %<GPI:w>2, %w1, <su>xt<ALLX:extsize>" [(set_attr "type" "alus_ext")] ) @@ -3206,7 +3206,7 @@ (set (match_operand:GPI 0 "register_operand" "=r") (minus:GPI (match_dup 1) (ANY_EXTEND:GPI (match_dup 2))))] "" - "subs\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:size>" + "subs\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:extsize>" [(set_attr "type" "alus_ext")] ) @@ -3224,7 +3224,7 @@ (match_dup 2)) (match_dup 3)))] "" - "adds\\t%<GPI:w>0, %<GPI:w>3, %w1, <su>xt<ALLX:size> %2" + "adds\\t%<GPI:w>0, %<GPI:w>3, %w1, <su>xt<ALLX:extsize> %2" [(set_attr "type" "alus_ext")] ) @@ -3242,7 +3242,7 @@ (ashift:GPI (ANY_EXTEND:GPI (match_dup 2)) (match_dup 3))))] "" - "subs\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:size> %3" + "subs\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:extsize> %3" [(set_attr "type" "alus_ext")] ) @@ -3308,7 +3308,7 @@ (plus:GPI (ANY_EXTEND:GPI (match_operand:ALLX 1 "register_operand" "r")) (match_operand:GPI 2 "register_operand" "r")))] "" - "add\\t%<GPI:w>0, %<GPI:w>2, %w1, <su>xt<ALLX:size>" + "add\\t%<GPI:w>0, %<GPI:w>2, %w1, <su>xt<ALLX:extsize>" [(set_attr "type" "alu_ext")] ) @@ -3319,7 +3319,7 @@ (plus:SI (ANY_EXTEND:SI (match_operand:SHORT 1 "register_operand" "r")) (match_operand:GPI 2 "register_operand" "r"))))] "" - "add\\t%w0, %w2, %w1, <su>xt<SHORT:size>" + "add\\t%w0, %w2, %w1, <su>xt<SHORT:extsize>" [(set_attr "type" "alu_ext")] ) @@ -3330,7 +3330,7 @@ (match_operand 2 "aarch64_imm3" "Ui3")) (match_operand:GPI 3 "register_operand" "r")))] "" - "add\\t%<GPI:w>0, %<GPI:w>3, %w1, <su>xt<ALLX:size> %2" + "add\\t%<GPI:w>0, %<GPI:w>3, %w1, <su>xt<ALLX:extsize> %2" [(set_attr "type" "alu_ext")] ) @@ -3343,7 +3343,7 @@ (match_operand 2 "aarch64_imm3" "Ui3")) (match_operand:SI 3 "register_operand" "r"))))] "" - "add\\t%w0, %w3, %w1, <su>xt<SHORT:size> %2" + "add\\t%w0, %w3, %w1, <su>xt<SHORT:extsize> %2" [(set_attr "type" "alu_ext")] ) @@ -3959,7 +3959,7 @@ (ANY_EXTEND:GPI (match_operand:ALLX 2 "register_operand" "r"))))] "" - "sub\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:size>" + "sub\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:extsize>" [(set_attr "type" "alu_ext")] ) @@ -3971,7 +3971,7 @@ (ANY_EXTEND:SI (match_operand:SHORT 2 "register_operand" "r")))))] "" - "sub\\t%w0, %w1, %w2, <su>xt<SHORT:size>" + "sub\\t%w0, %w1, %w2, <su>xt<SHORT:extsize>" [(set_attr "type" "alu_ext")] ) @@ -3982,7 +3982,7 @@ (match_operand:ALLX 2 "register_operand" "r")) (match_operand 3 "aarch64_imm3" "Ui3"))))] "" - "sub\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:size> %3" + "sub\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:extsize> %3" [(set_attr "type" "alu_ext")] ) @@ -3995,7 +3995,7 @@ (match_operand:SHORT 2 "register_operand" "r")) (match_operand 3 "aarch64_imm3" "Ui3")))))] "" - "sub\\t%w0, %w1, %w2, <su>xt<SHORT:size> %3" + "sub\\t%w0, %w1, %w2, <su>xt<SHORT:extsize> %3" [(set_attr "type" "alu_ext")] ) @@ -4714,7 +4714,7 @@ (match_operand:ALLX 0 "register_operand" "r")) (match_operand:GPI 1 "register_operand" "r")))] "" - "cmp\\t%<GPI:w>1, %w0, <su>xt<ALLX:size>" + "cmp\\t%<GPI:w>1, %w0, <su>xt<ALLX:extsize>" [(set_attr "type" "alus_ext")] ) @@ -4726,7 +4726,7 @@ (match_operand 1 "aarch64_imm3" "Ui3")) (match_operand:GPI 2 "register_operand" "r")))] "" - "cmp\\t%<GPI:w>2, %w0, <su>xt<ALLX:size> %1" + "cmp\\t%<GPI:w>2, %w0, <su>xt<ALLX:extsize> %1" [(set_attr "type" "alus_ext")] ) diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index c9534d43c0f..2316fea8135 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -729,7 +729,7 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPECV_LDAP)))] "TARGET_RCPC2 && (<GPI:sizen> > <ALLX:sizen>)" - "ldapurs<ALLX:size>\t%<GPI:w>0, %1" + "ldapurs<ALLX:extsize>\t%<GPI:w>0, %1" ) (define_insn "atomic_store<mode>" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 7b7c2bc34e5..a56edb8ebf4 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1577,11 +1577,16 @@ ;; Map a floating point or integer mode to the appropriate register name prefix (define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")]) -;; Give the length suffix letter for a sign- or zero-extension. -(define_mode_attr size [(QI "b") (HI "h") (SI "w") (HF "") (BF "") (SF "") +;; Give the length suffix letter for a load/store operation. +(define_mode_attr size [(QI "b") (HI "h") (SI "") (HF "h") (BF "h") (SF "") (V2QI "h") (V4QI "") (V2HI "") (V2HF "") (V2BF "")]) +;; Give the length suffix letter for a sign- or zero-extension. +(define_mode_attr extsize [(QI "b") (HI "h") (SI "w") (HF "h") (BF "h") (SF "w") + (V2QI "h") (V4QI "w") (V2HI "w") + (V2HF "w") (V2BF "w")]) + ;; Give the number of bits in the mode (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) (define_mode_attr ZEROM [(QI "SI") (HI "SI") (SI "SI") (DI "DI")]) -- 2.43.0
