Re: [PATCH] xtensa: Discourage use of hardware FP registers for SFmode load/store

[Max Filippov]

On Mon, Sep 7, 2026 at 7:07 AM Takayuki 'January June' Suwa
<jjsuwa_sys3...@yahoo.co.jp> wrote:
>
> In the Xtensa ISA, using either address (general-purpose) registers or
> hardware floating-point registers for loading or storing single-precision
> floating-point values results in no difference in semantics or speed;
> however, the former is advantageous in terms of code size when the Code
> Density Option is configured.
>
> This patch lowers the priority of H/W FP registers for SFmode load/store
> operations by prefixing the register constraints with '*' in the alternative
> specifications within the MD insn definition.
>
>      /* example */
>      extern float b;
>      void test0(int a) {
>        b = a ? b : 0;
>      }
>      void test1(int a) {
>        b = a ? b : 1;
>      }
>
>      ;; before (-O2 ; TARGET_HARD_FLOAT | TARGET_DENSITY)
>         .literal_position
>         .literal .LC0, b
>      test0:
>         entry   sp, 32
>         l32r    a8, .LC0
>         beqz.n  a2, .L3
>         lsi     f0, a8, 0       ;; load to FPR
>         j       .L2
>      .L3:
>         const.s f0, 0           ;; set +0.f to FPR
>      .L2:
>         ssi     f0, a8, 0       ;; store from FPR
>         retw.n
>         .literal_position
>         .literal .LC1, b
>      test1:
>         entry   sp, 32
>         l32r    a8, .LC1
>         beqz.n  a2, .L7
>         lsi     f0, a8, 0       ;; load to FPR
>         j       .L6
>      .L7:
>         const.s f0, 1           ;; set 1.f to FPR
>      .L6:
>         ssi     f0, a8, 0       ;; store from FPR
>         retw.n
>
>      ;; after (-O2 ; TARGET_HARD_FLOAT | TARGET_DENSITY)
>         .literal_position
>         .literal .LC0, b
>      test0:
>         entry   sp, 32
>         l32r    a8, .LC0
>         beqz.n  a2, .L3
>         l32i.n  a9, a8, 0       ;; load to GPR (1 byte shorter)
>         j       .L2
>      .L3:
>         movi.n  a9, 0           ;; set +0.f to GPR (1 byte shorter)
>      .L2:
>         s32i.n  a9, a8, 0       ;; store from GPR (1 byte shorter)
>         retw.n
>         .literal_position
>         .literal .LC1, b
>      test1:
>         entry   sp, 32
>         l32r    a8, .LC1
>         beqz.n  a2, .L7
>         lsi     f0, a8, 0       ;; load to FPR (no changes)
>         j       .L6
>      .L7:
>         const.s f0, 1           ;; set 1.f to FPR (no changes)
>                                 ;; Since this instruction constrains the
>                                 ;; regclass, the lowered priority of FPR
>                                 ;; is not taken into account.
>      .L6:
>         ssi     f0, a8, 0       ;; store from FPR (no changes)
>         retw.n
>
> gcc/ChangeLog:
>
>         * config/xtensa/xtensa.md (movsf_internal):
>         Prefix register constraints with '*' for hardware FP register load
>         and store alternatives.
> ---
>   gcc/config/xtensa/xtensa.md | 34 +++++++++++++++++-----------------
>   1 file changed, 17 insertions(+), 17 deletions(-)

Regtested for target=xtensa-linux-uclibc, no new regressions.
Committed to master.

-- 
Thanks.
-- Max