On 19/08/2026 10:20, Claudio Bantaloukas wrote:
> Unlike other aarch64_immx predicates that allow using all bits available,
> aarch64_imm3 was only allowing values up to 4. Since the predicate is only
> being
> used in extended register versions of add, adds etc to denote a shift amount,
> it is best renamed to aarch64_shift_imm3.
> The aarch64_lane_imm3 is being renamed to aarch64_imm3.
OK, thanks.
Alex
>
> gcc/
> * config/aarch64/aarch64.md: Rename aarch64_imm3 as aarch64_shift_imm3.
> * config/aarch64/aarch64-simd.md: Rename aarch64_lane_imm3 as
> aarch64_imm3.
> * config/aarch64/predicates.md: Rename aarch64_imm3 as
> aarch64_shift_imm3
> and aarch64_lane_imm3 to aarch64_imm3.
> ---
> gcc/config/aarch64/aarch64-simd.md | 24 ++++++++++++------------
> gcc/config/aarch64/aarch64.md | 22 +++++++++++-----------
> gcc/config/aarch64/predicates.md | 6 +++---
> 3 files changed, 26 insertions(+), 26 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64-simd.md
> b/gcc/config/aarch64/aarch64-simd.md
> index e6fe3bd9627..da88190f09c 100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -10314,7 +10314,7 @@ (define_expand "aarch64_fml<f16mac1>lq_laneq_lowv4sf"
> (unspec:V4SF [(match_operand:V4SF 1 "register_operand")
> (match_operand:V8HF 2 "register_operand")
> (match_operand:V8HF 3 "register_operand")
> - (match_operand:SI 4 "aarch64_lane_imm3")]
> + (match_operand:SI 4 "aarch64_imm3")]
> VFMLA16_LOW))]
> "TARGET_F16FML"
> {
> @@ -10334,7 +10334,7 @@ (define_expand "aarch64_fml<f16mac1>lq_laneq_highv4sf"
> (unspec:V4SF [(match_operand:V4SF 1 "register_operand")
> (match_operand:V8HF 2 "register_operand")
> (match_operand:V8HF 3 "register_operand")
> - (match_operand:SI 4 "aarch64_lane_imm3")]
> + (match_operand:SI 4 "aarch64_imm3")]
> VFMLA16_HIGH))]
> "TARGET_F16FML"
> {
> @@ -10360,7 +10360,7 @@ (define_insn "aarch64_simd_fmlalq_laneq_lowv4sf"
> (vec_duplicate:V4HF
> (vec_select:HF
> (match_operand:V8HF 3 "register_operand" "x")
> - (parallel [(match_operand:SI 5 "aarch64_lane_imm3" "Ui7")]))))
> + (parallel [(match_operand:SI 5 "aarch64_imm3" "Ui7")]))))
> (match_operand:V4SF 1 "register_operand" "0")))]
> "TARGET_F16FML"
> "fmlal\\t%0.4s, %2.4h, %3.h[%5]"
> @@ -10379,7 +10379,7 @@ (define_insn "aarch64_simd_fmlslq_laneq_lowv4sf"
> (vec_duplicate:V4HF
> (vec_select:HF
> (match_operand:V8HF 3 "register_operand" "x")
> - (parallel [(match_operand:SI 5 "aarch64_lane_imm3" "Ui7")]))))
> + (parallel [(match_operand:SI 5 "aarch64_imm3" "Ui7")]))))
> (match_operand:V4SF 1 "register_operand" "0")))]
> "TARGET_F16FML"
> "fmlsl\\t%0.4s, %2.4h, %3.h[%5]"
> @@ -10397,7 +10397,7 @@ (define_insn "aarch64_simd_fmlalq_laneq_highv4sf"
> (vec_duplicate:V4HF
> (vec_select:HF
> (match_operand:V8HF 3 "register_operand" "x")
> - (parallel [(match_operand:SI 5 "aarch64_lane_imm3" "Ui7")]))))
> + (parallel [(match_operand:SI 5 "aarch64_imm3" "Ui7")]))))
> (match_operand:V4SF 1 "register_operand" "0")))]
> "TARGET_F16FML"
> "fmlal2\\t%0.4s, %2.4h, %3.h[%5]"
> @@ -10416,7 +10416,7 @@ (define_insn "aarch64_simd_fmlslq_laneq_highv4sf"
> (vec_duplicate:V4HF
> (vec_select:HF
> (match_operand:V8HF 3 "register_operand" "x")
> - (parallel [(match_operand:SI 5 "aarch64_lane_imm3" "Ui7")]))))
> + (parallel [(match_operand:SI 5 "aarch64_imm3" "Ui7")]))))
> (match_operand:V4SF 1 "register_operand" "0")))]
> "TARGET_F16FML"
> "fmlsl2\\t%0.4s, %2.4h, %3.h[%5]"
> @@ -10428,7 +10428,7 @@ (define_expand "aarch64_fml<f16mac1>l_laneq_lowv2sf"
> (unspec:V2SF [(match_operand:V2SF 1 "register_operand")
> (match_operand:V4HF 2 "register_operand")
> (match_operand:V8HF 3 "register_operand")
> - (match_operand:SI 4 "aarch64_lane_imm3")]
> + (match_operand:SI 4 "aarch64_imm3")]
> VFMLA16_LOW))]
> "TARGET_F16FML"
> {
> @@ -10449,7 +10449,7 @@ (define_expand "aarch64_fml<f16mac1>l_laneq_highv2sf"
> (unspec:V2SF [(match_operand:V2SF 1 "register_operand")
> (match_operand:V4HF 2 "register_operand")
> (match_operand:V8HF 3 "register_operand")
> - (match_operand:SI 4 "aarch64_lane_imm3")]
> + (match_operand:SI 4 "aarch64_imm3")]
> VFMLA16_HIGH))]
> "TARGET_F16FML"
> {
> @@ -10476,7 +10476,7 @@ (define_insn "aarch64_simd_fmlal_laneq_lowv2sf"
> (vec_duplicate:V2HF
> (vec_select:HF
> (match_operand:V8HF 3 "register_operand" "x")
> - (parallel [(match_operand:SI 5 "aarch64_lane_imm3" "Ui7")]))))
> + (parallel [(match_operand:SI 5 "aarch64_imm3" "Ui7")]))))
> (match_operand:V2SF 1 "register_operand" "0")))]
> "TARGET_F16FML"
> "fmlal\\t%0.2s, %2.2h, %3.h[%5]"
> @@ -10495,7 +10495,7 @@ (define_insn "aarch64_simd_fmlsl_laneq_lowv2sf"
> (vec_duplicate:V2HF
> (vec_select:HF
> (match_operand:V8HF 3 "register_operand" "x")
> - (parallel [(match_operand:SI 5 "aarch64_lane_imm3" "Ui7")]))))
> + (parallel [(match_operand:SI 5 "aarch64_imm3" "Ui7")]))))
> (match_operand:V2SF 1 "register_operand" "0")))]
> "TARGET_F16FML"
> "fmlsl\\t%0.2s, %2.2h, %3.h[%5]"
> @@ -10513,7 +10513,7 @@ (define_insn "aarch64_simd_fmlal_laneq_highv2sf"
> (vec_duplicate:V2HF
> (vec_select:HF
> (match_operand:V8HF 3 "register_operand" "x")
> - (parallel [(match_operand:SI 5 "aarch64_lane_imm3" "Ui7")]))))
> + (parallel [(match_operand:SI 5 "aarch64_imm3" "Ui7")]))))
> (match_operand:V2SF 1 "register_operand" "0")))]
> "TARGET_F16FML"
> "fmlal2\\t%0.2s, %2.2h, %3.h[%5]"
> @@ -10532,7 +10532,7 @@ (define_insn "aarch64_simd_fmlsl_laneq_highv2sf"
> (vec_duplicate:V2HF
> (vec_select:HF
> (match_operand:V8HF 3 "register_operand" "x")
> - (parallel [(match_operand:SI 5 "aarch64_lane_imm3" "Ui7")]))))
> + (parallel [(match_operand:SI 5 "aarch64_imm3" "Ui7")]))))
> (match_operand:V2SF 1 "register_operand" "0")))]
> "TARGET_F16FML"
> "fmlsl2\\t%0.2s, %2.2h, %3.h[%5]"
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 9cb55602c36..e27d5b181ee 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -3170,7 +3170,7 @@ (define_insn "*adds_<optab><ALLX:mode>_shift_<GPI:mode>"
> (plus:GPI (ashift:GPI
> (ANY_EXTEND:GPI
> (match_operand:ALLX 1 "register_operand" "r"))
> - (match_operand 2 "aarch64_imm3" "Ui3"))
> + (match_operand 2 "aarch64_shift_imm3" "Ui3"))
> (match_operand:GPI 3 "register_operand" "rk"))
> (const_int 0)))
> (set (match_operand:GPI 0 "register_operand" "=rk")
> @@ -3189,7 +3189,7 @@ (define_insn "*subs_<optab><ALLX:mode>_shift_<GPI:mode>"
> (ashift:GPI
> (ANY_EXTEND:GPI
> (match_operand:ALLX 2 "register_operand" "r"))
> - (match_operand 3 "aarch64_imm3" "Ui3")))
> + (match_operand 3 "aarch64_shift_imm3" "Ui3")))
> (const_int 0)))
> (set (match_operand:GPI 0 "register_operand" "=rk")
> (minus:GPI (match_dup 1)
> @@ -3281,7 +3281,7 @@ (define_insn "*add_<optab><ALLX:mode>_shft_<GPI:mode>"
> [(set (match_operand:GPI 0 "register_operand" "=rk")
> (plus:GPI (ashift:GPI (ANY_EXTEND:GPI
> (match_operand:ALLX 1 "register_operand" "r"))
> - (match_operand 2 "aarch64_imm3" "Ui3"))
> + (match_operand 2 "aarch64_shift_imm3" "Ui3"))
> (match_operand:GPI 3 "register_operand" "r")))]
> ""
> "add\\t%<GPI:w>0, %<GPI:w>3, %w1, <su>xt<ALLX:size> %2"
> @@ -3294,7 +3294,7 @@ (define_insn "*add_<optab><SHORT:mode>_shft_si_uxtw"
> (zero_extend:DI
> (plus:SI (ashift:SI (ANY_EXTEND:SI
> (match_operand:SHORT 1 "register_operand" "r"))
> - (match_operand 2 "aarch64_imm3" "Ui3"))
> + (match_operand 2 "aarch64_shift_imm3" "Ui3"))
> (match_operand:SI 3 "register_operand" "r"))))]
> ""
> "add\\t%w0, %w3, %w1, <su>xt<SHORT:size> %2"
> @@ -3474,7 +3474,7 @@ (define_insn "*add_uxt<mode>_shift2"
> [(set (match_operand:GPI 0 "register_operand" "=rk")
> (plus:GPI (and:GPI
> (ashift:GPI (match_operand:GPI 1 "register_operand" "r")
> - (match_operand 2 "aarch64_imm3" "Ui3"))
> + (match_operand 2 "aarch64_shift_imm3" "Ui3"))
> (match_operand 3 "const_int_operand" "n"))
> (match_operand:GPI 4 "register_operand" "r")))]
> "aarch64_uxt_size (INTVAL (operands[2]), INTVAL (operands[3])) != 0"
> @@ -3491,7 +3491,7 @@ (define_insn "*add_uxtsi_shift2_uxtw"
> (zero_extend:DI
> (plus:SI (and:SI
> (ashift:SI (match_operand:SI 1 "register_operand" "r")
> - (match_operand 2 "aarch64_imm3" "Ui3"))
> + (match_operand 2 "aarch64_shift_imm3" "Ui3"))
> (match_operand 3 "const_int_operand" "n"))
> (match_operand:SI 4 "register_operand" "r"))))]
> "aarch64_uxt_size (INTVAL (operands[2]), INTVAL (operands[3])) != 0"
> @@ -3934,7 +3934,7 @@ (define_insn "*sub_<optab><ALLX:mode>_shft_<GPI:mode>"
> (minus:GPI (match_operand:GPI 1 "register_operand" "rk")
> (ashift:GPI (ANY_EXTEND:GPI
> (match_operand:ALLX 2 "register_operand" "r"))
> - (match_operand 3 "aarch64_imm3" "Ui3"))))]
> + (match_operand 3 "aarch64_shift_imm3" "Ui3"))))]
> ""
> "sub\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:size> %3"
> [(set_attr "type" "alu_ext")]
> @@ -3947,7 +3947,7 @@ (define_insn "*sub_<optab><SHORT:mode>_shft_si_uxtw"
> (minus:SI (match_operand:SI 1 "register_operand" "rk")
> (ashift:SI (ANY_EXTEND:SI
> (match_operand:SHORT 2 "register_operand" "r"))
> - (match_operand 3 "aarch64_imm3" "Ui3")))))]
> + (match_operand 3 "aarch64_shift_imm3" "Ui3")))))]
> ""
> "sub\\t%w0, %w1, %w2, <su>xt<SHORT:size> %3"
> [(set_attr "type" "alu_ext")]
> @@ -4181,7 +4181,7 @@ (define_insn "*sub_uxt<mode>_shift2"
> (minus:GPI (match_operand:GPI 4 "register_operand" "rk")
> (and:GPI
> (ashift:GPI (match_operand:GPI 1 "register_operand" "r")
> - (match_operand 2 "aarch64_imm3" "Ui3"))
> + (match_operand 2 "aarch64_shift_imm3" "Ui3"))
> (match_operand 3 "const_int_operand" "n"))))]
> "aarch64_uxt_size (INTVAL (operands[2]),INTVAL (operands[3])) != 0"
> "*
> @@ -4198,7 +4198,7 @@ (define_insn "*sub_uxtsi_shift2_uxtw"
> (minus:SI (match_operand:SI 4 "register_operand" "rk")
> (and:SI
> (ashift:SI (match_operand:SI 1 "register_operand" "r")
> - (match_operand 2 "aarch64_imm3" "Ui3"))
> + (match_operand 2 "aarch64_shift_imm3" "Ui3"))
> (match_operand 3 "const_int_operand" "n")))))]
> "aarch64_uxt_size (INTVAL (operands[2]),INTVAL (operands[3])) != 0"
> "*
> @@ -4677,7 +4677,7 @@ (define_insn
> "*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>"
> (compare:CC_SWP (ashift:GPI
> (ANY_EXTEND:GPI
> (match_operand:ALLX 0 "register_operand" "r"))
> - (match_operand 1 "aarch64_imm3" "Ui3"))
> + (match_operand 1 "aarch64_shift_imm3" "Ui3"))
> (match_operand:GPI 2 "register_operand" "r")))]
> ""
> "cmp\\t%<GPI:w>2, %w0, <su>xt<ALLX:size> %1"
> diff --git a/gcc/config/aarch64/predicates.md
> b/gcc/config/aarch64/predicates.md
> index 9d2613a9aee..6cd809cd615 100644
> --- a/gcc/config/aarch64/predicates.md
> +++ b/gcc/config/aarch64/predicates.md
> @@ -280,9 +280,9 @@ (define_predicate "aarch64_reg_or_shift_imm_di"
> (ior (match_operand 0 "register_operand")
> (match_operand 0 "aarch64_shift_imm_di")))
>
> -;; The imm3 field is a 3-bit field that only accepts immediates in the
> +;; The aarch64_shift_imm3 field is a 3-bit field that only accepts
> immediates in the
> ;; range 0..4.
> -(define_predicate "aarch64_imm3"
> +(define_predicate "aarch64_shift_imm3"
> (and (match_code "const_int")
> (match_test "UINTVAL (op) <= 4")))
>
> @@ -294,7 +294,7 @@ (define_predicate "aarch64_imm2"
>
> ;; The imm3 field is a 3-bit field that only accepts immediates in the
> ;; range 0..7.
> -(define_predicate "aarch64_lane_imm3"
> +(define_predicate "aarch64_imm3"
> (and (match_code "const_int")
> (match_test "UINTVAL (op) <= 7")))
>
> --
> 2.47.3
>
