[PATCH] aarch64: Set REGMODE_NATURAL_SIZE for advsimd vectors.

[Robin Dapp]

Hi,

Here now the split-out version after the middle-end and riscv changes 
have already been installed:

Similar to the riscv changes, this patch adjusts aarch64's
REGMODE_NATURAL_SIZE so it returns the size of one vector.
Subsequently, subregs of vectors smaller than a vector are invalid.

Bootstrapped and regtested on aarch64.

Regards
 Robin

---
 gcc/config/aarch64/aarch64.cc | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 5544d5f8c7a..71d8ab438b7 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -2996,20 +2996,19 @@ aarch64_regmode_natural_size (machine_mode mode)
   /* The natural size for SVE data modes is one SVE data vector,
      and similarly for predicates.  We can't independently modify
      anything smaller than that.  */
-  /* ??? For now, only do this for variable-width SVE registers.
-     Doing it for constant-sized registers breaks lower-subreg.cc.  */
-  /* ??? And once that's fixed, we should probably have similar
-     code for Advanced SIMD.  */
-  if (!aarch64_sve_vg.is_constant ())
-    {
-      /* REGMODE_NATURAL_SIZE influences general subreg validity rules,
-        so we need to handle memory-only modes as well.  */
+  if (VECTOR_MODE_P (mode))
+    {
       unsigned int vec_flags = aarch64_classify_vector_memory_mode (mode);
       if (vec_flags & VEC_SVE_PRED)
        return BYTES_PER_SVE_PRED;
       if (vec_flags & VEC_SVE_DATA)
        return BYTES_PER_SVE_VECTOR;
+      if (vec_flags & VEC_ADVSIMD)
+       return MAX (exact_div (GET_MODE_SIZE (mode),
+                              aarch64_ldn_stn_vectors (mode)).to_constant (),
+                   UNITS_PER_WORD);
     }
+
   return UNITS_PER_WORD;
 }
 
-- 
2.55.0