From: Stefan Schulze Frielinghaus <[email protected]>
Initially asm-hard-reg-2.c was intended to be considered only on 64-bit
x86. Commit r16-3110 changed this by adding i?86-*-* to the target
selector but does not add a definition for GPR which renders those tests
to fail for i?86-*-*. My intention to not include 32-bit targets was
due to the usage of long long integer types for GPR operands. @H.J. Lu,
can you elaborate on that commit? Was adding i?86-*-* really intended?
If so a #define GPR is needed for the target.
Test asm-hard-reg-5.c fails on powerpc64-*-* since option -maltivec is
missing.
Test asm-hard-reg-6.c is failing for ARM Thumb-2 e.g. if options -mthumb
-march=armv8.1-m.main+mve.fp+fp.dp -mtune=cortex-m55 -mfloat-abi=hard
-mfpu=auto are used. In that case GPR pairs must be in even/odd pairs in
contrast to Thumb-1. Fix this by changing GPR3 to r4.
I still see test failures on gcc-testresults for
- aarch64-apple-darwin27 and asm-hard-reg-error-2.c
- i386-pc-solaris2.11 and asm-hard-reg-1.c
- i686-apple-darwin{9,17} and asm-hard-reg-1.c
- ia64-t2-linux-gnu and asm-hard-reg-error-{4,5,6}.c
- x86_64-apple-darwin25 and gcc.target/i386/asm-hard-reg-2.c
which I couldn't investigate due to lack of access.
---
gcc/testsuite/gcc.dg/asm-hard-reg-5.c | 3 ++-
gcc/testsuite/gcc.dg/asm-hard-reg-6.c | 4 ++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-5.c
b/gcc/testsuite/gcc.dg/asm-hard-reg-5.c
index ea7907ae2a0..930c5b8039f 100644
--- a/gcc/testsuite/gcc.dg/asm-hard-reg-5.c
+++ b/gcc/testsuite/gcc.dg/asm-hard-reg-5.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { { aarch64*-*-* powerpc64*-*-* riscv64-*-*
s390*-*-* } || { { i?86-*-* x86_64-*-* } && { ! ia32 } } } } } */
+/* { dg-do compile { target { { aarch64*-*-* riscv64-*-* s390*-*-* } || { {
powerpc64*-*-* && powerpc_altivec_ok } || { x86_64-*-* && { ! ia32 } } } } } }
*/
typedef int V __attribute__ ((vector_size (4 * sizeof (int))));
@@ -7,6 +7,7 @@ typedef int V __attribute__ ((vector_size (4 * sizeof (int))));
/* { dg-final { scan-assembler-times "foo\tv20" 2 { target { aarch64*-*-* } }
} } */
#elif defined (__powerpc__) || defined (__POWERPC__)
# define VR "{v5}"
+/* { dg-additional-options "-maltivec" { target { powerpc64*-*-* } } } */
/* { dg-final { scan-assembler-times "foo\t5" 2 { target { powerpc64*-*-* } }
} } */
#elif defined (__riscv)
# define VR "{v5}"
diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-6.c
b/gcc/testsuite/gcc.dg/asm-hard-reg-6.c
index 37d15a6ed5c..5c1f8371897 100644
--- a/gcc/testsuite/gcc.dg/asm-hard-reg-6.c
+++ b/gcc/testsuite/gcc.dg/asm-hard-reg-6.c
@@ -12,8 +12,8 @@
#elif defined (__arm__)
# define GPR1 "{r1}"
# define GPR2 "{r2}"
-# define GPR3 "{r3}"
-/* { dg-final { scan-assembler-times "foo\tr1,r3" 1 { target { arm*-*-* } } }
} */
+# define GPR3 "{r4}"
+/* { dg-final { scan-assembler-times "foo\tr1,r4" 1 { target { arm*-*-* } } }
} */
/* { dg-final { scan-assembler-times "bar\tr2,\\\[r1\\\]" 1 { target {
arm*-*-* } } } } */
#elif defined (__i386__)
# define GPR1 "{eax}"
--
2.54.0
