On Wed, 09 Sep 2026 11:16:57 +0800, panciyan <[email protected]>
wrote:
> [...]
> * config/riscv/riscv.cc (riscv_zilsd_valid_mem_p): Double-check
> address.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/zilsd-align-split-arg-1.c: New test.
> * gcc.target/riscv/zilsd-align-split-arg-2.c: New test.
Thanks for the patch.
>
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index f8b54fc4ae6..9fa420a39b4 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -1270,10 +1270,31 @@ riscv_zilsd_required_align (void)
> [ ... skip 16 lines ... ]
> + offset, so double-check the address when it is a constant offset from a
> + frame-related pointer (all 16-byte aligned on RISC-V). */
> + rtx addr = XEXP (mem, 0);
> + if (GET_CODE (addr) == PLUS
> + && REG_P (XEXP (addr, 0))
> + && CONST_INT_P (XEXP (addr, 1)))
Could you please also handle large frame offsets?
Address legitimization can materialize part of the frame offset in a register,
so the MEM address is not
necessarily in frame_reg + CONST_INT form for this check to recognize.
For example, with a 4096-byte local frame, RV32I still emits with
-mzilsd-strict-align. The effective address
is only 4-byte aligned but MEM_ALIGN is still A64, so the Zilsd load is
incorrectly accepted.:
add a7,sp,a6 # address = entry_sp - 4
ld a0,0(a7)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/zilsd-align-split-arg-2.c
> b/gcc/testsuite/gcc.target/riscv/zilsd-align-split-arg-2.c
> new file mode 100644
> index 00000000000..248b16b0686
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zilsd-align-split-arg-2.c
> @@ -0,0 +1,22 @@
> [ ... skip 16 lines ... ]
> + return n;
> +}
> +
> +/* The misaligned reload must use two 32-bit "lw", never a single zilsd
> + "ld" from the 4-byte-aligned stack offset 12. */
> +/* { dg-final { scan-assembler-not {ld\t[a-z0-9]+,12\(sp\)} } } */
Could you also handle materialized frame addresses and add a regression test
covering this case?
Thanks,
Naveen
--
Naveen <[email protected]>
