> -----Original Message----- > From: H.J. Lu <[email protected]> > Sent: Thursday, September 10, 2026 10:03 AM > To: Hongtao Liu <[email protected]> > Cc: GCC Patches <[email protected]>; Uros Bizjak > <[email protected]>; Liu, Hongtao <[email protected]> > Subject: [PATCH v2] x86-64: Increase gain for TImode pand/pior/pxor loads > > On Mon, Aug 31, 2026 at 3:27 PM Hongtao Liu <[email protected]> wrote: > > > > On Mon, Aug 31, 2026 at 7:34 AM H.J. Lu <[email protected]> wrote: > > > > > > Add a gain of COSTS_N_INSNS (1) for pxor with TImode memory since it > > > reduces one memory access vs 2 x xorq with DImode memory > > > > On Intel E-core and Zen5, xorq with DImode memory takes only 1 uop, on > > intel P-core it takes 2 uops. So from uops perspective, on some > > platforms we don't have extra gain for memory access(we already gain > > COSTS_N_INSNS (1) for 1 por vs 2 xor). > > if we need to account for 1 less memory access, all operations which > > support memory_operand in their TImode patterns should be handled, not > > only xor/ior? > > Only pand/pior/pxor loads are relevant here. > > > even for xor/ior, why MEM_P(XEXP (src, 1)), although xorv1ti3 only > > supports memory operand for XEXP (src, 1), but the xorti3_doubleword > > pattern support memory_operand for XEXP (src, 0), and we're handling > > TImode insn in compute_convert_gain. > > Here is the v2 patch to handle pand and check XEXP (src, 0). Ok.
> > -- > H.J. > ---- > Add a gain of COSTS_N_INSNS (1) for TImode pand/pior/pxor loads since they > reduce one memory load, comparing against DImode and/ior/xor loads. > > gcc/ > > PR target/127020 > * config/i386/i386-features.cc > (timode_scalar_chain::compute_convert_gain): Add gain of COSTS_N_INSNS > (1) for pand/pior/pxor loads. > > gcc/testsuite/ > > PR target/127020 > * gcc.target/i386/sse2-stv-3.c: Adjusted. > * gcc.target/i386/sse2-stv-8.c: New test. > * gcc.target/i386/sse2-stv-9.c: Likewise.
