[PATCH v1 9/9] testsuite, amdgcn: testsuite changes

[Andrew Stubbs]

The GCN testcases were written with the assumption that vectorization was
always available.  With SIMT, this assumption is no longer valid, so this patch
adds the appropriate effective target lines.  The target-supports.exp settings
are adjusted to fix the target-independent test expectations.

gcc/testsuite/ChangeLog:

        * lib/target-supports.exp (check_effective_target_amdgcn_simd): New
        procedure.
        (check_effective_target_amdgcn_simt): New procedure.
        (check_effective_target_vect_int): Use
        check_effective_target_amdgcn_simd instead of testing for amdgcn
        directly, because the vector modes only exist in SIMD mode.
        (check_effective_target_vect_early_break): Likewise.
        (check_effective_target_vect_early_break_hw): Likewise.
        (check_effective_target_vect_intfloat_cvt): Likewise.
        (check_effective_target_vect_uintfloat_cvt): Likewise.
        (check_effective_target_vect_floatint_cvt): Likewise.
        (check_effective_target_vect_floatuint_cvt): Likewise.
        (check_effective_target_vect_simd_clones): Likewise.
        (check_effective_target_vect_shift): Likewise.
        (check_effective_target_whole_vector_shift): Likewise.
        (check_effective_target_vect_bswap): Likewise.
        (check_effective_target_vect_char_add): Likewise.
        (check_effective_target_vect_shift_char): Likewise.
        (check_effective_target_vect_long): Likewise.
        (check_effective_target_vect_float): Likewise.
        (check_effective_target_vect_double): Likewise.
        (check_effective_target_vect_long_long): Likewise.
        (check_effective_target_vect_perm): Likewise.
        (check_effective_target_vect_perm_byte): Likewise.
        (check_effective_target_vect_perm_short): Likewise.
        (check_effective_target_vect_widen_mult_qi_to_hi): Likewise.
        (check_effective_target_vect_widen_mult_hi_to_si): Likewise.
        (check_effective_target_vect_widen_mult_qi_to_hi_pattern): Likewise.
        (check_effective_target_vect_widen_mult_hi_to_si_pattern): Likewise.
        (check_effective_target_vect_pack_trunc): Likewise.
        (check_effective_target_vect_unpack): Likewise.
        (check_effective_target_vect_hw_misalign): Likewise.
        (check_effective_target_vect_natural_alignment): Likewise.
        (check_effective_target_vect_fully_masked): Likewise.
        (check_effective_target_vect_masked_load): Likewise.
        (check_effective_target_vect_masked_store): Likewise.
        (check_effective_target_vect_gather_load_ifn): Likewise.
        (check_effective_target_vect_scatter_store): Likewise.
        (check_effective_target_vect_condition): Likewise.
        (check_effective_target_vect_cond_mixed): Likewise.
        (check_effective_target_vect_char_mult): Likewise.
        (check_effective_target_vect_short_mult): Likewise.
        (check_effective_target_vect_int_mult): Likewise.
        (check_effective_target_vect_long_mult): Likewise.
        (check_effective_target_vect_call_copysignf): Likewise.
        (check_effective_target_vect_call_sqrtf): Likewise.
        (check_effective_target_vect_call_lrint): Likewise.
        (check_effective_target_vect_call_btrunc): Likewise.
        (check_effective_target_vect_call_btruncf): Likewise.
        (check_effective_target_vect_call_ceil): Likewise.
        (check_effective_target_vect_call_ceilf): Likewise.
        (check_effective_target_vect_call_floor): Likewise.
        (check_effective_target_vect_call_floorf): Likewise.
        (check_effective_target_vect_logical_reduc): Likewise.
        (check_effective_target_vect_fold_extract_last): Likewise.
        (check_vect_support_and_set_flags): Do not run the vectorizer tests
        on amdgcn in SIMT mode.
        * gcc.target/gcn/avgpr-spill-double.c: Require vect_double.
        * gcc.target/gcn/avgpr-spill-int.c: Require vect_int.
        * gcc.target/gcn/avgpr-spill-long.c: Likewise.
        * gcc.target/gcn/avgpr-spill-short.c: Likewise.
        * gcc.target/gcn/cond_fmaxnm_1.c: Require vect_float and vect_double.
        * gcc.target/gcn/cond_fmaxnm_1_run.c: Likewise.
        * gcc.target/gcn/cond_fmaxnm_2.c: Likewise.
        * gcc.target/gcn/cond_fmaxnm_2_run.c: Likewise.
        * gcc.target/gcn/cond_fmaxnm_3.c: Likewise.
        * gcc.target/gcn/cond_fmaxnm_3_run.c: Likewise.
        * gcc.target/gcn/cond_fmaxnm_4.c: Likewise.
        * gcc.target/gcn/cond_fmaxnm_4_run.c: Likewise.
        * gcc.target/gcn/cond_fmaxnm_5.c: Likewise.
        * gcc.target/gcn/cond_fmaxnm_5_run.c: Likewise.
        * gcc.target/gcn/cond_fmaxnm_6.c: Likewise.
        * gcc.target/gcn/cond_fmaxnm_6_run.c: Likewise.
        * gcc.target/gcn/cond_fmaxnm_7.c: Likewise.
        * gcc.target/gcn/cond_fmaxnm_7_run.c: Likewise.
        * gcc.target/gcn/cond_fmaxnm_8.c: Likewise.
        * gcc.target/gcn/cond_fmaxnm_8_run.c: Likewise.
        * gcc.target/gcn/cond_fminnm_1.c: Likewise.
        * gcc.target/gcn/cond_fminnm_1_run.c: Likewise.
        * gcc.target/gcn/cond_fminnm_2.c: Likewise.
        * gcc.target/gcn/cond_fminnm_2_run.c: Likewise.
        * gcc.target/gcn/cond_fminnm_3.c: Likewise.
        * gcc.target/gcn/cond_fminnm_3_run.c: Likewise.
        * gcc.target/gcn/cond_fminnm_4.c: Likewise.
        * gcc.target/gcn/cond_fminnm_4_run.c: Likewise.
        * gcc.target/gcn/cond_fminnm_5.c: Likewise.
        * gcc.target/gcn/cond_fminnm_5_run.c: Likewise.
        * gcc.target/gcn/cond_fminnm_6.c: Likewise.
        * gcc.target/gcn/cond_fminnm_6_run.c: Likewise.
        * gcc.target/gcn/cond_fminnm_7.c: Likewise.
        * gcc.target/gcn/cond_fminnm_7_run.c: Likewise.
        * gcc.target/gcn/cond_fminnm_8.c: Likewise.
        * gcc.target/gcn/cond_fminnm_8_run.c: Likewise.
        * gcc.target/gcn/cond_shift_3.c: Require vect_int.
        * gcc.target/gcn/cond_shift_3_run.c: Likewise.
        * gcc.target/gcn/cond_shift_4.c: Likewise.
        * gcc.target/gcn/cond_shift_4_run.c: Likewise.
        * gcc.target/gcn/cond_shift_8.c: Likewise.
        * gcc.target/gcn/cond_shift_8_run.c: Likewise.
        * gcc.target/gcn/cond_shift_9.c: Likewise.
        * gcc.target/gcn/cond_shift_9_run.c: Likewise.
        * gcc.target/gcn/cond_smax_1.c: Likewise.
        * gcc.target/gcn/cond_smax_1_run.c: Likewise.
        * gcc.target/gcn/cond_smin_1.c: Likewise.
        * gcc.target/gcn/cond_smin_1_run.c: Likewise.
        * gcc.target/gcn/cond_umax_1.c: Likewise.
        * gcc.target/gcn/cond_umax_1_run.c: Likewise.
        * gcc.target/gcn/cond_umin_1.c: Likewise.
        * gcc.target/gcn/cond_umin_1_run.c: Likewise.
        * gcc.target/gcn/math-builtins-1.c: Require vect_float and vect_double.
        * gcc.target/gcn/sgpr-spill-double.c: Require amdgcn_simd, and say
        why.
        * gcc.target/gcn/sgpr-spill-int.c: Likewise.
        * gcc.target/gcn/sgpr-spill-long.c: Likewise.
        * gcc.target/gcn/sgpr-spill-short.c: Likewise.
        * gcc.target/gcn/simd-math-1.c: Require vect_float and vect_double.
        * gcc.target/gcn/simd-math-2.c: Likewise.
        * gcc.target/gcn/simd-math-3-16.c: Require vect_int.
        * gcc.target/gcn/simd-math-3-2.c: Likewise.
        * gcc.target/gcn/simd-math-3-32.c: Likewise.
        * gcc.target/gcn/simd-math-3-4.c: Likewise.
        * gcc.target/gcn/simd-math-3-8.c: Likewise.
        * gcc.target/gcn/simd-math-3-char-16.c: Likewise.
        * gcc.target/gcn/simd-math-3-char-2.c: Likewise.
        * gcc.target/gcn/simd-math-3-char-32.c: Likewise.
        * gcc.target/gcn/simd-math-3-char-4.c: Likewise.
        * gcc.target/gcn/simd-math-3-char-8.c: Likewise.
        * gcc.target/gcn/simd-math-3-char-run-16.c: Likewise.
        * gcc.target/gcn/simd-math-3-char-run-2.c: Likewise.
        * gcc.target/gcn/simd-math-3-char-run-32.c: Likewise.
        * gcc.target/gcn/simd-math-3-char-run-4.c: Likewise.
        * gcc.target/gcn/simd-math-3-char-run-8.c: Likewise.
        * gcc.target/gcn/simd-math-3-char-run.c: Likewise.
        * gcc.target/gcn/simd-math-3-char.c: Likewise.
        * gcc.target/gcn/simd-math-3-long-16.c: Likewise.
        * gcc.target/gcn/simd-math-3-long-2.c: Likewise.
        * gcc.target/gcn/simd-math-3-long-32.c: Likewise.
        * gcc.target/gcn/simd-math-3-long-4.c: Likewise.
        * gcc.target/gcn/simd-math-3-long-8.c: Likewise.
        * gcc.target/gcn/simd-math-3-long-run-16.c: Likewise.
        * gcc.target/gcn/simd-math-3-long-run-2.c: Likewise.
        * gcc.target/gcn/simd-math-3-long-run-32.c: Likewise.
        * gcc.target/gcn/simd-math-3-long-run-4.c: Likewise.
        * gcc.target/gcn/simd-math-3-long-run-8.c: Likewise.
        * gcc.target/gcn/simd-math-3-long-run.c: Likewise.
        * gcc.target/gcn/simd-math-3-long.c: Likewise.
        * gcc.target/gcn/simd-math-3-run-16.c: Likewise.
        * gcc.target/gcn/simd-math-3-run-2.c: Likewise.
        * gcc.target/gcn/simd-math-3-run-32.c: Likewise.
        * gcc.target/gcn/simd-math-3-run-4.c: Likewise.
        * gcc.target/gcn/simd-math-3-run-8.c: Likewise.
        * gcc.target/gcn/simd-math-3-run.c: Likewise.
        * gcc.target/gcn/simd-math-3-short-16.c: Likewise.
        * gcc.target/gcn/simd-math-3-short-2.c: Likewise.
        * gcc.target/gcn/simd-math-3-short-32.c: Likewise.
        * gcc.target/gcn/simd-math-3-short-4.c: Likewise.
        * gcc.target/gcn/simd-math-3-short-8.c: Likewise.
        * gcc.target/gcn/simd-math-3-short-run-16.c: Likewise.
        * gcc.target/gcn/simd-math-3-short-run-2.c: Likewise.
        * gcc.target/gcn/simd-math-3-short-run-32.c: Likewise.
        * gcc.target/gcn/simd-math-3-short-run-4.c: Likewise.
        * gcc.target/gcn/simd-math-3-short-run-8.c: Likewise.
        * gcc.target/gcn/simd-math-3-short-run.c: Likewise.
        * gcc.target/gcn/simd-math-3-short.c: Likewise.
        * gcc.target/gcn/simd-math-3.c: Likewise.
        * gcc.target/gcn/simd-math-4-char-run.c: Likewise.
        * gcc.target/gcn/simd-math-4-char.c: Likewise.
        * gcc.target/gcn/simd-math-4-long-run.c: Likewise.
        * gcc.target/gcn/simd-math-4-long.c: Likewise.
        * gcc.target/gcn/simd-math-4-run.c: Likewise.
        * gcc.target/gcn/simd-math-4-short-run.c: Likewise.
        * gcc.target/gcn/simd-math-4-short.c: Likewise.
        * gcc.target/gcn/simd-math-4.c: Likewise.
        * gcc.target/gcn/simd-math-5-16.c: Likewise.
        * gcc.target/gcn/simd-math-5-32.c: Likewise.
        * gcc.target/gcn/simd-math-5-4.c: Likewise.
        * gcc.target/gcn/simd-math-5-8.c: Likewise.
        * gcc.target/gcn/simd-math-5-char-16.c: Likewise.
        * gcc.target/gcn/simd-math-5-char-32.c: Likewise.
        * gcc.target/gcn/simd-math-5-char-4.c: Likewise.
        * gcc.target/gcn/simd-math-5-char-8.c: Likewise.
        * gcc.target/gcn/simd-math-5-char-run-16.c: Likewise.
        * gcc.target/gcn/simd-math-5-char-run-32.c: Likewise.
        * gcc.target/gcn/simd-math-5-char-run-4.c: Likewise.
        * gcc.target/gcn/simd-math-5-char-run-8.c: Likewise.
        * gcc.target/gcn/simd-math-5-char-run.c: Likewise.
        * gcc.target/gcn/simd-math-5-char.c: Likewise.
        * gcc.target/gcn/simd-math-5-long-16.c: Likewise.
        * gcc.target/gcn/simd-math-5-long-32.c: Likewise.
        * gcc.target/gcn/simd-math-5-long-4.c: Likewise.
        * gcc.target/gcn/simd-math-5-long-8.c: Likewise.
        * gcc.target/gcn/simd-math-5-long-run-16.c: Likewise.
        * gcc.target/gcn/simd-math-5-long-run-32.c: Likewise.
        * gcc.target/gcn/simd-math-5-long-run-4.c: Likewise.
        * gcc.target/gcn/simd-math-5-long-run-8.c: Likewise.
        * gcc.target/gcn/simd-math-5-long-run.c: Likewise.
        * gcc.target/gcn/simd-math-5-long.c: Likewise.
        * gcc.target/gcn/simd-math-5-run-16.c: Likewise.
        * gcc.target/gcn/simd-math-5-run-32.c: Likewise.
        * gcc.target/gcn/simd-math-5-run-4.c: Likewise.
        * gcc.target/gcn/simd-math-5-run-8.c: Likewise.
        * gcc.target/gcn/simd-math-5-run.c: Likewise.
        * gcc.target/gcn/simd-math-5-short-16.c: Likewise.
        * gcc.target/gcn/simd-math-5-short-32.c: Likewise.
        * gcc.target/gcn/simd-math-5-short-4.c: Likewise.
        * gcc.target/gcn/simd-math-5-short-8.c: Likewise.
        * gcc.target/gcn/simd-math-5-short-run-16.c: Likewise.
        * gcc.target/gcn/simd-math-5-short-run-32.c: Likewise.
        * gcc.target/gcn/simd-math-5-short-run-4.c: Likewise.
        * gcc.target/gcn/simd-math-5-short-run-8.c: Likewise.
        * gcc.target/gcn/simd-math-5-short-run.c: Likewise.
        * gcc.target/gcn/simd-math-5-short.c: Likewise.
        * gcc.target/gcn/simd-math-5.c: Likewise.
        * gcc.target/gcn/smax_1.c: Likewise.
        * gcc.target/gcn/smax_1_run.c: Likewise.
        * gcc.target/gcn/smin_1.c: Likewise.
        * gcc.target/gcn/smin_1_run.c: Likewise.
        * gcc.target/gcn/sram-ecc-3.c: Likewise.
        * gcc.target/gcn/sram-ecc-4.c: Likewise.
        * gcc.target/gcn/sram-ecc-7.c: Likewise.
        * gcc.target/gcn/sram-ecc-8.c: Likewise.
        * gcc.target/gcn/umax_1.c: Likewise.
        * gcc.target/gcn/umax_1_run.c: Likewise.
        * gcc.target/gcn/umin_1.c: Likewise.
        * gcc.target/gcn/umin_1_run.c: Likewise.
        * gcc.target/gcn/vcc-clobber.c: Likewise.
---
 .../gcc.target/gcn/avgpr-spill-double.c       |   1 +
 .../gcc.target/gcn/avgpr-spill-int.c          |   1 +
 .../gcc.target/gcn/avgpr-spill-long.c         |   1 +
 .../gcc.target/gcn/avgpr-spill-short.c        |   1 +
 gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c  |   2 +
 .../gcc.target/gcn/cond_fmaxnm_1_run.c        |   2 +
 gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c  |   2 +
 .../gcc.target/gcn/cond_fmaxnm_2_run.c        |   2 +
 gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c  |   2 +
 .../gcc.target/gcn/cond_fmaxnm_3_run.c        |   2 +
 gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c  |   2 +
 .../gcc.target/gcn/cond_fmaxnm_4_run.c        |   2 +
 gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c  |   2 +
 .../gcc.target/gcn/cond_fmaxnm_5_run.c        |   2 +
 gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c  |   2 +
 .../gcc.target/gcn/cond_fmaxnm_6_run.c        |   2 +
 gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c  |   2 +
 .../gcc.target/gcn/cond_fmaxnm_7_run.c        |   2 +
 gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c  |   2 +
 .../gcc.target/gcn/cond_fmaxnm_8_run.c        |   2 +
 gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c  |   2 +
 .../gcc.target/gcn/cond_fminnm_1_run.c        |   2 +
 gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c  |   2 +
 .../gcc.target/gcn/cond_fminnm_2_run.c        |   2 +
 gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c  |   2 +
 .../gcc.target/gcn/cond_fminnm_3_run.c        |   2 +
 gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c  |   2 +
 .../gcc.target/gcn/cond_fminnm_4_run.c        |   2 +
 gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c  |   2 +
 .../gcc.target/gcn/cond_fminnm_5_run.c        |   2 +
 gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c  |   2 +
 .../gcc.target/gcn/cond_fminnm_6_run.c        |   2 +
 gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c  |   2 +
 .../gcc.target/gcn/cond_fminnm_7_run.c        |   2 +
 gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c  |   2 +
 .../gcc.target/gcn/cond_fminnm_8_run.c        |   2 +
 gcc/testsuite/gcc.target/gcn/cond_shift_3.c   |   1 +
 .../gcc.target/gcn/cond_shift_3_run.c         |   1 +
 gcc/testsuite/gcc.target/gcn/cond_shift_4.c   |   1 +
 .../gcc.target/gcn/cond_shift_4_run.c         |   1 +
 gcc/testsuite/gcc.target/gcn/cond_shift_8.c   |   1 +
 .../gcc.target/gcn/cond_shift_8_run.c         |   1 +
 gcc/testsuite/gcc.target/gcn/cond_shift_9.c   |   1 +
 .../gcc.target/gcn/cond_shift_9_run.c         |   1 +
 gcc/testsuite/gcc.target/gcn/cond_smax_1.c    |   1 +
 .../gcc.target/gcn/cond_smax_1_run.c          |   1 +
 gcc/testsuite/gcc.target/gcn/cond_smin_1.c    |   1 +
 .../gcc.target/gcn/cond_smin_1_run.c          |   1 +
 gcc/testsuite/gcc.target/gcn/cond_umax_1.c    |   1 +
 .../gcc.target/gcn/cond_umax_1_run.c          |   1 +
 gcc/testsuite/gcc.target/gcn/cond_umin_1.c    |   1 +
 .../gcc.target/gcn/cond_umin_1_run.c          |   1 +
 .../gcc.target/gcn/math-builtins-1.c          |   2 +
 .../gcc.target/gcn/sgpr-spill-double.c        |   2 +
 gcc/testsuite/gcc.target/gcn/sgpr-spill-int.c |   2 +
 .../gcc.target/gcn/sgpr-spill-long.c          |   2 +
 .../gcc.target/gcn/sgpr-spill-short.c         |   2 +
 gcc/testsuite/gcc.target/gcn/simd-math-1.c    |   2 +
 gcc/testsuite/gcc.target/gcn/simd-math-2.c    |   2 +
 gcc/testsuite/gcc.target/gcn/simd-math-3-16.c |   1 +
 gcc/testsuite/gcc.target/gcn/simd-math-3-2.c  |   1 +
 gcc/testsuite/gcc.target/gcn/simd-math-3-32.c |   1 +
 gcc/testsuite/gcc.target/gcn/simd-math-3-4.c  |   1 +
 gcc/testsuite/gcc.target/gcn/simd-math-3-8.c  |   1 +
 .../gcc.target/gcn/simd-math-3-char-16.c      |   1 +
 .../gcc.target/gcn/simd-math-3-char-2.c       |   1 +
 .../gcc.target/gcn/simd-math-3-char-32.c      |   1 +
 .../gcc.target/gcn/simd-math-3-char-4.c       |   1 +
 .../gcc.target/gcn/simd-math-3-char-8.c       |   1 +
 .../gcc.target/gcn/simd-math-3-char-run-16.c  |   1 +
 .../gcc.target/gcn/simd-math-3-char-run-2.c   |   1 +
 .../gcc.target/gcn/simd-math-3-char-run-32.c  |   1 +
 .../gcc.target/gcn/simd-math-3-char-run-4.c   |   1 +
 .../gcc.target/gcn/simd-math-3-char-run-8.c   |   1 +
 .../gcc.target/gcn/simd-math-3-char-run.c     |   1 +
 .../gcc.target/gcn/simd-math-3-char.c         |   1 +
 .../gcc.target/gcn/simd-math-3-long-16.c      |   1 +
 .../gcc.target/gcn/simd-math-3-long-2.c       |   1 +
 .../gcc.target/gcn/simd-math-3-long-32.c      |   1 +
 .../gcc.target/gcn/simd-math-3-long-4.c       |   1 +
 .../gcc.target/gcn/simd-math-3-long-8.c       |   1 +
 .../gcc.target/gcn/simd-math-3-long-run-16.c  |   1 +
 .../gcc.target/gcn/simd-math-3-long-run-2.c   |   1 +
 .../gcc.target/gcn/simd-math-3-long-run-32.c  |   1 +
 .../gcc.target/gcn/simd-math-3-long-run-4.c   |   1 +
 .../gcc.target/gcn/simd-math-3-long-run-8.c   |   1 +
 .../gcc.target/gcn/simd-math-3-long-run.c     |   1 +
 .../gcc.target/gcn/simd-math-3-long.c         |   1 +
 .../gcc.target/gcn/simd-math-3-run-16.c       |   1 +
 .../gcc.target/gcn/simd-math-3-run-2.c        |   1 +
 .../gcc.target/gcn/simd-math-3-run-32.c       |   1 +
 .../gcc.target/gcn/simd-math-3-run-4.c        |   1 +
 .../gcc.target/gcn/simd-math-3-run-8.c        |   1 +
 .../gcc.target/gcn/simd-math-3-run.c          |   1 +
 .../gcc.target/gcn/simd-math-3-short-16.c     |   1 +
 .../gcc.target/gcn/simd-math-3-short-2.c      |   1 +
 .../gcc.target/gcn/simd-math-3-short-32.c     |   1 +
 .../gcc.target/gcn/simd-math-3-short-4.c      |   1 +
 .../gcc.target/gcn/simd-math-3-short-8.c      |   1 +
 .../gcc.target/gcn/simd-math-3-short-run-16.c |   1 +
 .../gcc.target/gcn/simd-math-3-short-run-2.c  |   1 +
 .../gcc.target/gcn/simd-math-3-short-run-32.c |   1 +
 .../gcc.target/gcn/simd-math-3-short-run-4.c  |   1 +
 .../gcc.target/gcn/simd-math-3-short-run-8.c  |   1 +
 .../gcc.target/gcn/simd-math-3-short-run.c    |   1 +
 .../gcc.target/gcn/simd-math-3-short.c        |   1 +
 gcc/testsuite/gcc.target/gcn/simd-math-3.c    |   2 +
 .../gcc.target/gcn/simd-math-4-char-run.c     |   1 +
 .../gcc.target/gcn/simd-math-4-char.c         |   1 +
 .../gcc.target/gcn/simd-math-4-long-run.c     |   1 +
 .../gcc.target/gcn/simd-math-4-long.c         |   1 +
 .../gcc.target/gcn/simd-math-4-run.c          |   1 +
 .../gcc.target/gcn/simd-math-4-short-run.c    |   1 +
 .../gcc.target/gcn/simd-math-4-short.c        |   1 +
 gcc/testsuite/gcc.target/gcn/simd-math-4.c    |   2 +
 gcc/testsuite/gcc.target/gcn/simd-math-5-16.c |   1 +
 gcc/testsuite/gcc.target/gcn/simd-math-5-32.c |   1 +
 gcc/testsuite/gcc.target/gcn/simd-math-5-4.c  |   1 +
 gcc/testsuite/gcc.target/gcn/simd-math-5-8.c  |   1 +
 .../gcc.target/gcn/simd-math-5-char-16.c      |   1 +
 .../gcc.target/gcn/simd-math-5-char-32.c      |   1 +
 .../gcc.target/gcn/simd-math-5-char-4.c       |   1 +
 .../gcc.target/gcn/simd-math-5-char-8.c       |   1 +
 .../gcc.target/gcn/simd-math-5-char-run-16.c  |   1 +
 .../gcc.target/gcn/simd-math-5-char-run-32.c  |   1 +
 .../gcc.target/gcn/simd-math-5-char-run-4.c   |   1 +
 .../gcc.target/gcn/simd-math-5-char-run-8.c   |   1 +
 .../gcc.target/gcn/simd-math-5-char-run.c     |   1 +
 .../gcc.target/gcn/simd-math-5-char.c         |   1 +
 .../gcc.target/gcn/simd-math-5-long-16.c      |   1 +
 .../gcc.target/gcn/simd-math-5-long-32.c      |   1 +
 .../gcc.target/gcn/simd-math-5-long-4.c       |   1 +
 .../gcc.target/gcn/simd-math-5-long-8.c       |   1 +
 .../gcc.target/gcn/simd-math-5-long-run-16.c  |   1 +
 .../gcc.target/gcn/simd-math-5-long-run-32.c  |   1 +
 .../gcc.target/gcn/simd-math-5-long-run-4.c   |   1 +
 .../gcc.target/gcn/simd-math-5-long-run-8.c   |   1 +
 .../gcc.target/gcn/simd-math-5-long-run.c     |   1 +
 .../gcc.target/gcn/simd-math-5-long.c         |   1 +
 .../gcc.target/gcn/simd-math-5-run-16.c       |   1 +
 .../gcc.target/gcn/simd-math-5-run-32.c       |   1 +
 .../gcc.target/gcn/simd-math-5-run-4.c        |   1 +
 .../gcc.target/gcn/simd-math-5-run-8.c        |   1 +
 .../gcc.target/gcn/simd-math-5-run.c          |   1 +
 .../gcc.target/gcn/simd-math-5-short-16.c     |   1 +
 .../gcc.target/gcn/simd-math-5-short-32.c     |   1 +
 .../gcc.target/gcn/simd-math-5-short-4.c      |   1 +
 .../gcc.target/gcn/simd-math-5-short-8.c      |   1 +
 .../gcc.target/gcn/simd-math-5-short-run-16.c |   1 +
 .../gcc.target/gcn/simd-math-5-short-run-32.c |   1 +
 .../gcc.target/gcn/simd-math-5-short-run-4.c  |   1 +
 .../gcc.target/gcn/simd-math-5-short-run-8.c  |   1 +
 .../gcc.target/gcn/simd-math-5-short-run.c    |   1 +
 .../gcc.target/gcn/simd-math-5-short.c        |   1 +
 gcc/testsuite/gcc.target/gcn/simd-math-5.c    |   1 +
 gcc/testsuite/gcc.target/gcn/smax_1.c         |   1 +
 gcc/testsuite/gcc.target/gcn/smax_1_run.c     |   1 +
 gcc/testsuite/gcc.target/gcn/smin_1.c         |   1 +
 gcc/testsuite/gcc.target/gcn/smin_1_run.c     |   1 +
 gcc/testsuite/gcc.target/gcn/sram-ecc-3.c     |   1 +
 gcc/testsuite/gcc.target/gcn/sram-ecc-4.c     |   1 +
 gcc/testsuite/gcc.target/gcn/sram-ecc-7.c     |   1 +
 gcc/testsuite/gcc.target/gcn/sram-ecc-8.c     |   1 +
 gcc/testsuite/gcc.target/gcn/umax_1.c         |   1 +
 gcc/testsuite/gcc.target/gcn/umax_1_run.c     |   1 +
 gcc/testsuite/gcc.target/gcn/umin_1.c         |   1 +
 gcc/testsuite/gcc.target/gcn/umin_1_run.c     |   1 +
 gcc/testsuite/gcc.target/gcn/vcc-clobber.c    |   1 +
 gcc/testsuite/lib/target-supports.exp         | 131 +++++++++++-------
 169 files changed, 290 insertions(+), 50 deletions(-)

diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c 
b/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c
index 3015f8ec6bb..02a6d61cf56 100644
--- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx908 -O1" } */
+/* { dg-require-effective-target vect_double } */
 /* { dg-final { scan-assembler "accvgpr" } } */
 
 typedef double v32df __attribute__ ((__vector_size__ (sizeof(double)*32)));
diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c 
b/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c
index 2d033231ccc..8319c246922 100644
--- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx908 -O1" } */
+/* { dg-require-effective-target vect_int } */
 /* { dg-final { scan-assembler "accvgpr" } } */
 
 /* What spills here, in the vector variants, is the 64-bit per-lane
diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c 
b/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c
index 1926fd9df0b..42eb6dab35b 100644
--- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx908 -O1" } */
+/* { dg-require-effective-target vect_int } */
 /* { dg-final { scan-assembler "accvgpr" } } */
 
 typedef long v32di __attribute__ ((__vector_size__ (sizeof(long)*32)));
diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c 
b/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c
index 24e2c3751ca..726885dd194 100644
--- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx908 -O1" } */
+/* { dg-require-effective-target vect_int } */
 /* { dg-final { scan-assembler "accvgpr" } } */
 
 /* Use 64-lane vectors so that the array is larger than the 4096-byte
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c 
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c
index 29e77064bc5..7e0dd99057c 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c
@@ -2,6 +2,8 @@
 /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1_run.c
index 1e4c81c17a9..793b0fe944e 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1_run.c
@@ -1,5 +1,7 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include "cond_fmaxnm_1.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c 
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c
index f781ca2c013..fcc85fd008b 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c
@@ -2,6 +2,8 @@
 /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2_run.c
index 05d18f41f06..a78a54326d3 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2_run.c
@@ -1,5 +1,7 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include "cond_fmaxnm_2.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c 
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
index 0f1fcfbb149..58a1ea19a97 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
@@ -2,6 +2,8 @@
 /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3_run.c
index 23dd00b0b13..66656042c23 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3_run.c
@@ -1,5 +1,7 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include "cond_fmaxnm_3.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c 
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
index 7885808bca3..fd2994f0393 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
@@ -2,6 +2,8 @@
 /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4_run.c
index 1db583242ba..5e8731ff560 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4_run.c
@@ -1,5 +1,7 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include "cond_fmaxnm_4.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c 
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c
index 6bfc2b9627f..9d021042ee2 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c
@@ -2,6 +2,8 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include "cond_fmaxnm_1.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5_run.c
index 8c0bc2ae876..ea1ee8881f5 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5_run.c
@@ -1,4 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include "cond_fmaxnm_1_run.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c 
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c
index 8ea52725cbe..f0eb88465f5 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c
@@ -2,6 +2,8 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include "cond_fmaxnm_2.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6_run.c
index 5c5db46b390..12f6929f5c8 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6_run.c
@@ -1,4 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include "cond_fmaxnm_2_run.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c 
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c
index 97f8cf57ee3..36c0d65f93c 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c
@@ -2,6 +2,8 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include "cond_fmaxnm_3.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7_run.c
index 0abe626fdfb..bfceb361809 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7_run.c
@@ -1,4 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include "cond_fmaxnm_3_run.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c 
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c
index 9de89790a12..66ec4a7aba9 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c
@@ -2,6 +2,8 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include "cond_fmaxnm_4.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8_run.c
index 43b892f922e..1b838b3f833 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8_run.c
@@ -1,4 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include "cond_fmaxnm_4_run.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c 
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c
index 7068e8c4f54..c6ae78f785a 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c
@@ -2,6 +2,8 @@
 /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_1.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_1_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1_run.c
index 6dd9d499b35..f217f784a5c 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_1_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1_run.c
@@ -1,5 +1,7 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_1_run.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c 
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c
index d8ee9446e38..df4c85e5833 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c
@@ -2,6 +2,8 @@
 /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_2.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_2_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2_run.c
index 72784290113..fac8b59d74d 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_2_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2_run.c
@@ -1,5 +1,7 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_2_run.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c 
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
index 45b63c08814..ab7fa668232 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
@@ -2,6 +2,8 @@
 /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_3.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3_run.c
index 8c994cae202..1d955ac3c76 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3_run.c
@@ -1,5 +1,7 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_3_run.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c 
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
index bf41cc615a3..c3c348cc2f9 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
@@ -2,6 +2,8 @@
 /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4_run.c
index 728f4136015..31c1ef48d37 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4_run.c
@@ -1,5 +1,7 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_4_run.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c 
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c
index 84ab917043d..c15a7cda815 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c
@@ -2,6 +2,8 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_1.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_5_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5_run.c
index 9236ab5b211..c2cda7d6f9c 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_5_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5_run.c
@@ -1,4 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include "cond_fminnm_1_run.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c 
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c
index a1525d91b33..c6cd6807daa 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c
@@ -2,6 +2,8 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_2.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_6_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6_run.c
index a5f90d9e76a..a1d8382d1bd 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_6_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6_run.c
@@ -1,4 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include "cond_fminnm_2_run.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c 
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c
index bb5e0f24d5b..d4fae063cb4 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c
@@ -2,6 +2,8 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_3.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_7_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7_run.c
index d7ad738db5c..c50888bd707 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_7_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7_run.c
@@ -1,4 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include "cond_fminnm_3_run.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c 
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c
index c090377c0e1..26c4232c6fa 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c
@@ -2,6 +2,8 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmaxnm_4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_8_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8_run.c
index 3d92353ac55..5db747b0a82 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_8_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8_run.c
@@ -1,4 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #include "cond_fminnm_4_run.c"
diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_3.c 
b/gcc/testsuite/gcc.target/gcn/cond_shift_3.c
index 1181384a495..1b5899fc985 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_shift_3.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_shift_3.c
@@ -2,6 +2,7 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_int } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_3_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_shift_3_run.c
index 8f89918e8ac..b53dcb0fbb7 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_shift_3_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_shift_3_run.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_int } */
 
 #include "cond_shift_3.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_4.c 
b/gcc/testsuite/gcc.target/gcn/cond_shift_4.c
index ea2110d0a6f..62738931837 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_shift_4.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_shift_4.c
@@ -2,6 +2,7 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_int } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_4_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_shift_4_run.c
index 6017d68e820..6b89c7272e6 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_shift_4_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_shift_4_run.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_int } */
 
 #include "cond_shift_4.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_8.c 
b/gcc/testsuite/gcc.target/gcn/cond_shift_8.c
index 9942a2e167c..d4248c93477 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_shift_8.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_shift_8.c
@@ -2,6 +2,7 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_int } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_8_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_shift_8_run.c
index 13da0197569..5f9e9c5d9f6 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_shift_8_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_shift_8_run.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_int } */
 
 #include "cond_shift_8.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_9.c 
b/gcc/testsuite/gcc.target/gcn/cond_shift_9.c
index 663192f97e7..dcce492591d 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_shift_9.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_shift_9.c
@@ -2,6 +2,7 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_int } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_9_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_shift_9_run.c
index de8e010bdab..7bd03d4ba44 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_shift_9_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_shift_9_run.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_int } */
 
 #include "cond_shift_9.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_smax_1.c 
b/gcc/testsuite/gcc.target/gcn/cond_smax_1.c
index 212091a15df..d5c3a08f97b 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_smax_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_smax_1.c
@@ -2,6 +2,7 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_int } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_smax_1_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_smax_1_run.c
index c951e614579..1d818c346b8 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_smax_1_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_smax_1_run.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_int } */
 
 #include "cond_smax_1.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_smin_1.c 
b/gcc/testsuite/gcc.target/gcn/cond_smin_1.c
index 714aab2f7f7..adf586de79b 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_smin_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_smin_1.c
@@ -2,6 +2,7 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_int } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_smin_1_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_smin_1_run.c
index bfdb7d1b9e8..6c8c3ba257e 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_smin_1_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_smin_1_run.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_int } */
 
 #include "cond_smin_1.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_umax_1.c 
b/gcc/testsuite/gcc.target/gcn/cond_umax_1.c
index 9018b006817..405174288c5 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_umax_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_umax_1.c
@@ -2,6 +2,7 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_int } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_umax_1_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_umax_1_run.c
index 2396c2452d7..15e7f69221c 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_umax_1_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_umax_1_run.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_int } */
 
 #include "cond_umax_1.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_umin_1.c 
b/gcc/testsuite/gcc.target/gcn/cond_umin_1.c
index 64d0a5eb350..fd3830c8fcb 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_umin_1.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_umin_1.c
@@ -2,6 +2,7 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_int } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/gcn/cond_umin_1_run.c 
b/gcc/testsuite/gcc.target/gcn/cond_umin_1_run.c
index ef6f03948ea..17a7527f1a5 100644
--- a/gcc/testsuite/gcc.target/gcn/cond_umin_1_run.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_umin_1_run.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_int } */
 
 #include "cond_umin_1.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/math-builtins-1.c 
b/gcc/testsuite/gcc.target/gcn/math-builtins-1.c
index e1aadfb40d9..e5fb3f5b990 100644
--- a/gcc/testsuite/gcc.target/gcn/math-builtins-1.c
+++ b/gcc/testsuite/gcc.target/gcn/math-builtins-1.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O1" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 typedef float v64sf __attribute__ ((vector_size (256)));
 typedef double v64df __attribute__ ((vector_size (512)));
diff --git a/gcc/testsuite/gcc.target/gcn/sgpr-spill-double.c 
b/gcc/testsuite/gcc.target/gcn/sgpr-spill-double.c
index 6757a19d8c9..aad78b323d8 100644
--- a/gcc/testsuite/gcc.target/gcn/sgpr-spill-double.c
+++ b/gcc/testsuite/gcc.target/gcn/sgpr-spill-double.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx908 -O1" } */
+/* In SIMT mode all values live in VGPRs, so there are no SGPR spills.  */
+/* { dg-require-effective-target amdgcn_simd } */
 /* { dg-final { scan-assembler-not "accvgpr" } } */
 
 /* Function epilogues use v6, but other registers may be a spill.  */
diff --git a/gcc/testsuite/gcc.target/gcn/sgpr-spill-int.c 
b/gcc/testsuite/gcc.target/gcn/sgpr-spill-int.c
index aed29442ce2..55dd22b0050 100644
--- a/gcc/testsuite/gcc.target/gcn/sgpr-spill-int.c
+++ b/gcc/testsuite/gcc.target/gcn/sgpr-spill-int.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx908 -O1" } */
+/* In SIMT mode all values live in VGPRs, so there are no SGPR spills.  */
+/* { dg-require-effective-target amdgcn_simd } */
 /* { dg-final { scan-assembler-not "accvgpr" } } */
 
 /* Function epilogues use v6, but other registers may be a spill.  */
diff --git a/gcc/testsuite/gcc.target/gcn/sgpr-spill-long.c 
b/gcc/testsuite/gcc.target/gcn/sgpr-spill-long.c
index 248624381b8..77de280d9d8 100644
--- a/gcc/testsuite/gcc.target/gcn/sgpr-spill-long.c
+++ b/gcc/testsuite/gcc.target/gcn/sgpr-spill-long.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx908 -O1" } */
+/* In SIMT mode all values live in VGPRs, so there are no SGPR spills.  */
+/* { dg-require-effective-target amdgcn_simd } */
 /* { dg-final { scan-assembler-not "accvgpr" } } */
 
 /* Function epilogues use v6, but other registers may be a spill.  */
diff --git a/gcc/testsuite/gcc.target/gcn/sgpr-spill-short.c 
b/gcc/testsuite/gcc.target/gcn/sgpr-spill-short.c
index 35bd0d56089..7ec6d1a0d97 100644
--- a/gcc/testsuite/gcc.target/gcn/sgpr-spill-short.c
+++ b/gcc/testsuite/gcc.target/gcn/sgpr-spill-short.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx908 -O1" } */
+/* In SIMT mode all values live in VGPRs, so there are no SGPR spills.  */
+/* { dg-require-effective-target amdgcn_simd } */
 /* { dg-final { scan-assembler-not "accvgpr" } } */
 
 /* Function epilogues use v6, but other registers may be a spill.  */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-1.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-1.c
index abd6a932a01..d738be36397 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-1.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-1.c
@@ -4,6 +4,8 @@
 /* { dg-options "-O2 -ftree-vectorize -fno-math-errno -mstack-size=3000000 
-fdump-tree-vect" } */
 /* The 'scan-tree-dump' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 
 #undef PRINT_RESULT
 #define VERBOSE 0
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-2.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-2.c
index 375a2ad9263..bdd0657a244 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-2.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-2.c
@@ -3,6 +3,8 @@
 
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize -fno-math-errno" } */
+/* { dg-require-effective-target vect_float } */
+/* { dg-require-effective-target vect_double } */
 /* { dg-set-target-env-var "GCN_STACK_SIZE" "3000000" } */
 
 #include "simd-math-1.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-16.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-16.c
index 20fa12f0efc..b7bbe089a93 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-16.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-16.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v16si
 #define UTYPE v16usi
 #define N 16
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-2.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-2.c
index 3baffe9ef01..d1424229a98 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-2.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-2.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v2si
 #define UTYPE v2usi
 #define N 2
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-32.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-32.c
index eab48158405..de25c7586cc 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-32.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-32.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v32si
 #define UTYPE v32usi
 #define N 32
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-4.c
index 370ca63554b..4ed6850cd29 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-4.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v4si
 #define UTYPE v4usi
 #define N 4
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-8.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-8.c
index 833608eaf2a..db2d6a52dfa 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-8.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-8.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v8si
 #define UTYPE v8usi
 #define N 8
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-16.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-16.c
index f156d49cd2a..55b5d3329b3 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-16.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-16.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v16qi
 #define UTYPE v16uqi
 #define N 16
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-2.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-2.c
index be4b9050fcd..5e6665b9fdd 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-2.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-2.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v2qi
 #define UTYPE v2uqi
 #define N 2
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-32.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-32.c
index b0cadecb0d8..9d99b9908a8 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-32.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-32.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v32qi
 #define UTYPE v32uqi
 #define N 32
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-4.c
index 4dc7c783d35..95f3febd345 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-4.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v4qi
 #define UTYPE v4uqi
 #define N 4
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-8.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-8.c
index ea3753aaaf8..822550def2c 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-8.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-8.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v8qi
 #define UTYPE v8uqi
 #define N 8
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-16.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-16.c
index 159b9802b07..bf8c49a3ed2 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-16.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-16.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-char-16.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-2.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-2.c
index 6e730d07a03..b8ed022031f 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-2.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-2.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-char-2.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-32.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-32.c
index 8e4932bf5b9..b61b0a896a4 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-32.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-32.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-char-32.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-4.c
index d07a4318390..a0a8528d440 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-4.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-char-4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-8.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-8.c
index 64f789a4528..e0978e1faa7 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-8.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-8.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-char-8.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run.c
index 4e2d4c0a19a..22327d8e8c4 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-char.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-char.c
index 478d09e2ec7..99742284708 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v64qi
 #define UTYPE v64uqi
 #include "simd-math-3.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-16.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-16.c
index 530f29e3778..fd172320ea5 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-16.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-16.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v16di
 #define UTYPE v16udi
 #define N 16
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-2.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-2.c
index 1c3e833c733..0693f3133be 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-2.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-2.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v2di
 #define UTYPE v2udi
 #define N 2
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-32.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-32.c
index c8556a85ffd..c30aa3c9db5 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-32.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-32.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v32di
 #define UTYPE v32udi
 #define N 32
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-4.c
index 514396c565d..684f8df9a7d 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-4.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v4di
 #define UTYPE v4udi
 #define N 4
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-8.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-8.c
index 428e3a5a807..fefc2c2d6b8 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-8.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-8.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v8di
 #define UTYPE v8udi
 #define N 8
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-16.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-16.c
index 7ce9c92a7a0..2229a493be0 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-16.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-16.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-long-16.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-2.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-2.c
index 20996a56f5c..8c85a0b678e 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-2.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-2.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-long-2.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-32.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-32.c
index 1ca25ac9b51..2377af9a72e 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-32.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-32.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-long-32.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-4.c
index b31769ad0bc..3009939215b 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-4.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-long-4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-8.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-8.c
index 930256a0fc7..52869692348 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-8.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-8.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-long-8.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run.c
index 363e42573d2..47383e8e1a9 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-long.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-long.c
index 321297b75ba..68d96aea111 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v64di
 #define UTYPE v64udi
 #include "simd-math-3.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-16.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-16.c
index ae8cdbffa1d..60e80096993 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-16.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-16.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-16.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-2.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-2.c
index 7d80382f23b..c81ed35fc8e 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-2.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-2.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-2.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-32.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-32.c
index 127fd36f0f4..90cb14cca97 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-32.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-32.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-32.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-4.c
index e1d5b5de5c1..e7fe27ac283 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-4.c
@@ -1,3 +1,4 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-4.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-8.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-8.c
index ec98b60ae2e..415f811eaa8 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-8.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-8.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-8.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-run.c
index aca508cbc25..d05c0d12e3c 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-run.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-16.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-16.c
index 80f04149035..9f9b85cbb3b 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-16.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-16.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v16hi
 #define UTYPE v16uhi
 #define N 16
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-2.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-2.c
index 37e5008a871..8d31010ecd3 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-2.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-2.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v2hi
 #define UTYPE v2uhi
 #define N 2
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-32.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-32.c
index 79aada0ea5b..f30a40cfa10 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-32.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-32.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v32hi
 #define UTYPE v32uhi
 #define N 32
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-4.c
index 014acacd2ea..537862f2c7b 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-4.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v4hi
 #define UTYPE v4uhi
 #define N 4
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-8.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-8.c
index 308b72b53e2..5a74f5fbf0b 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-8.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-8.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v8hi
 #define UTYPE v8uhi
 #define N 8
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-16.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-16.c
index 8ca866ce21f..6a47c099760 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-16.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-16.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-short-16.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-2.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-2.c
index 6c6d8b68f28..58ea6748f53 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-2.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-2.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-short-2.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-32.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-32.c
index 8c30ebc5528..bcc4d091e27 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-32.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-32.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-short-32.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-4.c
index e70697e6e42..b089770f3d0 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-4.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-short-4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-8.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-8.c
index 9cb9a6fe297..de535791ccf 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-8.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-8.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-short-8.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run.c
index 08f72671e96..177a9c61264 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-3-short.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3-short.c
index 1ade288f389..37a1ae30b3a 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define STYPE v64hi
 #define UTYPE v64uhi
 #include "simd-math-3.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-3.c
index def83852461..5604a6fb5da 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-3.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3.c
@@ -1,6 +1,8 @@
 /* Test that signed and unsigned division and modulus use the correct
    vector routines and give the correct results.  */
 
+/* { dg-require-effective-target vect_int } */
+
 /* Setting it this way ensures the run tests use the same flag as the
    compile tests.  */
 #pragma GCC optimize("O2")
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-char-run.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-4-char-run.c
index b328a3eeec5..db349e97644 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-4-char-run.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-char-run.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-4-char.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-char.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-4-char.c
index df24bd4e56d..255a7624501 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-4-char.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-char.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define TYPE v64qi
 #include "simd-math-4.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-long-run.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-4-long-run.c
index 34cbc467709..ba84a89435f 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-4-long-run.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-long-run.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-4-long.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-long.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-4-long.c
index 768a0dfc848..0730cafb9ea 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-4-long.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-long.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define TYPE v64di
 #include "simd-math-4.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-run.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-4-run.c
index 3b98c0e7738..7a818babc71 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-4-run.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-run.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-short-run.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-4-short-run.c
index 4cbeb97432e..b16ce27b5a3 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-4-short-run.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-short-run.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-4-short.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-short.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-4-short.c
index f010942ffad..0c7fee1aaa9 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-4-short.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-short.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define TYPE v64hi
 #include "simd-math-4.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-4.c
index 833dfe2a866..bbb723fcaa6 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-4.c
@@ -1,6 +1,8 @@
 /* Test that signed division and modulus give the correct result with
    different variations of signedness.  */
 
+/* { dg-require-effective-target vect_int } */
+
 /* Setting it this way ensures the run tests use the same flag as the
    compile tests.  */
 #pragma GCC optimize("O2")
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-16.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-16.c
index 41c116758b4..a30fc48612b 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-16.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-16.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define N 16
 #include "simd-math-5.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-32.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-32.c
index 3fb92b2aab2..f67f29a951c 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-32.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-32.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define N 32
 #include "simd-math-5.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-4.c
index ffcd5120178..046b723c97f 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-4.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define N 4
 #include "simd-math-5.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-8.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-8.c
index 5d855b62752..7fe53032afe 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-8.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-8.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define N 8
 #include "simd-math-5.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-16.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-16.c
index 0ebf640dc8c..6c358dc27df 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-16.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-16.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define TYPE char
 #define N 16
 #include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-32.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-32.c
index 0905f31048c..e1675964a76 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-32.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-32.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define TYPE char
 #define N 32
 #include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-4.c
index 772fe37fe81..3bfd44ae837 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-4.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define TYPE char
 #define N 4
 #include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-8.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-8.c
index 539ce9a7f91..fe612ccfe1b 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-8.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-8.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define TYPE char
 #define N 8
 #include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-16.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-16.c
index 0f1af0858ca..5d3390fb972 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-16.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-16.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-char-16.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-32.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-32.c
index a2794c84a83..cbcd184d7bf 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-32.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-32.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-char-32.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-4.c
index a8e418770ff..ce752f846db 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-4.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-char-4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-8.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-8.c
index 7a6a95922cc..138bd1baec7 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-8.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-8.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-char-8.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run.c
index d3ca775f6a9..3cb1f3671fd 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-char.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c
index e3521ce7ca3..edcb4e37099 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c
@@ -1,5 +1,6 @@
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_int } */
 
 #define TYPE char
 #include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-16.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-16.c
index 659907d8d52..7ec7eebb274 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-16.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-16.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define TYPE long
 #define N 16
 #include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-32.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-32.c
index b03fd092470..c3cbdf74055 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-32.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-32.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define TYPE long
 #define N 32
 #include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-4.c
index a8877b6c63b..0b848cc2013 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-4.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define TYPE long
 #define N 4
 #include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-8.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-8.c
index 5b1106c73af..612d7e7105e 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-8.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-8.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define TYPE long
 #define N 8
 #include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-16.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-16.c
index 20919255404..1c4ef965324 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-16.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-16.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-long-16.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-32.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-32.c
index c7ff7ca52b9..ed194742243 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-32.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-32.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-long-32.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-4.c
index c6cf3344ec4..25179ca8d2b 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-4.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-long-4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-8.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-8.c
index 85fdf6ffe1b..128a8d5a4ea 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-8.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-8.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-long-8.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run.c
index b948fa08c7e..679b9bfa3c9 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-long.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c
index 96a9fd3e734..a7a0e0d91b5 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c
@@ -1,5 +1,6 @@
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_int } */
 
 #define TYPE long
 #include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-16.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-16.c
index 20919255404..1c4ef965324 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-16.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-16.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-long-16.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-32.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-32.c
index c7ff7ca52b9..ed194742243 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-32.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-32.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-long-32.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-4.c
index c6cf3344ec4..25179ca8d2b 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-4.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-long-4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-8.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-8.c
index 85fdf6ffe1b..128a8d5a4ea 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-8.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-8.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-long-8.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-run.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-run.c
index de6504c737c..3ea40b3d2e9 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-run.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-run.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-16.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-16.c
index 5d5953bc604..345cff8949a 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-16.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-16.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define TYPE short
 #define N 16
 #include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-32.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-32.c
index bf8a3addfc4..91147b29ba2 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-32.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-32.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define TYPE short
 #define N 32
 #include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-4.c
index a2cb46c8646..65701710605 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-4.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define TYPE short
 #define N 4
 #include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-8.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-8.c
index fa343e5262e..1dcbf76294d 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-8.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-8.c
@@ -1,3 +1,4 @@
+/* { dg-require-effective-target vect_int } */
 #define TYPE short
 #define N 8
 #include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-16.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-16.c
index 3fc946e2e09..5e314b4b7cd 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-16.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-16.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-short-16.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-32.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-32.c
index 34b1d75fa8e..20cc263a7ad 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-32.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-32.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-short-32.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-4.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-4.c
index 09385c78bc4..612160dd70e 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-4.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-4.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-short-4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-8.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-8.c
index 1de4d2631b3..ccd1b851476 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-8.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-8.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-short-8.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run.c
index 2e0c490fdd9..72dbbea78ee 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run.c
@@ -1,2 +1,3 @@
 /* { dg-do run } */
+/* { dg-require-effective-target vect_int } */
 #include "simd-math-5-short.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c
index c0bff40380a..3a8fadc9ee7 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c
@@ -1,5 +1,6 @@
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_int } */
 
 #define TYPE short
 #include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5.c 
b/gcc/testsuite/gcc.target/gcn/simd-math-5.c
index b5c5dc9f288..2316a89ef90 100644
--- a/gcc/testsuite/gcc.target/gcn/simd-math-5.c
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5.c
@@ -3,6 +3,7 @@
 
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_int } */
 
 /* Setting it this way ensures the run tests use the same flag as the
    compile tests.  */
diff --git a/gcc/testsuite/gcc.target/gcn/smax_1.c 
b/gcc/testsuite/gcc.target/gcn/smax_1.c
index eec050caf71..9f4d76b6c00 100644
--- a/gcc/testsuite/gcc.target/gcn/smax_1.c
+++ b/gcc/testsuite/gcc.target/gcn/smax_1.c
@@ -2,6 +2,7 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_int } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/gcn/smax_1_run.c 
b/gcc/testsuite/gcc.target/gcn/smax_1_run.c
index 4f975916229..1181c0fc96e 100644
--- a/gcc/testsuite/gcc.target/gcn/smax_1_run.c
+++ b/gcc/testsuite/gcc.target/gcn/smax_1_run.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_int } */
 
 #include "smax_1.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/smin_1.c 
b/gcc/testsuite/gcc.target/gcn/smin_1.c
index 8aa8cbb9db8..f8423ffeff9 100644
--- a/gcc/testsuite/gcc.target/gcn/smin_1.c
+++ b/gcc/testsuite/gcc.target/gcn/smin_1.c
@@ -2,6 +2,7 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_int } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/gcn/smin_1_run.c 
b/gcc/testsuite/gcc.target/gcn/smin_1_run.c
index 6758d571fe2..29071834c89 100644
--- a/gcc/testsuite/gcc.target/gcn/smin_1_run.c
+++ b/gcc/testsuite/gcc.target/gcn/smin_1_run.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_int } */
 
 #include "smin_1.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/sram-ecc-3.c 
b/gcc/testsuite/gcc.target/gcn/sram-ecc-3.c
index bc89e3542d2..da5405537cb 100644
--- a/gcc/testsuite/gcc.target/gcn/sram-ecc-3.c
+++ b/gcc/testsuite/gcc.target/gcn/sram-ecc-3.c
@@ -4,6 +4,7 @@
 
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp -msram-ecc=off" } */
+/* { dg-require-effective-target vect_int } */
 
 typedef unsigned int v64si __attribute__ ((vector_size (64*4)));
 typedef unsigned char v64qi __attribute__ ((vector_size (64*1)));
diff --git a/gcc/testsuite/gcc.target/gcn/sram-ecc-4.c 
b/gcc/testsuite/gcc.target/gcn/sram-ecc-4.c
index ff7e2d0bda5..8b509fbfce2 100644
--- a/gcc/testsuite/gcc.target/gcn/sram-ecc-4.c
+++ b/gcc/testsuite/gcc.target/gcn/sram-ecc-4.c
@@ -4,6 +4,7 @@
 
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp -msram-ecc=off" } */
+/* { dg-require-effective-target vect_int } */
 
 typedef unsigned int v64si __attribute__ ((vector_size (64*4)));
 typedef unsigned short v64hi __attribute__ ((vector_size (64*2)));
diff --git a/gcc/testsuite/gcc.target/gcn/sram-ecc-7.c 
b/gcc/testsuite/gcc.target/gcn/sram-ecc-7.c
index 8d363970ffb..426f5c0e55a 100644
--- a/gcc/testsuite/gcc.target/gcn/sram-ecc-7.c
+++ b/gcc/testsuite/gcc.target/gcn/sram-ecc-7.c
@@ -4,6 +4,7 @@
 
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp -msram-ecc=any" } */
+/* { dg-require-effective-target vect_int } */
 
 typedef unsigned int v64si __attribute__ ((vector_size (64*4)));
 typedef unsigned char v64qi __attribute__ ((vector_size (64*1)));
diff --git a/gcc/testsuite/gcc.target/gcn/sram-ecc-8.c 
b/gcc/testsuite/gcc.target/gcn/sram-ecc-8.c
index a2b25076ed1..23d1c7d1161 100644
--- a/gcc/testsuite/gcc.target/gcn/sram-ecc-8.c
+++ b/gcc/testsuite/gcc.target/gcn/sram-ecc-8.c
@@ -4,6 +4,7 @@
 
 /* { dg-do compile } */
 /* { dg-options "-O2 -ftree-vectorize -dp -msram-ecc=any" } */
+/* { dg-require-effective-target vect_int } */
 
 typedef unsigned int v64si __attribute__ ((vector_size (64*4)));
 typedef unsigned short v64hi __attribute__ ((vector_size (64*2)));
diff --git a/gcc/testsuite/gcc.target/gcn/umax_1.c 
b/gcc/testsuite/gcc.target/gcn/umax_1.c
index 934bf9a4a7c..48d2cec0150 100644
--- a/gcc/testsuite/gcc.target/gcn/umax_1.c
+++ b/gcc/testsuite/gcc.target/gcn/umax_1.c
@@ -2,6 +2,7 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_int } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/gcn/umax_1_run.c 
b/gcc/testsuite/gcc.target/gcn/umax_1_run.c
index b8ff54044fd..7e5e644eae1 100644
--- a/gcc/testsuite/gcc.target/gcn/umax_1_run.c
+++ b/gcc/testsuite/gcc.target/gcn/umax_1_run.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_int } */
 
 #include "umax_1.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/umin_1.c 
b/gcc/testsuite/gcc.target/gcn/umin_1.c
index 44343bd44cf..78a28e4b391 100644
--- a/gcc/testsuite/gcc.target/gcn/umin_1.c
+++ b/gcc/testsuite/gcc.target/gcn/umin_1.c
@@ -2,6 +2,7 @@
 /* { dg-options "-O2 -ftree-vectorize -dp" } */
 /* The 'scan-assembler' directives are specific to 64-lane vectors.
    { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */
+/* { dg-require-effective-target vect_int } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/gcn/umin_1_run.c 
b/gcc/testsuite/gcc.target/gcn/umin_1_run.c
index a15d7b3982a..7c40422d89a 100644
--- a/gcc/testsuite/gcc.target/gcn/umin_1_run.c
+++ b/gcc/testsuite/gcc.target/gcn/umin_1_run.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-require-effective-target vect_int } */
 
 #include "umin_1.c"
 
diff --git a/gcc/testsuite/gcc.target/gcn/vcc-clobber.c 
b/gcc/testsuite/gcc.target/gcn/vcc-clobber.c
index e52733cf1e5..df8b6721078 100644
--- a/gcc/testsuite/gcc.target/gcn/vcc-clobber.c
+++ b/gcc/testsuite/gcc.target/gcn/vcc-clobber.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2" } */
+/* { dg-require-effective-target vect_int } */
 
 /* Test that gcn_expand_scalar_to_vector_address does not clobber VCC.
    If it does then spills and reloads will be unsafe, leading to unexpected
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index a29d3bd89f5..0c137458743 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4720,7 +4720,7 @@ proc check_effective_target_vect_int { } {
       expr {
         [check_effective_target_x86]
         || [istarget powerpc*-*-*]
-        || [istarget amdgcn-*-*]
+        || [check_effective_target_amdgcn_simd]
         || [istarget sparc*-*-*]
         || [istarget alpha*-*-*]
         || [istarget ia64-*-*]
@@ -4763,7 +4763,7 @@ proc check_effective_target_vect_early_break { } {
        [istarget aarch64*-*-*]
        || [check_effective_target_arm_v8_neon_ok]
        || [check_effective_target_sse4]
-       || [istarget amdgcn-*-*]
+       || [check_effective_target_amdgcn_simd]
        || [check_effective_target_riscv_v]
        || [check_effective_target_loongarch_sx]
        || ([istarget s390*-*-*]
@@ -4782,7 +4782,7 @@ proc check_effective_target_vect_early_break_hw { } {
        [istarget aarch64*-*-*]
        || [check_effective_target_arm_v8_neon_hw]
        || [check_sse4_hw_available]
-       || [istarget amdgcn-*-*]
+       || [check_effective_target_amdgcn_simd]
        || [check_effective_target_riscv_v_ok]
        || [check_effective_target_loongarch_sx_hw]
        || ([istarget s390*-*-*]
@@ -4928,7 +4928,7 @@ proc check_effective_target_vect_intfloat_cvt { } {
             || [is-effective-target arm_neon]
             || ([istarget mips*-*-*]
                 && [et-is-effective-target mips_msa])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vxe2])
             || ([istarget riscv*-*-*]
@@ -5028,7 +5028,7 @@ proc check_effective_target_vect_uintfloat_cvt { } {
             || [is-effective-target arm_neon]
             || ([istarget mips*-*-*]
                 && [et-is-effective-target mips_msa])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vxe2])
             || ([istarget riscv*-*-*]
@@ -5048,7 +5048,7 @@ proc check_effective_target_vect_floatint_cvt { } {
             || [is-effective-target arm_neon]
             || ([istarget mips*-*-*]
                 && [et-is-effective-target mips_msa])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vxe2])
             || ([istarget riscv*-*-*]
@@ -5066,7 +5066,7 @@ proc check_effective_target_vect_floatuint_cvt { } {
            || [is-effective-target arm_neon]
            || ([istarget mips*-*-*]
                && [et-is-effective-target mips_msa])
-           || [istarget amdgcn-*-*]
+           || [check_effective_target_amdgcn_simd]
            || ([istarget s390*-*-*]
                && [check_effective_target_s390_vxe2])
            || ([istarget riscv*-*-*]
@@ -5108,7 +5108,7 @@ proc check_effective_target_vect_simd_clones { } {
     return [check_cached_effective_target vect_simd_clones {
       expr { ([check_effective_target_x86]
              && [check_effective_target_avx512f])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || [istarget aarch64*-*-*] }}]
 }
 
@@ -8594,7 +8594,7 @@ proc check_effective_target_vect_shift { } {
                     || [et-is-effective-target mips_loongson_mmi]))
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget riscv*-*-*]
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
@@ -8626,7 +8626,7 @@ proc check_effective_target_whole_vector_shift { } {
             && [et-is-effective-target mips_loongson_mmi])
         || ([istarget s390*-*-*]
             && [check_effective_target_s390_vx])
-        || [istarget amdgcn-*-*]
+        || [check_effective_target_amdgcn_simd]
         || ([istarget riscv*-*-*]
             && [check_effective_target_riscv_v])
         || ([istarget loongarch*-*-*]
@@ -8646,7 +8646,7 @@ proc check_effective_target_vect_bswap { } {
     return [check_cached_effective_target vect_bswap {
       expr { ([istarget aarch64*-*-*]
              || [is-effective-target arm_neon]
-             || [istarget amdgcn-*-*])
+             || [check_effective_target_amdgcn_simd])
              || [istarget loongarch*-*-*]
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx]) }}]
@@ -8674,7 +8674,7 @@ proc check_effective_target_vect_char_add { } {
       expr {
         [check_effective_target_x86]
         || [istarget powerpc*-*-*]
-        || [istarget amdgcn-*-*]
+        || [check_effective_target_amdgcn_simd]
         || [istarget ia64-*-*]
         || [istarget aarch64*-*-*]
         || [is-effective-target arm_neon]
@@ -8700,7 +8700,7 @@ proc check_effective_target_vect_shift_char { } {
                 && [et-is-effective-target mips_msa])
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget riscv*-*-*]
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
@@ -8722,7 +8722,7 @@ proc check_effective_target_vect_long { } {
              && [et-is-effective-target mips_msa])
         || ([istarget s390*-*-*]
             && [check_effective_target_s390_vx])
-        || [istarget amdgcn-*-*]
+        || [check_effective_target_amdgcn_simd]
         || ([istarget riscv*-*-*]
             && [check_effective_target_riscv_v])
         || ([istarget loongarch*-*-*]
@@ -8754,7 +8754,7 @@ proc check_effective_target_vect_float { } {
             || [is-effective-target arm_neon]
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vxe])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget riscv*-*-*]
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
@@ -8787,7 +8787,7 @@ proc check_effective_target_vect_double { } {
                 && [et-is-effective-target mips_msa])
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget riscv*-*-*]
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
@@ -8821,7 +8821,7 @@ proc check_effective_target_vect_long_long { } {
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
                 && [check_effective_target_loongarch_sx])
-            || [istarget amdgcn-*-*] }}]
+            || [check_effective_target_amdgcn_simd] }}]
 }
 
 
@@ -8874,7 +8874,7 @@ proc check_effective_target_vect_perm { } {
                     || [et-is-effective-target mips_msa]))
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget riscv*-*-*]
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
@@ -8971,7 +8971,7 @@ proc check_effective_target_vect_perm_byte { } {
                 && [et-is-effective-target mips_msa])
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget riscv*-*-*]
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
@@ -9004,7 +9004,7 @@ proc check_effective_target_vect_perm_short { } {
                  && [et-is-effective-target mips_msa])
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget riscv*-*-*]
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
@@ -9130,7 +9130,7 @@ proc check_effective_target_vect_widen_mult_qi_to_hi { } {
                  || [is-effective-target arm_neon]
                  || ([istarget s390*-*-*]
                      && [check_effective_target_s390_vx]))
-             || [istarget amdgcn-*-*] }}]
+             || [check_effective_target_amdgcn_simd] }}]
 }
 
 # Return 1 if the target plus current options supports a vector
@@ -9154,7 +9154,7 @@ proc check_effective_target_vect_widen_mult_hi_to_si { } {
                 || [is-effective-target arm_neon]
                 || ([istarget s390*-*-*]
                     && [check_effective_target_s390_vx]))
-            || [istarget amdgcn-*-*] }}]
+            || [check_effective_target_amdgcn_simd] }}]
 }
 
 # Return 1 if the target plus current options supports a vector
@@ -9170,7 +9170,7 @@ proc 
check_effective_target_vect_widen_mult_qi_to_hi_pattern { } {
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
             || [istarget loongarch*-*-*]
-            || [istarget amdgcn-*-*] }}]
+            || [check_effective_target_amdgcn_simd] }}]
 }
 
 # Return 1 if the target plus current options supports a vector
@@ -9188,7 +9188,7 @@ proc 
check_effective_target_vect_widen_mult_hi_to_si_pattern { } {
                 && [check_effective_target_arm_little_endian])
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
-            || [istarget amdgcn-*-*] }}]
+            || [check_effective_target_amdgcn_simd] }}]
 }
 
 # Return 1 if the target plus current options supports a vector
@@ -9377,7 +9377,7 @@ proc check_effective_target_vect_pack_trunc { } {
                 && [et-is-effective-target mips_msa])
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
-            || [istarget amdgcn*-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget riscv*-*-*]
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
@@ -9401,7 +9401,7 @@ proc check_effective_target_vect_unpack { } {
                 && [check_effective_target_arm_little_endian])
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
-            || [istarget amdgcn*-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget riscv*-*-*]
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
@@ -9447,7 +9447,7 @@ proc check_effective_target_vect_hw_misalign { } {
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
             || ([istarget loongarch*-*-*])
-            || [istarget amdgcn*-*-*] } {
+            || [check_effective_target_amdgcn_simd] } {
          return 1
        }
        if { [istarget arm*-*-*]
@@ -9537,7 +9537,7 @@ proc check_effective_target_vect_natural_alignment { } {
     if { [check_effective_target_arm_eabi]
         || [istarget nvptx-*-*]
         || [istarget s390*-*-*]
-        || [istarget amdgcn-*-*] } {
+        || [check_effective_target_amdgcn_simd] } {
        set et_vect_natural_alignment 0
     }
     verbose "check_effective_target_vect_natural_alignment:\
@@ -9556,7 +9556,7 @@ proc check_effective_target_vect_check_ptrs { } {
 
 proc check_effective_target_vect_fully_masked { } {
     return [expr { [check_effective_target_aarch64_sve]
-                  || [istarget amdgcn*-*-*]
+                  || [check_effective_target_amdgcn_simd]
                   || [check_effective_target_riscv_v] }]
 }
 
@@ -10042,7 +10042,7 @@ proc check_effective_target_vect_load_lanes { } {
 proc check_effective_target_vect_masked_load { } {
     return [expr { [check_avx_available]
                   || [check_effective_target_aarch64_sve]
-                  || [istarget amdgcn*-*-*]
+                  || [check_effective_target_amdgcn_simd]
                   || [check_effective_target_riscv_v] } ]
 }
 
@@ -10051,7 +10051,7 @@ proc check_effective_target_vect_masked_load { } {
 proc check_effective_target_vect_masked_store { } {
     return [expr { [check_avx_available]
                   || [check_effective_target_aarch64_sve]
-                  || [istarget amdgcn*-*-*]
+                  || [check_effective_target_amdgcn_simd]
                   || [check_effective_target_riscv_v] }]
 }
 
@@ -10059,7 +10059,7 @@ proc check_effective_target_vect_masked_store { } {
 
 proc check_effective_target_vect_gather_load_ifn { } {
     return [expr { [check_effective_target_aarch64_sve]
-                  || [istarget amdgcn*-*-*]
+                  || [check_effective_target_amdgcn_simd]
                   || [check_effective_target_riscv_v] }]
 }
 
@@ -10067,7 +10067,7 @@ proc check_effective_target_vect_gather_load_ifn { } {
 
 proc check_effective_target_vect_scatter_store { } {
     return [expr { [check_effective_target_aarch64_sve]
-                  || [istarget amdgcn*-*-*]
+                  || [check_effective_target_amdgcn_simd]
                   || [check_effective_target_riscv_v]
                   || [check_effective_target_loongarch_sx] }]
 }
@@ -10085,7 +10085,7 @@ proc check_effective_target_vect_condition { } {
             || [check_effective_target_arm_neon_ok]
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget riscv*-*-*]
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
@@ -10105,7 +10105,7 @@ proc check_effective_target_vect_cond_mixed { } {
                 && [et-is-effective-target mips_msa])
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget riscv*-*-*]
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
@@ -10125,7 +10125,7 @@ proc check_effective_target_vect_char_mult { } {
                 && [et-is-effective-target mips_msa])
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget riscv*-*-*]
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
@@ -10146,7 +10146,7 @@ proc check_effective_target_vect_short_mult { } {
                     || [et-is-effective-target mips_loongson_mmi]))
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget riscv*-*-*]
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
@@ -10166,7 +10166,7 @@ proc check_effective_target_vect_int_mult { } {
             || [check_effective_target_arm32]
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget riscv*-*-*]
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
@@ -10195,7 +10195,7 @@ proc check_effective_target_vect_long_mult { } {
              && [check_effective_target_riscv_v])
         || ([istarget loongarch*-*-*]
              && [check_effective_target_loongarch_sx])
-        || [istarget amdgcn-*-*] } {
+        || [check_effective_target_amdgcn_simd] } {
        set answer 1
     } else {
        set answer 0
@@ -10364,7 +10364,7 @@ proc check_effective_target_vect_call_copysignf { } {
       expr { [check_effective_target_x86]
             || [istarget powerpc*-*-*]
             || [istarget aarch64*-*-*]
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget riscv*-*-*]
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
@@ -10405,7 +10405,7 @@ proc check_effective_target_vect_call_sqrtf { } {
             || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
             || ([istarget s390*-*-*]
                 && [check_effective_target_s390_vx])
-            || [istarget amdgcn-*-*]
+            || [check_effective_target_amdgcn_simd]
             || ([istarget riscv*-*-*]
                 && [check_effective_target_riscv_v])
             || ([istarget loongarch*-*-*]
@@ -10418,7 +10418,7 @@ proc check_effective_target_vect_call_lrint { } {
     set et_vect_call_lrint 0
     if { ([check_effective_target_x86]
          && [check_effective_target_ilp32])
-        || [istarget amdgcn-*-*]
+        || [check_effective_target_amdgcn_simd]
         || [istarget loongarch*-*-*] } {
        set et_vect_call_lrint 1
     }
@@ -10432,7 +10432,7 @@ proc check_effective_target_vect_call_lrint { } {
 proc check_effective_target_vect_call_btrunc { } {
     return [check_cached_effective_target vect_call_btrunc {
       expr { [istarget aarch64*-*-*]
-            || [istarget amdgcn-*-*] }}]
+            || [check_effective_target_amdgcn_simd] }}]
 }
 
 # Return 1 if the target supports vector btruncf calls.
@@ -10440,7 +10440,7 @@ proc check_effective_target_vect_call_btrunc { } {
 proc check_effective_target_vect_call_btruncf { } {
     return [check_cached_effective_target vect_call_btruncf {
       expr { [istarget aarch64*-*-*]
-            || [istarget amdgcn-*-*] }}]
+            || [check_effective_target_amdgcn_simd] }}]
 }
 
 # Return 1 if the target supports vector ceil calls.
@@ -10448,7 +10448,7 @@ proc check_effective_target_vect_call_btruncf { } {
 proc check_effective_target_vect_call_ceil { } {
     return [check_cached_effective_target vect_call_ceil {
       expr { [istarget aarch64*-*-*]
-            || [istarget amdgcn-*-*] }}]
+            || [check_effective_target_amdgcn_simd] }}]
 }
 
 # Return 1 if the target supports vector ceilf calls.
@@ -10456,7 +10456,7 @@ proc check_effective_target_vect_call_ceil { } {
 proc check_effective_target_vect_call_ceilf { } {
     return [check_cached_effective_target vect_call_ceilf {
       expr { [istarget aarch64*-*-*]
-            || [istarget amdgcn-*-*] }}]
+            || [check_effective_target_amdgcn_simd] }}]
 }
 
 # Return 1 if the target supports vector floor calls.
@@ -10464,7 +10464,7 @@ proc check_effective_target_vect_call_ceilf { } {
 proc check_effective_target_vect_call_floor { } {
     return [check_cached_effective_target vect_call_floor {
       expr { [istarget aarch64*-*-*]
-            || [istarget amdgcn-*-*] }}]
+            || [check_effective_target_amdgcn_simd] }}]
 }
 
 # Return 1 if the target supports vector floorf calls.
@@ -10472,7 +10472,7 @@ proc check_effective_target_vect_call_floor { } {
 proc check_effective_target_vect_call_floorf { } {
     return [check_cached_effective_target vect_call_floorf {
       expr { [istarget aarch64*-*-*]
-            || [istarget amdgcn-*-*] }}]
+            || [check_effective_target_amdgcn_simd] }}]
 }
 
 # Return 1 if the target supports vector lceil calls.
@@ -10521,7 +10521,7 @@ proc check_effective_target_vect_call_roundf { } {
 
 proc check_effective_target_vect_logical_reduc { } {
     return [expr { [check_effective_target_aarch64_sve]
-                  || [istarget amdgcn-*-*]
+                  || [check_effective_target_amdgcn_simd]
                   || [check_effective_target_riscv_v]
                   || [check_effective_target_loongarch_sx]
                   || [check_effective_target_x86]
@@ -10532,7 +10532,7 @@ proc check_effective_target_vect_logical_reduc { } {
 
 proc check_effective_target_vect_fold_extract_last { } {
     return [expr { [check_effective_target_aarch64_sve]
-                  || [istarget amdgcn*-*-*]
+                  || [check_effective_target_amdgcn_simd]
                   || [check_effective_target_riscv_v] }]
 }
 
@@ -13002,6 +13002,9 @@ proc check_vect_support_and_set_flags { } {
            set dg-do-what-default compile
        }
     } elseif [istarget amdgcn-*-*] {
+       if { ![check_effective_target_amdgcn_simd] } {
+         return 0
+       }
        set dg-do-what-default run
     } elseif [istarget riscv*-*-*] {
        if [check_effective_target_riscv_v] {
@@ -15062,3 +15065,31 @@ proc check_effective_target_can_deref_null { } {
        }
       } "-O0 -fno-delete-null-pointer-checks -Wno-null-dereference"]
 }
+
+# Return 1 if the target is amdgcn and is building in SIMD mode.
+# The vector modes only exist in SIMD mode, so the vect_* effective targets
+# use this to decide whether amdgcn has vectors at all.
+
+proc check_effective_target_amdgcn_simd { } {
+    if { ![istarget amdgcn-*-*] } {
+       return 0
+    }
+    return [check_no_compiler_messages amdgcn_simd_ assembly {
+       #ifdef __SIMT__
+       #error "not simd"
+       #endif
+    }]
+}
+
+# Return 1 if the target is amdgcn and is building in SIMT mode
+
+proc check_effective_target_amdgcn_simt { } {
+    if { ![istarget amdgcn-*-*] } {
+       return 0
+    }
+    return [check_no_compiler_messages amdgcn_simt_ assembly {
+       #ifndef __SIMT__
+       #error "not simt"
+       #endif
+    }]
+}
-- 
2.54.0