This patch adds intrinsic and auto vectorization (vec_perm) support for xxtvarith, which is one of XuanTie's vendor vector extensions [1]. This extension include xt.vile (vector interleave even) and xt.vilo (vector interleave odd) instructions, that can be used for vector permutations like [0, 8, 2, 10, 4, 12, 6, 14]. When SEW is smaller than ELEN, a wider SEW may be used to generate code for permutations like [0, 1, 8, 9, 4, 5, 12, 13]. They can be useful for transpose operations in workloads like x264.
Note that Zvzip also has similar instructions. The same optimizations can be applied when Zvzip becomes available. Regtested on rv64gcv and rv32gcv, no regression. [1] https://github.com/XUANTIE-RV/thead-extension-spec/blob/master/xxtvarith.adoc gcc/ChangeLog: * config.gcc: Add xuantie-vector-builtins-bases.o and xuantie_vector.h. * config/riscv/riscv-cores.def (RISCV_CORE): Add xxtvarith to C950 arch string. * config/riscv/riscv-ext.def: Include riscv-ext-xuantie.def. * config/riscv/riscv-ext.opt: Regenerate. * config/riscv/riscv-v.cc (shuffle_interleave_even_odd_patterns): New function. (expand_vec_perm_const_1): Add even-odd interleave case. * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_DIU_OPS): New macro. * config/riscv/riscv-vector-builtins.cc (DEF_RVV_DIU_OPS): New. (function_groups): Include xuantie-vector-builtins-functions.def. (get_builtin_partition): Add XXTVARITH_EXT case. * config/riscv/riscv-vector-builtins.h (enum required_ext): Add XXTVARITH_EXT. (enum rvv_builtin_partition): Add RVV_PARTITION_XXTVARITH. (required_ext_to_isa_name): Add XXTVARITH_EXT case. (required_extensions_specified): Ditto. * config/riscv/t-riscv: Add new files. * config/riscv/vector.md: Include xuantie-vector.md. * doc/riscv-ext.texi: Regenerate. * config/riscv/riscv-ext-xuantie.def: New file. * config/riscv/xuantie-vector-builtins-bases.cc: New file. * config/riscv/xuantie-vector-builtins-bases.h: New file. * config/riscv/xuantie-vector-builtins-functions.def: New file. * config/riscv/xuantie-vector.md: New file. * config/riscv/xuantie_vector.h: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/intrinsic-detection.c: Add new ext. * gcc.target/riscv/rvv/rvv.exp: Include xxtvector directory. * gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-2x-run.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-2x-xxtvarith.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-2x.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-run.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-xxtvarith.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd.c: New test. * gcc.target/riscv/rvv/xxtvector/xuantie_vector.h: New test. * gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldn_vv_non_overloaded.c: New test. * gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldn_vv_overloaded.c: New test. * gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldr_vv_non_overloaded.c: New test. * gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldr_vv_overloaded.c: New test. * gcc.target/riscv/rvv/xxtvector/xxtvarith_vgmulxor_vv_non_overloaded.c: New test. * gcc.target/riscv/rvv/xxtvector/xxtvarith_vgmulxor_vv_overloaded.c: New test. * gcc.target/riscv/rvv/xxtvector/xxtvarith_vile_vv_non_overloaded.c: New test. * gcc.target/riscv/rvv/xxtvector/xxtvarith_vile_vv_overloaded.c: New test. * gcc.target/riscv/rvv/xxtvector/xxtvarith_vilo_vv_non_overloaded.c: New test. * gcc.target/riscv/rvv/xxtvector/xxtvarith_vilo_vv_overloaded.c: New test. Co-authored-by: Jin Ma <[email protected]> Co-authored-by: Yunze Zhu <[email protected]> --- gcc/config.gcc | 4 +- gcc/config/riscv/riscv-cores.def | 2 +- gcc/config/riscv/riscv-ext-xuantie.def | 35 ++ gcc/config/riscv/riscv-ext.def | 1 + gcc/config/riscv/riscv-ext.opt | 11 +- gcc/config/riscv/riscv-v.cc | 81 +++ .../riscv/riscv-vector-builtins-types.def | 16 + gcc/config/riscv/riscv-vector-builtins.cc | 24 + gcc/config/riscv/riscv-vector-builtins.h | 6 + gcc/config/riscv/t-riscv | 20 +- gcc/config/riscv/vector.md | 1 + .../riscv/xuantie-vector-builtins-bases.cc | 89 +++ .../riscv/xuantie-vector-builtins-bases.h | 37 ++ .../xuantie-vector-builtins-functions.def | 47 ++ gcc/config/riscv/xuantie-vector.md | 115 ++++ gcc/config/riscv/xuantie_vector.h | 34 ++ gcc/doc/riscv-ext.texi | 4 + .../shuffle-interleave-evenodd-2x-run.c | 105 ++++ .../shuffle-interleave-evenodd-2x-xxtvarith.c | 7 + .../vls-vlmax/shuffle-interleave-evenodd-2x.c | 61 ++ .../shuffle-interleave-evenodd-run.c | 122 ++++ .../shuffle-interleave-evenodd-xxtvarith.c | 7 + .../vls-vlmax/shuffle-interleave-evenodd.c | 67 +++ .../riscv/rvv/base/intrinsic-detection.c | 7 +- gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 + .../riscv/rvv/xxtvector/xuantie_vector.h | 11 + .../xxtvarith_vcrcfoldn_vv_non_overloaded.c | 119 ++++ .../xxtvarith_vcrcfoldn_vv_overloaded.c | 107 ++++ .../xxtvarith_vcrcfoldr_vv_non_overloaded.c | 119 ++++ .../xxtvarith_vcrcfoldr_vv_overloaded.c | 107 ++++ .../xxtvarith_vgmulxor_vv_non_overloaded.c | 101 ++++ .../xxtvarith_vgmulxor_vv_overloaded.c | 91 +++ .../xxtvarith_vile_vv_non_overloaded.c | 556 ++++++++++++++++++ .../xxtvector/xxtvarith_vile_vv_overloaded.c | 535 +++++++++++++++++ .../xxtvarith_vilo_vv_non_overloaded.c | 556 ++++++++++++++++++ .../xxtvector/xxtvarith_vilo_vv_overloaded.c | 535 +++++++++++++++++ 36 files changed, 3733 insertions(+), 9 deletions(-) create mode 100644 gcc/config/riscv/riscv-ext-xuantie.def create mode 100644 gcc/config/riscv/xuantie-vector-builtins-bases.cc create mode 100644 gcc/config/riscv/xuantie-vector-builtins-bases.h create mode 100644 gcc/config/riscv/xuantie-vector-builtins-functions.def create mode 100644 gcc/config/riscv/xuantie-vector.md create mode 100644 gcc/config/riscv/xuantie_vector.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-2x-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-2x-xxtvarith.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-2x.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-xxtvarith.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xuantie_vector.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldn_vv_non_overloaded.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldn_vv_overloaded.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldr_vv_non_overloaded.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldr_vv_overloaded.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vgmulxor_vv_non_overloaded.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vgmulxor_vv_overloaded.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vile_vv_non_overloaded.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vile_vv_overloaded.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vilo_vv_non_overloaded.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vilo_vv_overloaded.c diff --git a/gcc/config.gcc b/gcc/config.gcc index e600ae272db..6973932260a 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -574,10 +574,10 @@ riscv*) cpu_type=riscv extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-string.o" extra_objs="${extra_objs} riscv-v.o riscv-vsetvl.o riscv-vector-costs.o riscv-avlprop.o riscv-vect-permconst.o" - extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o sifive-vector-builtins-bases.o andes-vector-builtins-bases.o" + extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o sifive-vector-builtins-bases.o andes-vector-builtins-bases.o xuantie-vector-builtins-bases.o" extra_objs="${extra_objs} thead.o riscv-target-attr.o riscv-zicfilp.o riscv-bclr-lowest-set-bit.o riscv-opt-popretz.o riscv-fusion.o" d_target_objs="riscv-d.o" - extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h riscv_th_vector.h sifive_vector.h andes_vector.h" + extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h riscv_th_vector.h sifive_vector.h andes_vector.h xuantie_vector.h" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.h" extra_options="${extra_options} riscv/riscv-ext.opt" diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 7e10a3839c1..e8416498d66 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -266,7 +266,7 @@ RISCV_CORE("xt-c9501fdvt", "rva23s64_zfbfmin_zfh_zicfilp_zicfiss_zkr_zmmul_" "zvkng_zvknha_zvknhb_zvksc_zvksed_zvksg_zvksh_" "zvl256b_smaia_smcntrpmf_smcsrind_smepmp_smmpm_" "smnpm_smrnmi_ssaia_sscsrind_sspm_ssstrict_" - "svadu_svvptc", + "svadu_svvptc_xxtvarith", "xt-c9501fdvt", /* MVENDORID */ UNKNOWN_ID, /* MARCHID */ UNKNOWN_ID, diff --git a/gcc/config/riscv/riscv-ext-xuantie.def b/gcc/config/riscv/riscv-ext-xuantie.def new file mode 100644 index 00000000000..93011965133 --- /dev/null +++ b/gcc/config/riscv/riscv-ext-xuantie.def @@ -0,0 +1,35 @@ +/* XuanTie extension definition file for RISC-V. + Copyright (C) 2026 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. + +Please run `make riscv-regen` in build folder to make sure updated anything. + +Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */ + +DEFINE_RISCV_EXT( + /* NAME */ xxtvarith, + /* UPPERCASE_NAME */ XXTVARITH, + /* FULL_NAME */ "XuanTie vector arith turbo extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"v"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xxt, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def index eeee99da77e..e7b42edb4e4 100644 --- a/gcc/config/riscv/riscv-ext.def +++ b/gcc/config/riscv/riscv-ext.def @@ -2233,3 +2233,4 @@ DEFINE_RISCV_EXT( #include "riscv-ext-mips.def" #include "riscv-ext-andes.def" #include "riscv-ext-spacemit.def" +#include "riscv-ext-xuantie.def" diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt index 8cd7825522b..1967cd27b88 100644 --- a/gcc/config/riscv/riscv-ext.opt +++ b/gcc/config/riscv/riscv-ext.opt @@ -64,6 +64,9 @@ int riscv_xthead_subext TargetVariable int riscv_xventana_subext +TargetVariable +int riscv_xxt_subext + TargetVariable int riscv_za_subext @@ -91,6 +94,9 @@ int riscv_zm_subext TargetVariable int riscv_zt_subext +TargetVariable +int riscv_zvabd_subext + TargetVariable int riscv_zvb_subext @@ -106,9 +112,6 @@ int riscv_zvk_subext TargetVariable int riscv_zvl_subext -TargetVariable -int riscv_zvabd_subext - Mask(RVE) Var(riscv_base_subext) Mask(RVI) Var(riscv_base_subext) @@ -499,3 +502,5 @@ Mask(XSMTVDOT) Var(riscv_xsmt_subext) Mask(XSMTVDOTII) Var(riscv_xsmt_subext) +Mask(XXTVARITH) Var(riscv_xxt_subext) + diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index d98f0a94023..83ab3be7ad0 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -3650,6 +3650,85 @@ shuffle_consecutive_patterns (struct expand_vec_perm_d *d) return true; } +/* Recognize the patterns of th.vile and th.vilo. */ + +static bool +shuffle_interleave_even_odd_patterns (struct expand_vec_perm_d *d) +{ + machine_mode vmode = d->vmode; + poly_int64 vec_len = d->perm.length (); + + if (!TARGET_XXTVARITH) + return false; + + if (!vec_len.is_constant ()) + return false; + + unsigned vlen = vec_len.to_constant (); + + if (vlen < 4 || vlen > 64) + return false; + + if (d->one_vector_p) + return false; + + bool even = false, elen_is_2x = false; + if (d->perm.series_p (0, 2, 0, 2) && d->perm.series_p (1, 2, vlen, 2)) + { + even = true; + elen_is_2x = false; + } + else if (d->perm.series_p (0, 2, 1, 2) + && d->perm.series_p (1, 2, vlen + 1, 2)) + { + even = false; + elen_is_2x = false; + } + else if (d->perm.series_p (0, 4, 0, 4) && d->perm.series_p (1, 4, 1, 4) + && d->perm.series_p (2, 4, vlen, 4) + && d->perm.series_p (3, 4, vlen + 1, 4)) + { + even = true; + elen_is_2x = true; + } + else if (d->perm.series_p (0, 4, 2, 4) && d->perm.series_p (1, 4, 3, 4) + && d->perm.series_p (2, 4, vlen + 2, 4) + && d->perm.series_p (3, 4, vlen + 3, 4)) + { + even = false; + elen_is_2x = true; + } + else + { + return false; + } + + gcc_assert (TARGET_VECTOR_ELEN_64); + if (elen_is_2x && GET_MODE_BITSIZE (GET_MODE_INNER (vmode)) >= 64) + return false; + + /* Success! */ + if (d->testing_p) + return true; + + if (elen_is_2x) + { + unsigned int elen2x = GET_MODE_BITSIZE (GET_MODE_INNER (vmode)) * 2; + scalar_int_mode smode = int_mode_for_size (elen2x, 0).require (); + vmode = get_vector_mode (smode, vlen / 2).require (); + } + + rtx ops[] = {gen_lowpart (vmode, d->target), gen_lowpart (vmode, d->op0), + gen_lowpart (vmode, d->op1)}; + + insn_code icode + = code_for_xt_pred (even ? UNSPEC_XT_VILE : UNSPEC_XT_VILO, vmode); + + emit_vlmax_insn (icode, __NORMAL_OP_TA2 | BINARY_OP_P, ops); + + return true; +} + /* Recognize the patterns that we can use compress operation to shuffle the vectors. The perm selector of compress pattern is divided into 2 part: The first part is the random index number < NUNITS. @@ -4501,6 +4580,8 @@ expand_vec_perm_const_1 (struct expand_vec_perm_d *d) return true; if (shuffle_consecutive_patterns (d)) return true; + if (shuffle_interleave_even_odd_patterns (d)) + return true; if (shuffle_slide_patterns (d)) return true; if (shuffle_interleave_patterns (d)) diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def index 2e952bedca1..9ea89b870bb 100644 --- a/gcc/config/riscv/riscv-vector-builtins-types.def +++ b/gcc/config/riscv/riscv-vector-builtins-types.def @@ -411,6 +411,12 @@ along with GCC; see the file COPYING3. If not see #define DEF_RVV_HU_SU_OPS(TYPE, REQUIRE) #endif +/* Use "DEF_RVV_DIU_OPS" macro include all 64-bit integer which will be iterated + and registered as intrinsic functions. */ +#ifndef DEF_RVV_DIU_OPS +#define DEF_RVV_DIU_OPS(TYPE, REQUIRE) +#endif + DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_ELEN_64) DEF_RVV_I_OPS (vint8mf4_t, 0) DEF_RVV_I_OPS (vint8mf2_t, 0) @@ -1580,6 +1586,15 @@ DEF_RVV_HU_SU_OPS (vuint32m2_t, 0) DEF_RVV_HU_SU_OPS (vuint32m4_t, 0) DEF_RVV_HU_SU_OPS (vuint32m8_t, 0) +DEF_RVV_DIU_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_DIU_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_DIU_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_DIU_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_DIU_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_DIU_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_DIU_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_DIU_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64) + #undef DEF_RVV_I_OPS #undef DEF_RVV_U_OPS #undef DEF_RVV_F_OPS @@ -1643,3 +1658,4 @@ DEF_RVV_HU_SU_OPS (vuint32m8_t, 0) #undef DEF_RVV_F16_OPS #undef DEF_RVV_QU_HU_OPS #undef DEF_RVV_HU_SU_OPS +#undef DEF_RVV_DIU_OPS diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index a7e5c24281f..1d3fe2eaf62 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -53,6 +53,7 @@ #include "riscv-vector-builtins-bases.h" #include "sifive-vector-builtins-bases.h" #include "andes-vector-builtins-bases.h" +#include "xuantie-vector-builtins-bases.h" using namespace riscv_vector; @@ -584,6 +585,12 @@ static const rvv_type_info qu_ops[] = { #include "riscv-vector-builtins-types.def" {NUM_VECTOR_TYPES, 0}}; +/* A list of all v[u]int64m_t will be registered for intrinsic functions. */ +static const rvv_type_info diu_ops[] = { +#define DEF_RVV_DIU_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, +#include "riscv-vector-builtins-types.def" + {NUM_VECTOR_TYPES, 0}}; + /* A list of FP16 will be registered for intrinsic functions. */ static const rvv_type_info f16_ops[] = { #define DEF_RVV_F16_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, @@ -3509,6 +3516,18 @@ static constexpr const rvv_op_info u_s_ops rvv_arg_type_info (RVV_BASE_vector), /* Return type */ x_v_args /* Args */}; +static constexpr const rvv_op_info xt_qu_vvv_ops + = {qu_ops, /* Types */ + OP_TYPE_vv, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + vvv_args /* Args */}; + +static constexpr const rvv_op_info xt_diu_vvvv_ops + = {diu_ops, /* Types */ + OP_TYPE_vv, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + vvv_args /* Args */}; + /* A list of all RVV base function types. */ static constexpr const function_type_info function_types[] = { #define DEF_RVV_TYPE_INDEX( \ @@ -3619,6 +3638,9 @@ static function_group_info function_groups[] = { #define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) \ {#NAME, &bases::NAME, &shapes::SHAPE, PREDS, OPS_INFO, REQUIRED_EXTENSIONS}, #include "andes-vector-builtins-functions.def" +#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) \ + {#NAME, &bases::NAME, &shapes::SHAPE, PREDS, OPS_INFO, REQUIRED_EXTENSIONS}, +#include "xuantie-vector-builtins-functions.def" }; @@ -3742,6 +3764,8 @@ get_builtin_partition (required_ext ext, const function_instance &instance) return RVV_PARTITION_XANDESVPACKFPH; case XANDESVDOT_EXT: return RVV_PARTITION_XANDESVDOT; + case XXTVARITH_EXT: + return RVV_PARTITION_XXTVARITH; default: gcc_unreachable (); } diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h index 8e5cba1e1b6..3cd60cff4f2 100644 --- a/gcc/config/riscv/riscv-vector-builtins.h +++ b/gcc/config/riscv/riscv-vector-builtins.h @@ -140,6 +140,7 @@ enum required_ext XANDESVSINTLOAD_EXT, /* XANDESVSINTLOAD extension */ XANDESVPACKFPH_EXT, /* XANDESVPACKFPH extension */ XANDESVDOT_EXT, /* XANDESVDOT extension */ + XXTVARITH_EXT, /* XXTVARITH extension */ /* Please update required_ext_to_isa_name and required_extensions_specified when adding or removing enum values. */ }; @@ -172,6 +173,7 @@ enum rvv_builtin_partition RVV_PARTITION_XANDESVSINTLOAD, RVV_PARTITION_XANDESVPACKFPH, RVV_PARTITION_XANDESVDOT, + RVV_PARTITION_XXTVARITH, NUM_RVV_EXT_PARTITIONS }; @@ -236,6 +238,8 @@ static inline const char * required_ext_to_isa_name (enum required_ext required) return "xandesvpackfph"; case XANDESVDOT_EXT: return "xandesvdot"; + case XXTVARITH_EXT: + return "xxtvarith"; default: gcc_unreachable (); } @@ -295,6 +299,8 @@ static inline bool required_extensions_specified (enum required_ext required) return TARGET_XANDESVPACKFPH; case XANDESVDOT_EXT: return TARGET_XANDESVDOT; + case XXTVARITH_EXT: + return TARGET_XXTVARITH; default: gcc_unreachable (); } diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv index 2a4a2ccab50..c498b908008 100644 --- a/gcc/config/riscv/t-riscv +++ b/gcc/config/riscv/t-riscv @@ -4,6 +4,7 @@ RISCV_BUILTINS_H = $(srcdir)/config/riscv/riscv-vector-builtins.h \ $(srcdir)/config/riscv/thead-vector-builtins-functions.def \ $(srcdir)/config/riscv/sifive-vector-builtins-functions.def \ $(srcdir)/config/riscv/andes-vector-builtins-functions.def \ + $(srcdir)/config/riscv/xuantie-vector-builtins-functions.def \ riscv-vector-type-indexer.gen.def riscv-builtins.o: $(srcdir)/config/riscv/riscv-builtins.cc $(CONFIG_H) \ @@ -28,8 +29,10 @@ riscv-vector-builtins.o: $(srcdir)/config/riscv/riscv-vector-builtins.cc \ $(srcdir)/config/riscv/riscv-vector-builtins-bases.h \ $(srcdir)/config/riscv/sifive-vector-builtins-bases.h \ $(srcdir)/config/riscv/andes-vector-builtins-bases.h \ + $(srcdir)/config/riscv/xuantie-vector-builtins-bases.h \ $(srcdir)/config/riscv/riscv-vector-builtins-types.def \ $(srcdir)/config/riscv/sifive-vector-builtins-functions.def \ + $(srcdir)/config/riscv/xuantie-vector-builtins-functions.def \ $(RISCV_BUILTINS_H) $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/riscv/riscv-vector-builtins.cc @@ -41,6 +44,7 @@ riscv-vector-builtins-shapes.o: \ $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \ $(srcdir)/config/riscv/riscv-vector-builtins-bases.h \ $(srcdir)/config/riscv/sifive-vector-builtins-bases.h \ + $(srcdir)/config/riscv/xuantie-vector-builtins-bases.h \ $(RISCV_BUILTINS_H) $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/riscv/riscv-vector-builtins-shapes.cc @@ -84,6 +88,19 @@ andes-vector-builtins-bases.o: \ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/riscv/andes-vector-builtins-bases.cc +xuantie-vector-builtins-bases.o: \ + $(srcdir)/config/riscv/xuantie-vector-builtins-bases.cc \ + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) \ + $(TM_P_H) memmodel.h insn-codes.h $(OPTABS_H) $(RECOG_H) \ + $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) fold-const.h $(GIMPLE_H) \ + gimple-iterator.h gimplify.h explow.h $(EMIT_RTL_H) tree-vector-builder.h \ + rtx-vector-builder.h \ + $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \ + $(srcdir)/config/riscv/xuantie-vector-builtins-bases.h \ + $(RISCV_BUILTINS_H) + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(srcdir)/config/riscv/xuantie-vector-builtins-bases.cc + riscv-sr.o: $(srcdir)/config/riscv/riscv-sr.cc $(CONFIG_H) \ $(SYSTEM_H) $(TM_H) $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ @@ -226,7 +243,8 @@ RISCV_EXT_DEFS = \ $(srcdir)/config/riscv/riscv-ext-ventana.def \ $(srcdir)/config/riscv/riscv-ext-mips.def \ $(srcdir)/config/riscv/riscv-ext-andes.def \ - $(srcdir)/config/riscv/riscv-ext-spacemit.def + $(srcdir)/config/riscv/riscv-ext-spacemit.def \ + $(srcdir)/config/riscv/riscv-ext-xuantie.def $(srcdir)/config/riscv/riscv-ext.opt: $(RISCV_EXT_DEFS) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index e760f708faf..8cc7fd61489 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -9310,3 +9310,4 @@ (define_insn "@pred_widen_abd_plus<su><mode>" (include "autovec-opt.md") (include "sifive-vector.md") (include "andes-vector.md") +(include "xuantie-vector.md") diff --git a/gcc/config/riscv/xuantie-vector-builtins-bases.cc b/gcc/config/riscv/xuantie-vector-builtins-bases.cc new file mode 100644 index 00000000000..f7f9c6f05a6 --- /dev/null +++ b/gcc/config/riscv/xuantie-vector-builtins-bases.cc @@ -0,0 +1,89 @@ +/* function_base implementation for XuanTie custom 'V' Extension for GNU compiler. + Copyright (C) 2026 Free Software Foundation, Inc. + Contributed by Alibaba DAMO Academy XuanTie Team. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + <http://www.gnu.org/licenses/>. */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" +#include "tree.h" +#include "rtl.h" +#include "tm_p.h" +#include "memmodel.h" +#include "insn-codes.h" +#include "optabs.h" +#include "recog.h" +#include "expr.h" +#include "basic-block.h" +#include "function.h" +#include "fold-const.h" +#include "gimple.h" +#include "gimple-iterator.h" +#include "gimplify.h" +#include "explow.h" +#include "emit-rtl.h" +#include "tree-vector-builder.h" +#include "rtx-vector-builder.h" +#include "riscv-vector-builtins.h" +#include "riscv-vector-builtins-shapes.h" +#include "xuantie-vector-builtins-bases.h" +#include "riscv-vector-builtins-bases.h" + +using namespace riscv_vector; + +namespace riscv_vector { + +/* XXTVarith */ +/* Implements xt.vgmulxor.vv/xt.vilo.vv/xt.vile.vv/xt.vcrcfoldr.vv + xt.vcrcfoldn.vv. */ +template<int UNSPEC> +class xt_varith : public function_base +{ +public: + bool apply_mask_policy_p () const override { return false; } + bool use_mask_predication_p () const override { return false; } + bool has_merge_operand_p () const override + { + return (UNSPEC == UNSPEC_XT_VILE || UNSPEC == UNSPEC_XT_VILO); + } + rtx expand (function_expander &e) const override + { + return e.use_exact_insn (code_for_xt_pred (UNSPEC, e.vector_mode ())); + } +}; + +/* XXTVarith */ +static constexpr const xt_varith<UNSPEC_XT_VGMULXOR> xt_vgmulxor_obj; +static constexpr const xt_varith<UNSPEC_XT_VILO> xt_vilo_obj; +static constexpr const xt_varith<UNSPEC_XT_VILE> xt_vile_obj; +static constexpr const xt_varith<UNSPEC_XT_VCRCFOLDR> xt_vcrcfoldr_obj; +static constexpr const xt_varith<UNSPEC_XT_VCRCFOLDN> xt_vcrcfoldn_obj; + +/* Declare the function base NAME, pointing it to an instance + of class <NAME>_obj. */ +#define BASE(NAME) \ + namespace bases { const function_base *const NAME = &NAME##_obj; } + +/* XXTVarith */ +BASE (xt_vgmulxor) +BASE (xt_vilo) +BASE (xt_vile) +BASE (xt_vcrcfoldr) +BASE (xt_vcrcfoldn) +} // end namespace riscv_vector diff --git a/gcc/config/riscv/xuantie-vector-builtins-bases.h b/gcc/config/riscv/xuantie-vector-builtins-bases.h new file mode 100644 index 00000000000..ec1e0d71a0e --- /dev/null +++ b/gcc/config/riscv/xuantie-vector-builtins-bases.h @@ -0,0 +1,37 @@ +/* function_base declaration for XuanTie custom 'V' Extension for GNU compiler. + Copyright (C) 2026 Free Software Foundation, Inc. + Contributed by Alibaba DAMO Academy XuanTie Team. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + <http://www.gnu.org/licenses/>. */ + +#ifndef GCC_XUANTIE_VECTOR_BUILTINS_BASES_H +#define GCC_XUANTIE_VECTOR_BUILTINS_BASES_H + +namespace riscv_vector { + +namespace bases { +/* XXTVarith */ +extern const function_base *const xt_vgmulxor; +extern const function_base *const xt_vilo; +extern const function_base *const xt_vile; +extern const function_base *const xt_vcrcfoldr; +extern const function_base *const xt_vcrcfoldn; +} + +} // end namespace riscv_vector + +#endif diff --git a/gcc/config/riscv/xuantie-vector-builtins-functions.def b/gcc/config/riscv/xuantie-vector-builtins-functions.def new file mode 100644 index 00000000000..e174ac10f90 --- /dev/null +++ b/gcc/config/riscv/xuantie-vector-builtins-functions.def @@ -0,0 +1,47 @@ +/* Intrinsic define macros for XuanTie custom 'V' Extension for GNU compiler. + Copyright (C) 2026 Free Software Foundation, Inc. + Contributed by Alibaba DAMO Academy XuanTie Team. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +/* Use "DEF_RVV_FUNCTION" macro to define RVV intrinsic functions. + + - NAME not only describes the base_name of the functions + but also point to the name of the function_base class. + + - SHAPE point to the function_shape class. + + - PREDS describes the predication types that are supported in the + functions. + + - OPS_INFO describes all information of return type and each + argument type. + +*/ +#ifndef DEF_RVV_FUNCTION +#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) +#endif + +#define REQUIRED_EXTENSIONS XXTVARITH_EXT +DEF_RVV_FUNCTION (xt_vgmulxor, alu, none_tu_preds, xt_qu_vvv_ops) +DEF_RVV_FUNCTION (xt_vilo, alu, none_tu_preds, iu_vvv_ops) +DEF_RVV_FUNCTION (xt_vile, alu, none_tu_preds, iu_vvv_ops) +DEF_RVV_FUNCTION (xt_vcrcfoldr, alu, none_tu_preds, xt_diu_vvvv_ops) +DEF_RVV_FUNCTION (xt_vcrcfoldn, alu, none_tu_preds, xt_diu_vvvv_ops) +#undef REQUIRED_EXTENSIONS + +#undef DEF_RVV_FUNCTION diff --git a/gcc/config/riscv/xuantie-vector.md b/gcc/config/riscv/xuantie-vector.md new file mode 100644 index 00000000000..827aeaf9e38 --- /dev/null +++ b/gcc/config/riscv/xuantie-vector.md @@ -0,0 +1,115 @@ +;; Machine description for XuanTie vector extensions. +;; Copyright (C) 2026 Free Software Foundation, Inc. +;; Contributed by Alibaba DAMO Academy XuanTie Team. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +(define_c_enum "unspec" [ + ; XXTVarith + UNSPEC_XT_VGMULXOR + UNSPEC_XT_VILO + UNSPEC_XT_VILE + UNSPEC_XT_VCRCFOLDR + UNSPEC_XT_VCRCFOLDN +]) + +;; XXTVarith +(define_int_iterator UNSPEC_XT_VGMULXOR_IT [ + UNSPEC_XT_VGMULXOR +]) + +(define_int_iterator UNSPEC_XT_VIL_IT [ + UNSPEC_XT_VILO + UNSPEC_XT_VILE +]) + +(define_int_iterator UNSPEC_XT_VCRCFOLD_IT [ + UNSPEC_XT_VCRCFOLDR + UNSPEC_XT_VCRCFOLDN +]) + +(define_int_attr xxtvarith_ins_name [ + (UNSPEC_XT_VGMULXOR "vgmulxor") + (UNSPEC_XT_VILO "vilo") (UNSPEC_XT_VILE "vile") + (UNSPEC_XT_VCRCFOLDR "vcrcfoldr") (UNSPEC_XT_VCRCFOLDN "vcrcfoldn") +]) + +(define_mode_iterator VI_Q [ + RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI + (RVVMF8QI "TARGET_MIN_VLEN > 32") +]) + +(define_insn "@xt_pred_<xxtvarith_ins_name><mode>" + [(set (match_operand:VI_Q 0 "register_operand" "=&vr") + (if_then_else:VI_Q + (unspec:<VM> + [(match_operand 4 "vector_length_operand" " rK") + (match_operand 5 "const_int_operand" " i") + (match_operand 6 "const_int_operand" " i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (unspec:VI_Q + [(match_operand:VI_Q 1 "register_operand" " 0") + (match_operand:VI_Q 2 "register_operand" "vr") + (match_operand:VI_Q 3 "register_operand" "vr")] UNSPEC_XT_VGMULXOR_IT) + (match_dup 1)))] + "TARGET_VECTOR && TARGET_XXTVARITH" + "xt.<xxtvarith_ins_name>.vv\t%0,%2,%3" + [(set_attr "type" "vcompress") + (set_attr "mode" "<MODE>")]) + +(define_insn "@xt_pred_<xxtvarith_ins_name><mode>" + [(set (match_operand:V_VLS 0 "register_operand" "=vr, vr") + (if_then_else:V_VLS + (unspec:<VM> + [(match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (unspec:V_VLS + [(match_operand:V_VLS 2 "register_operand" "vr,vr") + (match_operand:V_VLS 3 "register_operand" "vr,vr")] UNSPEC_XT_VIL_IT) + (match_operand:V_VLS 1 "vector_merge_operand" "vu,0")))] + "TARGET_VECTOR && TARGET_XXTVARITH" + "xt.<xxtvarith_ins_name>.vv\t%0,%2,%3" + [(set_attr "type" "vcompress") + (set_attr "mode" "<MODE>") + (set_attr "merge_op_idx" "1") + (set_attr "vl_op_idx" "4") + (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])")) + (set (attr "avl_type_idx") (const_int 6))]) + +(define_insn "@xt_pred_<xxtvarith_ins_name><mode>" + [(set (match_operand:VI_D 0 "register_operand" "=vr") + (if_then_else:VI_D + (unspec:<VM> + [(match_operand 4 "vector_length_operand" "rK") + (match_operand 5 "const_int_operand" " i") + (match_operand 6 "const_int_operand" " i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (unspec:VI_D + [(match_operand:VI_D 1 "register_operand" " 0") + (match_operand:VI_D 2 "register_operand" "vr") + (match_operand:VI_D 3 "register_operand" "vr")] + UNSPEC_XT_VCRCFOLD_IT) + (match_dup 1)))] + "TARGET_VECTOR && TARGET_XXTVARITH" + "xt.<xxtvarith_ins_name>.vv\t%0,%2,%3" + [(set_attr "type" "vcompress") + (set_attr "mode" "<MODE>")]) diff --git a/gcc/config/riscv/xuantie_vector.h b/gcc/config/riscv/xuantie_vector.h new file mode 100644 index 00000000000..2b07105ca9d --- /dev/null +++ b/gcc/config/riscv/xuantie_vector.h @@ -0,0 +1,34 @@ +/* XuanTie Vector Extension intrinsics include file. + Copyright (C) 2026 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef __XUANTIE_VECTOR_H +#define __XUANTIE_VECTOR_H + +#define __riscv_intrinsic_xxtvarith 1 + +/* TODO: This should have a separate pragma to include only the XuanTie + vector intrinsics. For now, we are including riscv_vector.h. */ +#include <riscv_vector.h> + +#endif // __XUANTIE_VECTOR_H diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi index c3fc8c79118..2c485492b6f 100644 --- a/gcc/doc/riscv-ext.texi +++ b/gcc/doc/riscv-ext.texi @@ -798,4 +798,8 @@ @tab 1.0 @tab SpacemiT vector dot product II extension +@item @samp{xxtvarith} +@tab 1.0 +@tab XuanTie vector arith turbo extension + @end multitable diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-2x-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-2x-run.c new file mode 100644 index 00000000000..83989716e96 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-2x-run.c @@ -0,0 +1,105 @@ +/* { dg-do run } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-add-options riscv_v } */ +/* { dg-additional-options "-O3 -mrvv-max-lmul=m8 -std=gnu99" } */ + +#include "shuffle-interleave-evenodd-2x.c" + +#define SERIES_2(x, y) (x), (x + 1) +#define SERIES_4(x, y) SERIES_2 (x, y), SERIES_2 (x + 2, y) +#define SERIES_8(x, y) SERIES_4 (x, y), SERIES_4 (x + 4, y) +#define SERIES_16(x, y) SERIES_8 (x, y), SERIES_8 (x + 8, y) +#define SERIES_32(x, y) SERIES_16 (x, y), SERIES_16 (x + 16, y) +#define SERIES_64(x, y) SERIES_32 (x, y), SERIES_32 (x + 32, y) + +#define comp(a, b, n) \ + for (unsigned i = 0; i < n; ++i) \ + if ((a)[i] != (b)[i]) \ + __builtin_abort (); + +#define CHECK1(TYPE, NUNITS) \ + __attribute__ ((noipa)) void check1_##TYPE () \ + { \ + TYPE v0 = (TYPE){SERIES_##NUNITS (0, NUNITS)}; \ + TYPE v1 = (TYPE){SERIES_##NUNITS (NUNITS, NUNITS)}; \ + TYPE ref = (TYPE){MASKE_##NUNITS (0, NUNITS)}; \ + TYPE res; \ + permute1_##TYPE (v0, v1, &res); \ + comp (res, ref, NUNITS); \ + } + +#define CHECK2(TYPE, NUNITS) \ + __attribute__ ((noipa)) void check2_##TYPE () \ + { \ + TYPE v0 = (TYPE){SERIES_##NUNITS (0, NUNITS)}; \ + TYPE v1 = (TYPE){SERIES_##NUNITS (NUNITS, NUNITS)}; \ + TYPE ref = (TYPE){MASKO_##NUNITS (0, NUNITS)}; \ + TYPE res; \ + permute2_##TYPE (v0, v1, &res); \ + comp (res, ref, NUNITS); \ + } + +#define CHECK_ALL(T) \ + T (vnx4qi, 4) \ + T (vnx8qi, 8) \ + T (vnx16qi, 16) \ + T (vnx32qi, 32) \ + T (vnx64qi, 64) \ + T (vnx4hi, 4) \ + T (vnx8hi, 8) \ + T (vnx16hi, 16) \ + T (vnx32hi, 32) \ + T (vnx64hi, 64) \ + T (vnx4si, 4) \ + T (vnx8si, 8) \ + T (vnx16si, 16) \ + T (vnx32si, 32) \ + T (vnx4sf, 4) \ + T (vnx8sf, 8) \ + T (vnx16sf, 16) \ + T (vnx32sf, 32) + +CHECK_ALL (CHECK1) +CHECK_ALL (CHECK2) + +int +main () +{ + check1_vnx4qi (); + check1_vnx8qi (); + check1_vnx16qi (); + check1_vnx32qi (); + check1_vnx64qi (); + check1_vnx4hi (); + check1_vnx8hi (); + check1_vnx16hi (); + check1_vnx32hi (); + check1_vnx64hi (); + check1_vnx4si (); + check1_vnx8si (); + check1_vnx16si (); + check1_vnx32si (); + check1_vnx4sf (); + check1_vnx8sf (); + check1_vnx16sf (); + check1_vnx32sf (); + check2_vnx4qi (); + check2_vnx8qi (); + check2_vnx16qi (); + check2_vnx32qi (); + check2_vnx64qi (); + check2_vnx4hi (); + check2_vnx8hi (); + check2_vnx16hi (); + check2_vnx32hi (); + check2_vnx64hi (); + check2_vnx4si (); + check2_vnx8si (); + check2_vnx16si (); + check2_vnx32si (); + check2_vnx4sf (); + check2_vnx8sf (); + check2_vnx16sf (); + check2_vnx32sf (); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-2x-xxtvarith.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-2x-xxtvarith.c new file mode 100644 index 00000000000..e5a8a214b33 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-2x-xxtvarith.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv_xxtvarith -mabi=lp64d -mrvv-max-lmul=m8" } */ + +#include "shuffle-interleave-evenodd-2x.c" + +/* { dg-final { scan-assembler-times "xt.vile" 18 } } */ +/* { dg-final { scan-assembler-times "xt.vilo" 18 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-2x.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-2x.c new file mode 100644 index 00000000000..01fbbe54692 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-2x.c @@ -0,0 +1,61 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-max-lmul=m8" } */ + +#include "perm.h" + +#define MASKE_4(x, y) (x), (x + 1), (x + y), (x + 1 + y) +#define MASKE_8(x, y) MASKE_4 (x, y), MASKE_4 (x + 4, y) +#define MASKE_16(x, y) MASKE_8 (x, y), MASKE_8 (x + 8, y) +#define MASKE_32(x, y) MASKE_16 (x, y), MASKE_16 (x + 16, y) +#define MASKE_64(x, y) MASKE_32 (x, y), MASKE_32 (x + 32, y) + +#define MASKO_4(x, y) (x + 2), (x + 3), (x + 2 + y), (x + 3 + y) +#define MASKO_8(x, y) MASKO_4 (x, y), MASKO_4 (x + 4, y) +#define MASKO_16(x, y) MASKO_8 (x, y), MASKO_8 (x + 8, y) +#define MASKO_32(x, y) MASKO_16 (x, y), MASKO_16 (x + 16, y) +#define MASKO_64(x, y) MASKO_32 (x, y), MASKO_32 (x + 32, y) + +#define PERMUTE1(TYPE, NUNITS) \ + __attribute__ ((noipa)) void permute1_##TYPE (TYPE values1, TYPE values2, \ + TYPE *out) \ + { \ + TYPE v = __builtin_shufflevector (values1, values2, \ + MASKE_##NUNITS (0, NUNITS)); \ + *(TYPE *) out = v; \ + } + +#define PERMUTE2(TYPE, NUNITS) \ + __attribute__ ((noipa)) void permute2_##TYPE (TYPE values1, TYPE values2, \ + TYPE *out) \ + { \ + TYPE v = __builtin_shufflevector (values1, values2, \ + MASKO_##NUNITS (0, NUNITS)); \ + *(TYPE *) out = v; \ + } + +#define TEST_ALL(T) \ + T (vnx4qi, 4) \ + T (vnx8qi, 8) \ + T (vnx16qi, 16) \ + T (vnx32qi, 32) \ + T (vnx64qi, 64) \ + T (vnx4hi, 4) \ + T (vnx8hi, 8) \ + T (vnx16hi, 16) \ + T (vnx32hi, 32) \ + T (vnx64hi, 64) \ + T (vnx4si, 4) \ + T (vnx8si, 8) \ + T (vnx16si, 16) \ + T (vnx32si, 32) \ + T (vnx4sf, 4) \ + T (vnx8sf, 8) \ + T (vnx16sf, 16) \ + T (vnx32sf, 32) + +TEST_ALL (PERMUTE1) +TEST_ALL (PERMUTE2) + +/* { dg-final { scan-assembler-times "vrgather" 56 } } */ +/* { dg-final { scan-assembler-times "vslideup" 4 } } */ +/* { dg-final { scan-assembler-times "vslidedown" 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-run.c new file mode 100644 index 00000000000..a9d31f68106 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-run.c @@ -0,0 +1,122 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-add-options riscv_v } */ +/* { dg-additional-options "-O3 -mrvv-max-lmul=m8 -std=gnu99" } */ + +#include "shuffle-interleave-evenodd.c" + +#define SERIES_2(x, y) (x), (x + 1) +#define SERIES_4(x, y) SERIES_2 (x, y), SERIES_2 (x + 2, y) +#define SERIES_8(x, y) SERIES_4 (x, y), SERIES_4 (x + 4, y) +#define SERIES_16(x, y) SERIES_8 (x, y), SERIES_8 (x + 8, y) +#define SERIES_32(x, y) SERIES_16 (x, y), SERIES_16 (x + 16, y) +#define SERIES_64(x, y) SERIES_32 (x, y), SERIES_32 (x + 32, y) + +#define comp(a, b, n) \ + for (unsigned i = 0; i < n; ++i) \ + if ((a)[i] != (b)[i]) \ + __builtin_abort (); + +#define CHECK1(TYPE, NUNITS) \ + __attribute__ ((noipa)) void check1_##TYPE () \ + { \ + TYPE v0 = (TYPE){SERIES_##NUNITS (0, NUNITS)}; \ + TYPE v1 = (TYPE){SERIES_##NUNITS (NUNITS, NUNITS)}; \ + TYPE ref = (TYPE){MASKE_##NUNITS (0, NUNITS)}; \ + TYPE res; \ + permute1_##TYPE (v0, v1, &res); \ + comp (res, ref, NUNITS); \ + } + +#define CHECK2(TYPE, NUNITS) \ + __attribute__ ((noipa)) void check2_##TYPE () \ + { \ + TYPE v0 = (TYPE){SERIES_##NUNITS (0, NUNITS)}; \ + TYPE v1 = (TYPE){SERIES_##NUNITS (NUNITS, NUNITS)}; \ + TYPE ref = (TYPE){MASKO_##NUNITS (0, NUNITS)}; \ + TYPE res; \ + permute2_##TYPE (v0, v1, &res); \ + comp (res, ref, NUNITS); \ + } + +#define CHECK_ALL(T) \ + T (vnx4qi, 4) \ + T (vnx8qi, 8) \ + T (vnx16qi, 16) \ + T (vnx32qi, 32) \ + T (vnx64qi, 64) \ + T (vnx4hi, 4) \ + T (vnx8hi, 8) \ + T (vnx16hi, 16) \ + T (vnx32hi, 32) \ + T (vnx64hi, 64) \ + T (vnx4si, 4) \ + T (vnx8si, 8) \ + T (vnx16si, 16) \ + T (vnx32si, 32) \ + T (vnx4di, 4) \ + T (vnx8di, 8) \ + T (vnx16di, 16) \ + T (vnx4sf, 4) \ + T (vnx8sf, 8) \ + T (vnx16sf, 16) \ + T (vnx32sf, 32) \ + T (vnx4df, 4) \ + T (vnx8df, 8) \ + T (vnx16df, 16) + +CHECK_ALL (CHECK1) +CHECK_ALL (CHECK2) + +int +main () +{ + check1_vnx4qi (); + check1_vnx8qi (); + check1_vnx16qi (); + check1_vnx32qi (); + check1_vnx64qi (); + check1_vnx4hi (); + check1_vnx8hi (); + check1_vnx16hi (); + check1_vnx32hi (); + check1_vnx64hi (); + check1_vnx4si (); + check1_vnx8si (); + check1_vnx16si (); + check1_vnx32si (); + check1_vnx4di (); + check1_vnx8di (); + check1_vnx16di (); + check1_vnx4sf (); + check1_vnx8sf (); + check1_vnx16sf (); + check1_vnx32sf (); + check1_vnx4df (); + check1_vnx8df (); + check1_vnx16df (); + check2_vnx4qi (); + check2_vnx8qi (); + check2_vnx16qi (); + check2_vnx32qi (); + check2_vnx64qi (); + check2_vnx4hi (); + check2_vnx8hi (); + check2_vnx16hi (); + check2_vnx32hi (); + check2_vnx64hi (); + check2_vnx4si (); + check2_vnx8si (); + check2_vnx16si (); + check2_vnx32si (); + check2_vnx4di (); + check2_vnx8di (); + check2_vnx16di (); + check2_vnx4sf (); + check2_vnx8sf (); + check2_vnx16sf (); + check2_vnx32sf (); + check2_vnx4df (); + check2_vnx8df (); + check2_vnx16df (); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-xxtvarith.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-xxtvarith.c new file mode 100644 index 00000000000..27c1be3e0f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd-xxtvarith.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv_xxtvarith -mabi=lp64d -mrvv-max-lmul=m8" } */ + +#include "shuffle-interleave-evenodd.c" + +/* { dg-final { scan-assembler-times "xt.vile" 24 } } */ +/* { dg-final { scan-assembler-times "xt.vilo" 24 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd.c new file mode 100644 index 00000000000..491ae36dc90 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-evenodd.c @@ -0,0 +1,67 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-max-lmul=m8" } */ + +#include "perm.h" + +#define MASKE_2(x, y) (x), (x + y) +#define MASKE_4(x, y) MASKE_2 (x, y), MASKE_2 (x + 2, y) +#define MASKE_8(x, y) MASKE_4 (x, y), MASKE_4 (x + 4, y) +#define MASKE_16(x, y) MASKE_8 (x, y), MASKE_8 (x + 8, y) +#define MASKE_32(x, y) MASKE_16 (x, y), MASKE_16 (x + 16, y) +#define MASKE_64(x, y) MASKE_32 (x, y), MASKE_32 (x + 32, y) + +#define MASKO_2(x, y) (x + 1), (x + 1 + y) +#define MASKO_4(x, y) MASKO_2 (x, y), MASKO_2 (x + 2, y) +#define MASKO_8(x, y) MASKO_4 (x, y), MASKO_4 (x + 4, y) +#define MASKO_16(x, y) MASKO_8 (x, y), MASKO_8 (x + 8, y) +#define MASKO_32(x, y) MASKO_16 (x, y), MASKO_16 (x + 16, y) +#define MASKO_64(x, y) MASKO_32 (x, y), MASKO_32 (x + 32, y) + +#define PERMUTE1(TYPE, NUNITS) \ + __attribute__ ((noipa)) void permute1_##TYPE (TYPE values1, TYPE values2, \ + TYPE *out) \ + { \ + TYPE v = __builtin_shufflevector (values1, values2, \ + MASKE_##NUNITS (0, NUNITS)); \ + *(TYPE *) out = v; \ + } + +#define PERMUTE2(TYPE, NUNITS) \ + __attribute__ ((noipa)) void permute2_##TYPE (TYPE values1, TYPE values2, \ + TYPE *out) \ + { \ + TYPE v = __builtin_shufflevector (values1, values2, \ + MASKO_##NUNITS (0, NUNITS)); \ + *(TYPE *) out = v; \ + } + +#define TEST_ALL(T) \ + T (vnx4qi, 4) \ + T (vnx8qi, 8) \ + T (vnx16qi, 16) \ + T (vnx32qi, 32) \ + T (vnx64qi, 64) \ + T (vnx4hi, 4) \ + T (vnx8hi, 8) \ + T (vnx16hi, 16) \ + T (vnx32hi, 32) \ + T (vnx64hi, 64) \ + T (vnx4si, 4) \ + T (vnx8si, 8) \ + T (vnx16si, 16) \ + T (vnx32si, 32) \ + T (vnx4di, 4) \ + T (vnx8di, 8) \ + T (vnx16di, 16) \ + T (vnx4sf, 4) \ + T (vnx8sf, 8) \ + T (vnx16sf, 16) \ + T (vnx32sf, 32) \ + T (vnx4df, 4) \ + T (vnx8df, 8) \ + T (vnx16df, 16) + +TEST_ALL (PERMUTE1) +TEST_ALL (PERMUTE2) + +/* { dg-final { scan-assembler-times "vrgather" 96 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic-detection.c b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic-detection.c index 4ba99664ed1..ba26958d900 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic-detection.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/intrinsic-detection.c @@ -4,6 +4,7 @@ #include <riscv_vector.h> #include <sifive_vector.h> #include <andes_vector.h> +#include <xuantie_vector.h> #if defined (__riscv_vector) || defined (__riscv_zvabd) \ || defined (__riscv_zvbb) \ @@ -52,7 +53,8 @@ || !defined (__riscv_intrinsic_xandesvbfhcvt) \ || !defined (__riscv_intrinsic_xandesvdot) \ || !defined (__riscv_intrinsic_xandesvpackfph) \ - || !defined (__riscv_intrinsic_xandesvsintload) + || !defined (__riscv_intrinsic_xandesvsintload) \ + || !defined (__riscv_intrinsic_xxtvarith) #error "missing vector intrinsic detection macro" #endif @@ -89,6 +91,7 @@ || __riscv_intrinsic_xandesvbfhcvt != 1 \ || __riscv_intrinsic_xandesvdot != 1 \ || __riscv_intrinsic_xandesvpackfph != 1 \ - || __riscv_intrinsic_xandesvsintload != 1 + || __riscv_intrinsic_xandesvsintload != 1 \ + || __riscv_intrinsic_xxtvarith != 1 #error "bad vector intrinsic detection macro value" #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index 9a3f05366e8..cc9fa62d912 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -45,6 +45,8 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xtheadvector/*.\[cS\]]] \ "" $CFLAGS dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xandesvector/*.\[cS\]]] \ "" $CFLAGS +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xxtvector/*.\[cS\]]] \ + "" $CFLAGS gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \ "" $CFLAGS dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xuantie_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xuantie_vector.h new file mode 100644 index 00000000000..38ca7d95d42 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xuantie_vector.h @@ -0,0 +1,11 @@ +/* Wrapper of xuantie_vector.h, prevent xuantie_vector.h including stdint.h from + C library, that might cause problem on testing RV32 related testcase when + we disable multilib. */ +#ifndef _XUANTIE_VECTOR_WRAP_H + +#define _GCC_WRAP_STDINT_H +#include "stdint-gcc.h" +#include_next <xuantie_vector.h> +#define _XUANTIE_VECTOR_WRAP_H + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldn_vv_non_overloaded.c b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldn_vv_non_overloaded.c new file mode 100644 index 00000000000..9fae60ebf43 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldn_vv_non_overloaded.c @@ -0,0 +1,119 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_xxtvarith -mabi=ilp32d" { target { rv32 } } } */ +/* { dg-options "-march=rv64gcv_xxtvarith -mabi=lp64d" { target { rv64 } } } */ + +#include "xuantie_vector.h" + +vint64m1_t +test_vcrcfoldn_vv_i64m1 (vint64m1_t vd, vint64m1_t vs2, vint64m1_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_vv_i64m1 (vd, vs2, vs1, vl); +} + +vint64m2_t +test_vcrcfoldn_vv_i64m2 (vint64m2_t vd, vint64m2_t vs2, vint64m2_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_vv_i64m2 (vd, vs2, vs1, vl); +} + +vint64m4_t +test_vcrcfoldn_vv_i64m4 (vint64m4_t vd, vint64m4_t vs2, vint64m4_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_vv_i64m4 (vd, vs2, vs1, vl); +} + +vint64m8_t +test_vcrcfoldn_vv_i64m8 (vint64m8_t vd, vint64m8_t vs2, vint64m8_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_vv_i64m8 (vd, vs2, vs1, vl); +} + +vuint64m1_t +test_vcrcfoldn_vv_u64m1 (vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_vv_u64m1 (vd, vs2, vs1, vl); +} + +vuint64m2_t +test_vcrcfoldn_vv_u64m2 (vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_vv_u64m2 (vd, vs2, vs1, vl); +} + +vuint64m4_t +test_vcrcfoldn_vv_u64m4 (vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_vv_u64m4 (vd, vs2, vs1, vl); +} + +vuint64m8_t +test_vcrcfoldn_vv_u64m8 (vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_vv_u64m8 (vd, vs2, vs1, vl); +} + +vint64m1_t +test_vcrcfoldn_vv_i64m1_tu (vint64m1_t vd, vint64m1_t vs2, vint64m1_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_vv_i64m1_tu (vd, vs2, vs1, vl); +} + +vint64m2_t +test_vcrcfoldn_vv_i64m2_tu (vint64m2_t vd, vint64m2_t vs2, vint64m2_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_vv_i64m2_tu (vd, vs2, vs1, vl); +} + +vint64m4_t +test_vcrcfoldn_vv_i64m4_tu (vint64m4_t vd, vint64m4_t vs2, vint64m4_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_vv_i64m4_tu (vd, vs2, vs1, vl); +} + +vint64m8_t +test_vcrcfoldn_vv_i64m8_tu (vint64m8_t vd, vint64m8_t vs2, vint64m8_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_vv_i64m8_tu (vd, vs2, vs1, vl); +} + +vuint64m1_t +test_vcrcfoldn_vv_u64m1_tu (vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_vv_u64m1_tu (vd, vs2, vs1, vl); +} + +vuint64m2_t +test_vcrcfoldn_vv_u64m2_tu (vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_vv_u64m2_tu (vd, vs2, vs1, vl); +} + +vuint64m4_t +test_vcrcfoldn_vv_u64m4_tu (vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_vv_u64m4_tu (vd, vs2, vs1, vl); +} + +vuint64m8_t +test_vcrcfoldn_vv_u64m8_tu (vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_vv_u64m8_tu (vd, vs2, vs1, vl); +} + +/* { dg-final { scan-assembler-times "xt\\.vcrcfoldn\\.vv\t" 16 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldn_vv_overloaded.c b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldn_vv_overloaded.c new file mode 100644 index 00000000000..bb829a8e013 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldn_vv_overloaded.c @@ -0,0 +1,107 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_xxtvarith -mabi=ilp32d" { target { rv32 } } } */ +/* { dg-options "-march=rv64gcv_xxtvarith -mabi=lp64d" { target { rv64 } } } */ + +#include "xuantie_vector.h" + +vint64m1_t +test0_vcrcfoldn (vint64m1_t vd, vint64m1_t vs2, vint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldn (vd, vs2, vs1, vl); +} + +vint64m2_t +test1_vcrcfoldn (vint64m2_t vd, vint64m2_t vs2, vint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldn (vd, vs2, vs1, vl); +} + +vint64m4_t +test2_vcrcfoldn (vint64m4_t vd, vint64m4_t vs2, vint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldn (vd, vs2, vs1, vl); +} + +vint64m8_t +test3_vcrcfoldn (vint64m8_t vd, vint64m8_t vs2, vint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldn (vd, vs2, vs1, vl); +} + +vuint64m1_t +test4_vcrcfoldn (vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldn (vd, vs2, vs1, vl); +} + +vuint64m2_t +test5_vcrcfoldn (vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldn (vd, vs2, vs1, vl); +} + +vuint64m4_t +test6_vcrcfoldn (vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldn (vd, vs2, vs1, vl); +} + +vuint64m8_t +test7_vcrcfoldn (vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldn (vd, vs2, vs1, vl); +}; + +vint64m1_t +test9_vcrcfoldn_tu (vint64m1_t vd, vint64m1_t vs2, vint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldn_tu (vd, vs2, vs1, vl); +} + +vint64m2_t +test10_vcrcfoldn_tu (vint64m2_t vd, vint64m2_t vs2, vint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldn_tu (vd, vs2, vs1, vl); +} + +vint64m4_t +test11_vcrcfoldn_tu (vint64m4_t vd, vint64m4_t vs2, vint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldn_tu (vd, vs2, vs1, vl); +} + +vint64m8_t +test12_vcrcfoldn_tu (vint64m8_t vd, vint64m8_t vs2, vint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldn_tu (vd, vs2, vs1, vl); +} + +vuint64m1_t +test13_vcrcfoldn_tu (vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_tu (vd, vs2, vs1, vl); +} + +vuint64m2_t +test14_vcrcfoldn_tu (vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_tu (vd, vs2, vs1, vl); +} + +vuint64m4_t +test15_vcrcfoldn_tu (vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_tu (vd, vs2, vs1, vl); +} + +vuint64m8_t +test16_vcrcfoldn_tu (vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldn_tu (vd, vs2, vs1, vl); +} + +/* { dg-final { scan-assembler-times "xt\\.vcrcfoldn\\.vv\t" 16 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldr_vv_non_overloaded.c b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldr_vv_non_overloaded.c new file mode 100644 index 00000000000..f2cefbd025b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldr_vv_non_overloaded.c @@ -0,0 +1,119 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_xxtvarith -mabi=ilp32d" { target { rv32 } } } */ +/* { dg-options "-march=rv64gcv_xxtvarith -mabi=lp64d" { target { rv64 } } } */ + +#include "xuantie_vector.h" + +vint64m1_t +test_vcrcfoldr_vv_i64m1 (vint64m1_t vd, vint64m1_t vs2, vint64m1_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_vv_i64m1 (vd, vs2, vs1, vl); +} + +vint64m2_t +test_vcrcfoldr_vv_i64m2 (vint64m2_t vd, vint64m2_t vs2, vint64m2_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_vv_i64m2 (vd, vs2, vs1, vl); +} + +vint64m4_t +test_vcrcfoldr_vv_i64m4 (vint64m4_t vd, vint64m4_t vs2, vint64m4_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_vv_i64m4 (vd, vs2, vs1, vl); +} + +vint64m8_t +test_vcrcfoldr_vv_i64m8 (vint64m8_t vd, vint64m8_t vs2, vint64m8_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_vv_i64m8 (vd, vs2, vs1, vl); +} + +vuint64m1_t +test_vcrcfoldr_vv_u64m1 (vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_vv_u64m1 (vd, vs2, vs1, vl); +} + +vuint64m2_t +test_vcrcfoldr_vv_u64m2 (vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_vv_u64m2 (vd, vs2, vs1, vl); +} + +vuint64m4_t +test_vcrcfoldr_vv_u64m4 (vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_vv_u64m4 (vd, vs2, vs1, vl); +} + +vuint64m8_t +test_vcrcfoldr_vv_u64m8 (vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_vv_u64m8 (vd, vs2, vs1, vl); +} + +vint64m1_t +test_vcrcfoldr_vv_i64m1_tu (vint64m1_t vd, vint64m1_t vs2, vint64m1_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_vv_i64m1_tu (vd, vs2, vs1, vl); +} + +vint64m2_t +test_vcrcfoldr_vv_i64m2_tu (vint64m2_t vd, vint64m2_t vs2, vint64m2_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_vv_i64m2_tu (vd, vs2, vs1, vl); +} + +vint64m4_t +test_vcrcfoldr_vv_i64m4_tu (vint64m4_t vd, vint64m4_t vs2, vint64m4_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_vv_i64m4_tu (vd, vs2, vs1, vl); +} + +vint64m8_t +test_vcrcfoldr_vv_i64m8_tu (vint64m8_t vd, vint64m8_t vs2, vint64m8_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_vv_i64m8_tu (vd, vs2, vs1, vl); +} + +vuint64m1_t +test_vcrcfoldr_vv_u64m1_tu (vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_vv_u64m1_tu (vd, vs2, vs1, vl); +} + +vuint64m2_t +test_vcrcfoldr_vv_u64m2_tu (vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_vv_u64m2_tu (vd, vs2, vs1, vl); +} + +vuint64m4_t +test_vcrcfoldr_vv_u64m4_tu (vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_vv_u64m4_tu (vd, vs2, vs1, vl); +} + +vuint64m8_t +test_vcrcfoldr_vv_u64m8_tu (vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_vv_u64m8_tu (vd, vs2, vs1, vl); +} + +/* { dg-final { scan-assembler-times "xt\\.vcrcfoldr\\.vv\t" 16 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldr_vv_overloaded.c b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldr_vv_overloaded.c new file mode 100644 index 00000000000..0f866dbe32b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vcrcfoldr_vv_overloaded.c @@ -0,0 +1,107 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_xxtvarith -mabi=ilp32d" { target { rv32 } } } */ +/* { dg-options "-march=rv64gcv_xxtvarith -mabi=lp64d" { target { rv64 } } } */ + +#include "xuantie_vector.h" + +vint64m1_t +test0_vcrcfoldr (vint64m1_t vd, vint64m1_t vs2, vint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldr (vd, vs2, vs1, vl); +} + +vint64m2_t +test1_vcrcfoldr (vint64m2_t vd, vint64m2_t vs2, vint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldr (vd, vs2, vs1, vl); +} + +vint64m4_t +test2_vcrcfoldr (vint64m4_t vd, vint64m4_t vs2, vint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldr (vd, vs2, vs1, vl); +} + +vint64m8_t +test3_vcrcfoldr (vint64m8_t vd, vint64m8_t vs2, vint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldr (vd, vs2, vs1, vl); +} + +vuint64m1_t +test4_vcrcfoldr (vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldr (vd, vs2, vs1, vl); +} + +vuint64m2_t +test5_vcrcfoldr (vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldr (vd, vs2, vs1, vl); +} + +vuint64m4_t +test6_vcrcfoldr (vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldr (vd, vs2, vs1, vl); +} + +vuint64m8_t +test7_vcrcfoldr (vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldr (vd, vs2, vs1, vl); +}; + +vint64m1_t +test9_vcrcfoldr_tu (vint64m1_t vd, vint64m1_t vs2, vint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldr_tu (vd, vs2, vs1, vl); +} + +vint64m2_t +test10_vcrcfoldr_tu (vint64m2_t vd, vint64m2_t vs2, vint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldr_tu (vd, vs2, vs1, vl); +} + +vint64m4_t +test11_vcrcfoldr_tu (vint64m4_t vd, vint64m4_t vs2, vint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldr_tu (vd, vs2, vs1, vl); +} + +vint64m8_t +test12_vcrcfoldr_tu (vint64m8_t vd, vint64m8_t vs2, vint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vcrcfoldr_tu (vd, vs2, vs1, vl); +} + +vuint64m1_t +test13_vcrcfoldr_tu (vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_tu (vd, vs2, vs1, vl); +} + +vuint64m2_t +test14_vcrcfoldr_tu (vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_tu (vd, vs2, vs1, vl); +} + +vuint64m4_t +test15_vcrcfoldr_tu (vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_tu (vd, vs2, vs1, vl); +} + +vuint64m8_t +test16_vcrcfoldr_tu (vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, + size_t vl) +{ + return __riscv_xt_vcrcfoldr_tu (vd, vs2, vs1, vl); +} + +/* { dg-final { scan-assembler-times "xt\\.vcrcfoldr\\.vv\t" 16 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vgmulxor_vv_non_overloaded.c b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vgmulxor_vv_non_overloaded.c new file mode 100644 index 00000000000..15c4f412d0d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vgmulxor_vv_non_overloaded.c @@ -0,0 +1,101 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_xxtvarith -mabi=ilp32d" { target { rv32 } } } */ +/* { dg-options "-march=rv64gcv_xxtvarith -mabi=lp64d" { target { rv64 } } } */ + +#include "xuantie_vector.h" + +vuint8mf8_t +test_vgmulxor_vv_u8mf8 (vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, + size_t vl) +{ + return __riscv_xt_vgmulxor_vv_u8mf8 (vd, vs2, vs1, vl); +} + +vuint8mf4_t +test_vgmulxor_vv_u8mf4 (vuint8mf4_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, + size_t vl) +{ + return __riscv_xt_vgmulxor_vv_u8mf4 (vd, vs2, vs1, vl); +} + +vuint8mf2_t +test_vgmulxor_vv_u8mf2 (vuint8mf2_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, + size_t vl) +{ + return __riscv_xt_vgmulxor_vv_u8mf2 (vd, vs2, vs1, vl); +} + +vuint8m1_t +test_vgmulxor_vv_u8m1 (vuint8m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor_vv_u8m1 (vd, vs2, vs1, vl); +} + +vuint8m2_t +test_vgmulxor_vv_u8m2 (vuint8m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor_vv_u8m2 (vd, vs2, vs1, vl); +} + +vuint8m4_t +test_vgmulxor_vv_u8m4 (vuint8m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor_vv_u8m4 (vd, vs2, vs1, vl); +} + +vuint8m8_t +test_vgmulxor_vv_u8m8 (vuint8m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor_vv_u8m8 (vd, vs2, vs1, vl); +} + +vuint8mf8_t +test_vgmulxor_vv_u8mf8_tu (vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, + size_t vl) +{ + return __riscv_xt_vgmulxor_vv_u8mf8_tu (vd, vs2, vs1, vl); +} + +vuint8mf4_t +test_vgmulxor_vv_u8mf4_tu (vuint8mf4_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, + size_t vl) +{ + return __riscv_xt_vgmulxor_vv_u8mf4_tu (vd, vs2, vs1, vl); +} + +vuint8mf2_t +test_vgmulxor_vv_u8mf2_tu (vuint8mf2_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, + size_t vl) +{ + return __riscv_xt_vgmulxor_vv_u8mf2_tu (vd, vs2, vs1, vl); +} + +vuint8m1_t +test_vgmulxor_vv_u8m1_tu (vuint8m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1, + size_t vl) +{ + return __riscv_xt_vgmulxor_vv_u8m1_tu (vd, vs2, vs1, vl); +} + +vuint8m2_t +test_vgmulxor_vv_u8m2_tu (vuint8m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1, + size_t vl) +{ + return __riscv_xt_vgmulxor_vv_u8m2_tu (vd, vs2, vs1, vl); +} + +vuint8m4_t +test_vgmulxor_vv_u8m4_tu (vuint8m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1, + size_t vl) +{ + return __riscv_xt_vgmulxor_vv_u8m4_tu (vd, vs2, vs1, vl); +} + +vuint8m8_t +test_vgmulxor_vv_u8m8_tu (vuint8m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1, + size_t vl) +{ + return __riscv_xt_vgmulxor_vv_u8m8_tu (vd, vs2, vs1, vl); +} + +/* { dg-final { scan-assembler-times "xt\\.vgmulxor\\.vv\t" 14 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vgmulxor_vv_overloaded.c b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vgmulxor_vv_overloaded.c new file mode 100644 index 00000000000..f01ea80ae1a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vgmulxor_vv_overloaded.c @@ -0,0 +1,91 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_xxtvarith -mabi=ilp32d" { target { rv32 } } } */ +/* { dg-options "-march=rv64gcv_xxtvarith -mabi=lp64d" { target { rv64 } } } */ + +#include "xuantie_vector.h" + +vuint8mf8_t +test0_vgmulxor (vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor (vd, vs2, vs1, vl); +} + +vuint8mf4_t +test1_vgmulxor (vuint8mf4_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor (vd, vs2, vs1, vl); +} + +vuint8mf2_t +test2_vgmulxor (vuint8mf2_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor (vd, vs2, vs1, vl); +} + +vuint8m1_t +test3_vgmulxor (vuint8m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor (vd, vs2, vs1, vl); +} + +vuint8m2_t +test4_vgmulxor (vuint8m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor (vd, vs2, vs1, vl); +} + +vuint8m4_t +test5_vgmulxor (vuint8m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor (vd, vs2, vs1, vl); +} + +vuint8m8_t +test6_vgmulxor (vuint8m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor (vd, vs2, vs1, vl); +} + +vuint8mf8_t +test8_vgmulxor_tu (vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor_tu (vd, vs2, vs1, vl); +} + +vuint8mf4_t +test9_vgmulxor_tu (vuint8mf4_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor_tu (vd, vs2, vs1, vl); +} + +vuint8mf2_t +test10_vgmulxor_tu (vuint8mf2_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor_tu (vd, vs2, vs1, vl); +} + +vuint8m1_t +test11_vgmulxor_tu (vuint8m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor_tu (vd, vs2, vs1, vl); +} + +vuint8m2_t +test12_vgmulxor_tu (vuint8m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor_tu (vd, vs2, vs1, vl); +} + +vuint8m4_t +test13_vgmulxor_tu (vuint8m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor_tu (vd, vs2, vs1, vl); +} + +vuint8m8_t +test14_vgmulxor_tu (vuint8m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vgmulxor_tu (vd, vs2, vs1, vl); +} + +/* { dg-final { scan-assembler-times "xt\\.vgmulxor\\.vv\t" 14 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vile_vv_non_overloaded.c b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vile_vv_non_overloaded.c new file mode 100644 index 00000000000..c483ed9e93b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vile_vv_non_overloaded.c @@ -0,0 +1,556 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_xxtvarith -mabi=ilp32d" { target { rv32 } } } */ +/* { dg-options "-march=rv64gcv_xxtvarith -mabi=lp64d" { target { rv64 } } } */ + +#include "xuantie_vector.h" + +vint8mf8_t +test_vile_vv_i8mf8 (vint8mf8_t vs2, vint8mf8_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i8mf8 (vs2, vs1, vl); +} + +vint8mf4_t +test_vile_vv_i8mf4 (vint8mf4_t vs2, vint8mf4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i8mf4 (vs2, vs1, vl); +} + +vint8mf2_t +test_vile_vv_i8mf2 (vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i8mf2 (vs2, vs1, vl); +} + +vint8m1_t +test_vile_vv_i8m1 (vint8m1_t vs2, vint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i8m1 (vs2, vs1, vl); +} + +vint8m2_t +test_vile_vv_i8m2 (vint8m2_t vs2, vint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i8m2 (vs2, vs1, vl); +} + +vint8m4_t +test_vile_vv_i8m4 (vint8m4_t vs2, vint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i8m4 (vs2, vs1, vl); +} + +vint8m8_t +test_vile_vv_i8m8 (vint8m8_t vs2, vint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i8m8 (vs2, vs1, vl); +} + +vint16mf4_t +test_vile_vv_i16mf4 (vint16mf4_t vs2, vint16mf4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i16mf4 (vs2, vs1, vl); +} + +vint16mf2_t +test_vile_vv_i16mf2 (vint16mf2_t vs2, vint16mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i16mf2 (vs2, vs1, vl); +} + +vint16m1_t +test_vile_vv_i16m1 (vint16m1_t vs2, vint16m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i16m1 (vs2, vs1, vl); +} + +vint16m2_t +test_vile_vv_i16m2 (vint16m2_t vs2, vint16m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i16m2 (vs2, vs1, vl); +} + +vint16m4_t +test_vile_vv_i16m4 (vint16m4_t vs2, vint16m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i16m4 (vs2, vs1, vl); +} + +vint16m8_t +test_vile_vv_i16m8 (vint16m8_t vs2, vint16m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i16m8 (vs2, vs1, vl); +} + +vint32mf2_t +test_vile_vv_i32mf2 (vint32mf2_t vs2, vint32mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i32mf2 (vs2, vs1, vl); +} + +vint32m1_t +test_vile_vv_i32m1 (vint32m1_t vs2, vint32m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i32m1 (vs2, vs1, vl); +} + +vint32m2_t +test_vile_vv_i32m2 (vint32m2_t vs2, vint32m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i32m2 (vs2, vs1, vl); +} + +vint32m4_t +test_vile_vv_i32m4 (vint32m4_t vs2, vint32m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i32m4 (vs2, vs1, vl); +} + +vint32m8_t +test_vile_vv_i32m8 (vint32m8_t vs2, vint32m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i32m8 (vs2, vs1, vl); +} + +vint64m1_t +test_vile_vv_i64m1 (vint64m1_t vs2, vint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i64m1 (vs2, vs1, vl); +} + +vint64m2_t +test_vile_vv_i64m2 (vint64m2_t vs2, vint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i64m2 (vs2, vs1, vl); +} + +vint64m4_t +test_vile_vv_i64m4 (vint64m4_t vs2, vint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i64m4 (vs2, vs1, vl); +} + +vint64m8_t +test_vile_vv_i64m8 (vint64m8_t vs2, vint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i64m8 (vs2, vs1, vl); +} + +vuint8mf8_t +test_vile_vv_u8mf8 (vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u8mf8 (vs2, vs1, vl); +} + +vuint8mf4_t +test_vile_vv_u8mf4 (vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u8mf4 (vs2, vs1, vl); +} + +vuint8mf2_t +test_vile_vv_u8mf2 (vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u8mf2 (vs2, vs1, vl); +} + +vuint8m1_t +test_vile_vv_u8m1 (vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u8m1 (vs2, vs1, vl); +} + +vuint8m2_t +test_vile_vv_u8m2 (vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u8m2 (vs2, vs1, vl); +} + +vuint8m4_t +test_vile_vv_u8m4 (vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u8m4 (vs2, vs1, vl); +} + +vuint8m8_t +test_vile_vv_u8m8 (vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u8m8 (vs2, vs1, vl); +} + +vuint16mf4_t +test_vile_vv_u16mf4 (vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u16mf4 (vs2, vs1, vl); +} + +vuint16mf2_t +test_vile_vv_u16mf2 (vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u16mf2 (vs2, vs1, vl); +} + +vuint16m1_t +test_vile_vv_u16m1 (vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u16m1 (vs2, vs1, vl); +} + +vuint16m2_t +test_vile_vv_u16m2 (vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u16m2 (vs2, vs1, vl); +} + +vuint16m4_t +test_vile_vv_u16m4 (vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u16m4 (vs2, vs1, vl); +} + +vuint16m8_t +test_vile_vv_u16m8 (vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u16m8 (vs2, vs1, vl); +} + +vuint32mf2_t +test_vile_vv_u32mf2 (vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u32mf2 (vs2, vs1, vl); +} + +vuint32m1_t +test_vile_vv_u32m1 (vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u32m1 (vs2, vs1, vl); +} + +vuint32m2_t +test_vile_vv_u32m2 (vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u32m2 (vs2, vs1, vl); +} + +vuint32m4_t +test_vile_vv_u32m4 (vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u32m4 (vs2, vs1, vl); +} + +vuint32m8_t +test_vile_vv_u32m8 (vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u32m8 (vs2, vs1, vl); +} + +vuint64m1_t +test_vile_vv_u64m1 (vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u64m1 (vs2, vs1, vl); +} + +vuint64m2_t +test_vile_vv_u64m2 (vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u64m2 (vs2, vs1, vl); +} + +vuint64m4_t +test_vile_vv_u64m4 (vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u64m4 (vs2, vs1, vl); +} + +vuint64m8_t +test_vile_vv_u64m8 (vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u64m8 (vs2, vs1, vl); +} + +vint8mf8_t +test_vile_vv_i8mf8_tu (vint8mf8_t vd, vint8mf8_t vs2, vint8mf8_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i8mf8_tu (vd, vs2, vs1, vl); +} + +vint8mf4_t +test_vile_vv_i8mf4_tu (vint8mf4_t vd, vint8mf4_t vs2, vint8mf4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i8mf4_tu (vd, vs2, vs1, vl); +} + +vint8mf2_t +test_vile_vv_i8mf2_tu (vint8mf2_t vd, vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i8mf2_tu (vd, vs2, vs1, vl); +} + +vint8m1_t +test_vile_vv_i8m1_tu (vint8m1_t vd, vint8m1_t vs2, vint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i8m1_tu (vd, vs2, vs1, vl); +} + +vint8m2_t +test_vile_vv_i8m2_tu (vint8m2_t vd, vint8m2_t vs2, vint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i8m2_tu (vd, vs2, vs1, vl); +} + +vint8m4_t +test_vile_vv_i8m4_tu (vint8m4_t vd, vint8m4_t vs2, vint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i8m4_tu (vd, vs2, vs1, vl); +} + +vint8m8_t +test_vile_vv_i8m8_tu (vint8m8_t vd, vint8m8_t vs2, vint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i8m8_tu (vd, vs2, vs1, vl); +} + +vint16mf4_t +test_vile_vv_i16mf4_tu (vint16mf4_t vd, vint16mf4_t vs2, vint16mf4_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_i16mf4_tu (vd, vs2, vs1, vl); +} + +vint16mf2_t +test_vile_vv_i16mf2_tu (vint16mf2_t vd, vint16mf2_t vs2, vint16mf2_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_i16mf2_tu (vd, vs2, vs1, vl); +} + +vint16m1_t +test_vile_vv_i16m1_tu (vint16m1_t vd, vint16m1_t vs2, vint16m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i16m1_tu (vd, vs2, vs1, vl); +} + +vint16m2_t +test_vile_vv_i16m2_tu (vint16m2_t vd, vint16m2_t vs2, vint16m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i16m2_tu (vd, vs2, vs1, vl); +} + +vint16m4_t +test_vile_vv_i16m4_tu (vint16m4_t vd, vint16m4_t vs2, vint16m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i16m4_tu (vd, vs2, vs1, vl); +} + +vint16m8_t +test_vile_vv_i16m8_tu (vint16m8_t vd, vint16m8_t vs2, vint16m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i16m8_tu (vd, vs2, vs1, vl); +} + +vint32mf2_t +test_vile_vv_i32mf2_tu (vint32mf2_t vd, vint32mf2_t vs2, vint32mf2_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_i32mf2_tu (vd, vs2, vs1, vl); +} + +vint32m1_t +test_vile_vv_i32m1_tu (vint32m1_t vd, vint32m1_t vs2, vint32m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i32m1_tu (vd, vs2, vs1, vl); +} + +vint32m2_t +test_vile_vv_i32m2_tu (vint32m2_t vd, vint32m2_t vs2, vint32m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i32m2_tu (vd, vs2, vs1, vl); +} + +vint32m4_t +test_vile_vv_i32m4_tu (vint32m4_t vd, vint32m4_t vs2, vint32m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i32m4_tu (vd, vs2, vs1, vl); +} + +vint32m8_t +test_vile_vv_i32m8_tu (vint32m8_t vd, vint32m8_t vs2, vint32m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i32m8_tu (vd, vs2, vs1, vl); +} + +vint64m1_t +test_vile_vv_i64m1_tu (vint64m1_t vd, vint64m1_t vs2, vint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i64m1_tu (vd, vs2, vs1, vl); +} + +vint64m2_t +test_vile_vv_i64m2_tu (vint64m2_t vd, vint64m2_t vs2, vint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i64m2_tu (vd, vs2, vs1, vl); +} + +vint64m4_t +test_vile_vv_i64m4_tu (vint64m4_t vd, vint64m4_t vs2, vint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i64m4_tu (vd, vs2, vs1, vl); +} + +vint64m8_t +test_vile_vv_i64m8_tu (vint64m8_t vd, vint64m8_t vs2, vint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_i64m8_tu (vd, vs2, vs1, vl); +} + +vuint8mf8_t +test_vile_vv_u8mf8_tu (vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u8mf8_tu (vd, vs2, vs1, vl); +} + +vuint8mf4_t +test_vile_vv_u8mf4_tu (vuint8mf4_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u8mf4_tu (vd, vs2, vs1, vl); +} + +vuint8mf2_t +test_vile_vv_u8mf2_tu (vuint8mf2_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u8mf2_tu (vd, vs2, vs1, vl); +} + +vuint8m1_t +test_vile_vv_u8m1_tu (vuint8m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u8m1_tu (vd, vs2, vs1, vl); +} + +vuint8m2_t +test_vile_vv_u8m2_tu (vuint8m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u8m2_tu (vd, vs2, vs1, vl); +} + +vuint8m4_t +test_vile_vv_u8m4_tu (vuint8m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u8m4_tu (vd, vs2, vs1, vl); +} + +vuint8m8_t +test_vile_vv_u8m8_tu (vuint8m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_vv_u8m8_tu (vd, vs2, vs1, vl); +} + +vuint16mf4_t +test_vile_vv_u16mf4_tu (vuint16mf4_t vd, vuint16mf4_t vs2, vuint16mf4_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u16mf4_tu (vd, vs2, vs1, vl); +} + +vuint16mf2_t +test_vile_vv_u16mf2_tu (vuint16mf2_t vd, vuint16mf2_t vs2, vuint16mf2_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u16mf2_tu (vd, vs2, vs1, vl); +} + +vuint16m1_t +test_vile_vv_u16m1_tu (vuint16m1_t vd, vuint16m1_t vs2, vuint16m1_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u16m1_tu (vd, vs2, vs1, vl); +} + +vuint16m2_t +test_vile_vv_u16m2_tu (vuint16m2_t vd, vuint16m2_t vs2, vuint16m2_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u16m2_tu (vd, vs2, vs1, vl); +} + +vuint16m4_t +test_vile_vv_u16m4_tu (vuint16m4_t vd, vuint16m4_t vs2, vuint16m4_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u16m4_tu (vd, vs2, vs1, vl); +} + +vuint16m8_t +test_vile_vv_u16m8_tu (vuint16m8_t vd, vuint16m8_t vs2, vuint16m8_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u16m8_tu (vd, vs2, vs1, vl); +} + +vuint32mf2_t +test_vile_vv_u32mf2_tu (vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u32mf2_tu (vd, vs2, vs1, vl); +} + +vuint32m1_t +test_vile_vv_u32m1_tu (vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u32m1_tu (vd, vs2, vs1, vl); +} + +vuint32m2_t +test_vile_vv_u32m2_tu (vuint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u32m2_tu (vd, vs2, vs1, vl); +} + +vuint32m4_t +test_vile_vv_u32m4_tu (vuint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u32m4_tu (vd, vs2, vs1, vl); +} + +vuint32m8_t +test_vile_vv_u32m8_tu (vuint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u32m8_tu (vd, vs2, vs1, vl); +} + +vuint64m1_t +test_vile_vv_u64m1_tu (vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u64m1_tu (vd, vs2, vs1, vl); +} + +vuint64m2_t +test_vile_vv_u64m2_tu (vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u64m2_tu (vd, vs2, vs1, vl); +} + +vuint64m4_t +test_vile_vv_u64m4_tu (vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u64m4_tu (vd, vs2, vs1, vl); +} + +vuint64m8_t +test_vile_vv_u64m8_tu (vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, + size_t vl) +{ + return __riscv_xt_vile_vv_u64m8_tu (vd, vs2, vs1, vl); +} + +/* { dg-final { scan-assembler-times "xt\\.vile\\.vv\t" 88 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vile_vv_overloaded.c b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vile_vv_overloaded.c new file mode 100644 index 00000000000..06112efca42 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vile_vv_overloaded.c @@ -0,0 +1,535 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_xxtvarith -mabi=ilp32d" { target { rv32 } } } */ +/* { dg-options "-march=rv64gcv_xxtvarith -mabi=lp64d" { target { rv64 } } } */ + +#include "xuantie_vector.h" + +vint8mf8_t +test0_vile (vint8mf8_t vs2, vint8mf8_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint8mf4_t +test1_vile (vint8mf4_t vs2, vint8mf4_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint8mf2_t +test2_vile (vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint8m1_t +test3_vile (vint8m1_t vs2, vint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint8m2_t +test4_vile (vint8m2_t vs2, vint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint8m4_t +test5_vile (vint8m4_t vs2, vint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint8m8_t +test6_vile (vint8m8_t vs2, vint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint16mf4_t +test7_vile (vint16mf4_t vs2, vint16mf4_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint16mf2_t +test8_vile (vint16mf2_t vs2, vint16mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint16m1_t +test9_vile (vint16m1_t vs2, vint16m1_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint16m2_t +test10_vile (vint16m2_t vs2, vint16m2_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint16m4_t +test11_vile (vint16m4_t vs2, vint16m4_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint16m8_t +test12_vile (vint16m8_t vs2, vint16m8_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint32mf2_t +test13_vile (vint32mf2_t vs2, vint32mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint32m1_t +test14_vile (vint32m1_t vs2, vint32m1_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint32m2_t +test15_vile (vint32m2_t vs2, vint32m2_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint32m4_t +test16_vile (vint32m4_t vs2, vint32m4_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint32m8_t +test17_vile (vint32m8_t vs2, vint32m8_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint64m1_t +test18_vile (vint64m1_t vs2, vint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint64m2_t +test19_vile (vint64m2_t vs2, vint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint64m4_t +test20_vile (vint64m4_t vs2, vint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vint64m8_t +test21_vile (vint64m8_t vs2, vint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint8mf8_t +test22_vile (vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint8mf4_t +test23_vile (vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint8mf2_t +test24_vile (vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint8m1_t +test25_vile (vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint8m2_t +test26_vile (vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint8m4_t +test27_vile (vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint8m8_t +test28_vile (vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint16mf4_t +test29_vile (vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint16mf2_t +test30_vile (vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint16m1_t +test31_vile (vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint16m2_t +test32_vile (vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint16m4_t +test33_vile (vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint16m8_t +test34_vile (vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint32mf2_t +test35_vile (vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint32m1_t +test36_vile (vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint32m2_t +test37_vile (vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint32m4_t +test38_vile (vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint32m8_t +test39_vile (vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint64m1_t +test40_vile (vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint64m2_t +test41_vile (vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint64m4_t +test42_vile (vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +} + +vuint64m8_t +test43_vile (vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vile (vs2, vs1, vl); +}; + +vint8mf8_t +test45_vile_tu (vint8mf8_t vd, vint8mf8_t vs2, vint8mf8_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint8mf4_t +test46_vile_tu (vint8mf4_t vd, vint8mf4_t vs2, vint8mf4_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint8mf2_t +test47_vile_tu (vint8mf2_t vd, vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint8m1_t +test48_vile_tu (vint8m1_t vd, vint8m1_t vs2, vint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint8m2_t +test49_vile_tu (vint8m2_t vd, vint8m2_t vs2, vint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint8m4_t +test50_vile_tu (vint8m4_t vd, vint8m4_t vs2, vint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint8m8_t +test51_vile_tu (vint8m8_t vd, vint8m8_t vs2, vint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint16mf4_t +test52_vile_tu (vint16mf4_t vd, vint16mf4_t vs2, vint16mf4_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint16mf2_t +test53_vile_tu (vint16mf2_t vd, vint16mf2_t vs2, vint16mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint16m1_t +test54_vile_tu (vint16m1_t vd, vint16m1_t vs2, vint16m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint16m2_t +test55_vile_tu (vint16m2_t vd, vint16m2_t vs2, vint16m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint16m4_t +test56_vile_tu (vint16m4_t vd, vint16m4_t vs2, vint16m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint16m8_t +test57_vile_tu (vint16m8_t vd, vint16m8_t vs2, vint16m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint32mf2_t +test58_vile_tu (vint32mf2_t vd, vint32mf2_t vs2, vint32mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint32m1_t +test59_vile_tu (vint32m1_t vd, vint32m1_t vs2, vint32m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint32m2_t +test60_vile_tu (vint32m2_t vd, vint32m2_t vs2, vint32m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint32m4_t +test61_vile_tu (vint32m4_t vd, vint32m4_t vs2, vint32m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint32m8_t +test62_vile_tu (vint32m8_t vd, vint32m8_t vs2, vint32m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint64m1_t +test63_vile_tu (vint64m1_t vd, vint64m1_t vs2, vint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint64m2_t +test64_vile_tu (vint64m2_t vd, vint64m2_t vs2, vint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint64m4_t +test65_vile_tu (vint64m4_t vd, vint64m4_t vs2, vint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vint64m8_t +test66_vile_tu (vint64m8_t vd, vint64m8_t vs2, vint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint8mf8_t +test67_vile_tu (vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint8mf4_t +test68_vile_tu (vuint8mf4_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint8mf2_t +test69_vile_tu (vuint8mf2_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint8m1_t +test70_vile_tu (vuint8m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint8m2_t +test71_vile_tu (vuint8m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint8m4_t +test72_vile_tu (vuint8m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint8m8_t +test73_vile_tu (vuint8m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint16mf4_t +test74_vile_tu (vuint16mf4_t vd, vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint16mf2_t +test75_vile_tu (vuint16mf2_t vd, vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint16m1_t +test76_vile_tu (vuint16m1_t vd, vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint16m2_t +test77_vile_tu (vuint16m2_t vd, vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint16m4_t +test78_vile_tu (vuint16m4_t vd, vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint16m8_t +test79_vile_tu (vuint16m8_t vd, vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint32mf2_t +test80_vile_tu (vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint32m1_t +test81_vile_tu (vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint32m2_t +test82_vile_tu (vuint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint32m4_t +test83_vile_tu (vuint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint32m8_t +test84_vile_tu (vuint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint64m1_t +test85_vile_tu (vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint64m2_t +test86_vile_tu (vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint64m4_t +test87_vile_tu (vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +vuint64m8_t +test88_vile_tu (vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vile_tu (vd, vs2, vs1, vl); +} + +/* { dg-final { scan-assembler-times "xt\\.vile\\.vv\t" 88 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vilo_vv_non_overloaded.c b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vilo_vv_non_overloaded.c new file mode 100644 index 00000000000..744db99e342 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vilo_vv_non_overloaded.c @@ -0,0 +1,556 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_xxtvarith -mabi=ilp32d" { target { rv32 } } } */ +/* { dg-options "-march=rv64gcv_xxtvarith -mabi=lp64d" { target { rv64 } } } */ + +#include "xuantie_vector.h" + +vint8mf8_t +test_vilo_vv_i8mf8 (vint8mf8_t vs2, vint8mf8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i8mf8 (vs2, vs1, vl); +} + +vint8mf4_t +test_vilo_vv_i8mf4 (vint8mf4_t vs2, vint8mf4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i8mf4 (vs2, vs1, vl); +} + +vint8mf2_t +test_vilo_vv_i8mf2 (vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i8mf2 (vs2, vs1, vl); +} + +vint8m1_t +test_vilo_vv_i8m1 (vint8m1_t vs2, vint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i8m1 (vs2, vs1, vl); +} + +vint8m2_t +test_vilo_vv_i8m2 (vint8m2_t vs2, vint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i8m2 (vs2, vs1, vl); +} + +vint8m4_t +test_vilo_vv_i8m4 (vint8m4_t vs2, vint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i8m4 (vs2, vs1, vl); +} + +vint8m8_t +test_vilo_vv_i8m8 (vint8m8_t vs2, vint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i8m8 (vs2, vs1, vl); +} + +vint16mf4_t +test_vilo_vv_i16mf4 (vint16mf4_t vs2, vint16mf4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i16mf4 (vs2, vs1, vl); +} + +vint16mf2_t +test_vilo_vv_i16mf2 (vint16mf2_t vs2, vint16mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i16mf2 (vs2, vs1, vl); +} + +vint16m1_t +test_vilo_vv_i16m1 (vint16m1_t vs2, vint16m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i16m1 (vs2, vs1, vl); +} + +vint16m2_t +test_vilo_vv_i16m2 (vint16m2_t vs2, vint16m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i16m2 (vs2, vs1, vl); +} + +vint16m4_t +test_vilo_vv_i16m4 (vint16m4_t vs2, vint16m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i16m4 (vs2, vs1, vl); +} + +vint16m8_t +test_vilo_vv_i16m8 (vint16m8_t vs2, vint16m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i16m8 (vs2, vs1, vl); +} + +vint32mf2_t +test_vilo_vv_i32mf2 (vint32mf2_t vs2, vint32mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i32mf2 (vs2, vs1, vl); +} + +vint32m1_t +test_vilo_vv_i32m1 (vint32m1_t vs2, vint32m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i32m1 (vs2, vs1, vl); +} + +vint32m2_t +test_vilo_vv_i32m2 (vint32m2_t vs2, vint32m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i32m2 (vs2, vs1, vl); +} + +vint32m4_t +test_vilo_vv_i32m4 (vint32m4_t vs2, vint32m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i32m4 (vs2, vs1, vl); +} + +vint32m8_t +test_vilo_vv_i32m8 (vint32m8_t vs2, vint32m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i32m8 (vs2, vs1, vl); +} + +vint64m1_t +test_vilo_vv_i64m1 (vint64m1_t vs2, vint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i64m1 (vs2, vs1, vl); +} + +vint64m2_t +test_vilo_vv_i64m2 (vint64m2_t vs2, vint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i64m2 (vs2, vs1, vl); +} + +vint64m4_t +test_vilo_vv_i64m4 (vint64m4_t vs2, vint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i64m4 (vs2, vs1, vl); +} + +vint64m8_t +test_vilo_vv_i64m8 (vint64m8_t vs2, vint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i64m8 (vs2, vs1, vl); +} + +vuint8mf8_t +test_vilo_vv_u8mf8 (vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u8mf8 (vs2, vs1, vl); +} + +vuint8mf4_t +test_vilo_vv_u8mf4 (vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u8mf4 (vs2, vs1, vl); +} + +vuint8mf2_t +test_vilo_vv_u8mf2 (vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u8mf2 (vs2, vs1, vl); +} + +vuint8m1_t +test_vilo_vv_u8m1 (vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u8m1 (vs2, vs1, vl); +} + +vuint8m2_t +test_vilo_vv_u8m2 (vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u8m2 (vs2, vs1, vl); +} + +vuint8m4_t +test_vilo_vv_u8m4 (vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u8m4 (vs2, vs1, vl); +} + +vuint8m8_t +test_vilo_vv_u8m8 (vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u8m8 (vs2, vs1, vl); +} + +vuint16mf4_t +test_vilo_vv_u16mf4 (vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u16mf4 (vs2, vs1, vl); +} + +vuint16mf2_t +test_vilo_vv_u16mf2 (vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u16mf2 (vs2, vs1, vl); +} + +vuint16m1_t +test_vilo_vv_u16m1 (vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u16m1 (vs2, vs1, vl); +} + +vuint16m2_t +test_vilo_vv_u16m2 (vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u16m2 (vs2, vs1, vl); +} + +vuint16m4_t +test_vilo_vv_u16m4 (vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u16m4 (vs2, vs1, vl); +} + +vuint16m8_t +test_vilo_vv_u16m8 (vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u16m8 (vs2, vs1, vl); +} + +vuint32mf2_t +test_vilo_vv_u32mf2 (vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u32mf2 (vs2, vs1, vl); +} + +vuint32m1_t +test_vilo_vv_u32m1 (vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u32m1 (vs2, vs1, vl); +} + +vuint32m2_t +test_vilo_vv_u32m2 (vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u32m2 (vs2, vs1, vl); +} + +vuint32m4_t +test_vilo_vv_u32m4 (vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u32m4 (vs2, vs1, vl); +} + +vuint32m8_t +test_vilo_vv_u32m8 (vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u32m8 (vs2, vs1, vl); +} + +vuint64m1_t +test_vilo_vv_u64m1 (vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u64m1 (vs2, vs1, vl); +} + +vuint64m2_t +test_vilo_vv_u64m2 (vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u64m2 (vs2, vs1, vl); +} + +vuint64m4_t +test_vilo_vv_u64m4 (vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u64m4 (vs2, vs1, vl); +} + +vuint64m8_t +test_vilo_vv_u64m8 (vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u64m8 (vs2, vs1, vl); +} + +vint8mf8_t +test_vilo_vv_i8mf8_tu (vint8mf8_t vd, vint8mf8_t vs2, vint8mf8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i8mf8_tu (vd, vs2, vs1, vl); +} + +vint8mf4_t +test_vilo_vv_i8mf4_tu (vint8mf4_t vd, vint8mf4_t vs2, vint8mf4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i8mf4_tu (vd, vs2, vs1, vl); +} + +vint8mf2_t +test_vilo_vv_i8mf2_tu (vint8mf2_t vd, vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i8mf2_tu (vd, vs2, vs1, vl); +} + +vint8m1_t +test_vilo_vv_i8m1_tu (vint8m1_t vd, vint8m1_t vs2, vint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i8m1_tu (vd, vs2, vs1, vl); +} + +vint8m2_t +test_vilo_vv_i8m2_tu (vint8m2_t vd, vint8m2_t vs2, vint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i8m2_tu (vd, vs2, vs1, vl); +} + +vint8m4_t +test_vilo_vv_i8m4_tu (vint8m4_t vd, vint8m4_t vs2, vint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i8m4_tu (vd, vs2, vs1, vl); +} + +vint8m8_t +test_vilo_vv_i8m8_tu (vint8m8_t vd, vint8m8_t vs2, vint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i8m8_tu (vd, vs2, vs1, vl); +} + +vint16mf4_t +test_vilo_vv_i16mf4_tu (vint16mf4_t vd, vint16mf4_t vs2, vint16mf4_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_i16mf4_tu (vd, vs2, vs1, vl); +} + +vint16mf2_t +test_vilo_vv_i16mf2_tu (vint16mf2_t vd, vint16mf2_t vs2, vint16mf2_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_i16mf2_tu (vd, vs2, vs1, vl); +} + +vint16m1_t +test_vilo_vv_i16m1_tu (vint16m1_t vd, vint16m1_t vs2, vint16m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i16m1_tu (vd, vs2, vs1, vl); +} + +vint16m2_t +test_vilo_vv_i16m2_tu (vint16m2_t vd, vint16m2_t vs2, vint16m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i16m2_tu (vd, vs2, vs1, vl); +} + +vint16m4_t +test_vilo_vv_i16m4_tu (vint16m4_t vd, vint16m4_t vs2, vint16m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i16m4_tu (vd, vs2, vs1, vl); +} + +vint16m8_t +test_vilo_vv_i16m8_tu (vint16m8_t vd, vint16m8_t vs2, vint16m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i16m8_tu (vd, vs2, vs1, vl); +} + +vint32mf2_t +test_vilo_vv_i32mf2_tu (vint32mf2_t vd, vint32mf2_t vs2, vint32mf2_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_i32mf2_tu (vd, vs2, vs1, vl); +} + +vint32m1_t +test_vilo_vv_i32m1_tu (vint32m1_t vd, vint32m1_t vs2, vint32m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i32m1_tu (vd, vs2, vs1, vl); +} + +vint32m2_t +test_vilo_vv_i32m2_tu (vint32m2_t vd, vint32m2_t vs2, vint32m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i32m2_tu (vd, vs2, vs1, vl); +} + +vint32m4_t +test_vilo_vv_i32m4_tu (vint32m4_t vd, vint32m4_t vs2, vint32m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i32m4_tu (vd, vs2, vs1, vl); +} + +vint32m8_t +test_vilo_vv_i32m8_tu (vint32m8_t vd, vint32m8_t vs2, vint32m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i32m8_tu (vd, vs2, vs1, vl); +} + +vint64m1_t +test_vilo_vv_i64m1_tu (vint64m1_t vd, vint64m1_t vs2, vint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i64m1_tu (vd, vs2, vs1, vl); +} + +vint64m2_t +test_vilo_vv_i64m2_tu (vint64m2_t vd, vint64m2_t vs2, vint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i64m2_tu (vd, vs2, vs1, vl); +} + +vint64m4_t +test_vilo_vv_i64m4_tu (vint64m4_t vd, vint64m4_t vs2, vint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i64m4_tu (vd, vs2, vs1, vl); +} + +vint64m8_t +test_vilo_vv_i64m8_tu (vint64m8_t vd, vint64m8_t vs2, vint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_i64m8_tu (vd, vs2, vs1, vl); +} + +vuint8mf8_t +test_vilo_vv_u8mf8_tu (vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u8mf8_tu (vd, vs2, vs1, vl); +} + +vuint8mf4_t +test_vilo_vv_u8mf4_tu (vuint8mf4_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u8mf4_tu (vd, vs2, vs1, vl); +} + +vuint8mf2_t +test_vilo_vv_u8mf2_tu (vuint8mf2_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u8mf2_tu (vd, vs2, vs1, vl); +} + +vuint8m1_t +test_vilo_vv_u8m1_tu (vuint8m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u8m1_tu (vd, vs2, vs1, vl); +} + +vuint8m2_t +test_vilo_vv_u8m2_tu (vuint8m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u8m2_tu (vd, vs2, vs1, vl); +} + +vuint8m4_t +test_vilo_vv_u8m4_tu (vuint8m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u8m4_tu (vd, vs2, vs1, vl); +} + +vuint8m8_t +test_vilo_vv_u8m8_tu (vuint8m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_vv_u8m8_tu (vd, vs2, vs1, vl); +} + +vuint16mf4_t +test_vilo_vv_u16mf4_tu (vuint16mf4_t vd, vuint16mf4_t vs2, vuint16mf4_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u16mf4_tu (vd, vs2, vs1, vl); +} + +vuint16mf2_t +test_vilo_vv_u16mf2_tu (vuint16mf2_t vd, vuint16mf2_t vs2, vuint16mf2_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u16mf2_tu (vd, vs2, vs1, vl); +} + +vuint16m1_t +test_vilo_vv_u16m1_tu (vuint16m1_t vd, vuint16m1_t vs2, vuint16m1_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u16m1_tu (vd, vs2, vs1, vl); +} + +vuint16m2_t +test_vilo_vv_u16m2_tu (vuint16m2_t vd, vuint16m2_t vs2, vuint16m2_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u16m2_tu (vd, vs2, vs1, vl); +} + +vuint16m4_t +test_vilo_vv_u16m4_tu (vuint16m4_t vd, vuint16m4_t vs2, vuint16m4_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u16m4_tu (vd, vs2, vs1, vl); +} + +vuint16m8_t +test_vilo_vv_u16m8_tu (vuint16m8_t vd, vuint16m8_t vs2, vuint16m8_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u16m8_tu (vd, vs2, vs1, vl); +} + +vuint32mf2_t +test_vilo_vv_u32mf2_tu (vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u32mf2_tu (vd, vs2, vs1, vl); +} + +vuint32m1_t +test_vilo_vv_u32m1_tu (vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u32m1_tu (vd, vs2, vs1, vl); +} + +vuint32m2_t +test_vilo_vv_u32m2_tu (vuint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u32m2_tu (vd, vs2, vs1, vl); +} + +vuint32m4_t +test_vilo_vv_u32m4_tu (vuint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u32m4_tu (vd, vs2, vs1, vl); +} + +vuint32m8_t +test_vilo_vv_u32m8_tu (vuint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u32m8_tu (vd, vs2, vs1, vl); +} + +vuint64m1_t +test_vilo_vv_u64m1_tu (vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u64m1_tu (vd, vs2, vs1, vl); +} + +vuint64m2_t +test_vilo_vv_u64m2_tu (vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u64m2_tu (vd, vs2, vs1, vl); +} + +vuint64m4_t +test_vilo_vv_u64m4_tu (vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u64m4_tu (vd, vs2, vs1, vl); +} + +vuint64m8_t +test_vilo_vv_u64m8_tu (vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, + size_t vl) +{ + return __riscv_xt_vilo_vv_u64m8_tu (vd, vs2, vs1, vl); +} + +/* { dg-final { scan-assembler-times "xt\\.vilo\\.vv\t" 88 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vilo_vv_overloaded.c b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vilo_vv_overloaded.c new file mode 100644 index 00000000000..4ab3045ed0e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xxtvector/xxtvarith_vilo_vv_overloaded.c @@ -0,0 +1,535 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_xxtvarith -mabi=ilp32d" { target { rv32 } } } */ +/* { dg-options "-march=rv64gcv_xxtvarith -mabi=lp64d" { target { rv64 } } } */ + +#include "xuantie_vector.h" + +vint8mf8_t +test0_vilo (vint8mf8_t vs2, vint8mf8_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint8mf4_t +test1_vilo (vint8mf4_t vs2, vint8mf4_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint8mf2_t +test2_vilo (vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint8m1_t +test3_vilo (vint8m1_t vs2, vint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint8m2_t +test4_vilo (vint8m2_t vs2, vint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint8m4_t +test5_vilo (vint8m4_t vs2, vint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint8m8_t +test6_vilo (vint8m8_t vs2, vint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint16mf4_t +test7_vilo (vint16mf4_t vs2, vint16mf4_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint16mf2_t +test8_vilo (vint16mf2_t vs2, vint16mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint16m1_t +test9_vilo (vint16m1_t vs2, vint16m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint16m2_t +test10_vilo (vint16m2_t vs2, vint16m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint16m4_t +test11_vilo (vint16m4_t vs2, vint16m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint16m8_t +test12_vilo (vint16m8_t vs2, vint16m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint32mf2_t +test13_vilo (vint32mf2_t vs2, vint32mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint32m1_t +test14_vilo (vint32m1_t vs2, vint32m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint32m2_t +test15_vilo (vint32m2_t vs2, vint32m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint32m4_t +test16_vilo (vint32m4_t vs2, vint32m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint32m8_t +test17_vilo (vint32m8_t vs2, vint32m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint64m1_t +test18_vilo (vint64m1_t vs2, vint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint64m2_t +test19_vilo (vint64m2_t vs2, vint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint64m4_t +test20_vilo (vint64m4_t vs2, vint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vint64m8_t +test21_vilo (vint64m8_t vs2, vint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint8mf8_t +test22_vilo (vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint8mf4_t +test23_vilo (vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint8mf2_t +test24_vilo (vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint8m1_t +test25_vilo (vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint8m2_t +test26_vilo (vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint8m4_t +test27_vilo (vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint8m8_t +test28_vilo (vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint16mf4_t +test29_vilo (vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint16mf2_t +test30_vilo (vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint16m1_t +test31_vilo (vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint16m2_t +test32_vilo (vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint16m4_t +test33_vilo (vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint16m8_t +test34_vilo (vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint32mf2_t +test35_vilo (vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint32m1_t +test36_vilo (vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint32m2_t +test37_vilo (vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint32m4_t +test38_vilo (vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint32m8_t +test39_vilo (vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint64m1_t +test40_vilo (vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint64m2_t +test41_vilo (vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint64m4_t +test42_vilo (vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +} + +vuint64m8_t +test43_vilo (vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo (vs2, vs1, vl); +}; + +vint8mf8_t +test45_vilo_tu (vint8mf8_t vd, vint8mf8_t vs2, vint8mf8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint8mf4_t +test46_vilo_tu (vint8mf4_t vd, vint8mf4_t vs2, vint8mf4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint8mf2_t +test47_vilo_tu (vint8mf2_t vd, vint8mf2_t vs2, vint8mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint8m1_t +test48_vilo_tu (vint8m1_t vd, vint8m1_t vs2, vint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint8m2_t +test49_vilo_tu (vint8m2_t vd, vint8m2_t vs2, vint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint8m4_t +test50_vilo_tu (vint8m4_t vd, vint8m4_t vs2, vint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint8m8_t +test51_vilo_tu (vint8m8_t vd, vint8m8_t vs2, vint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint16mf4_t +test52_vilo_tu (vint16mf4_t vd, vint16mf4_t vs2, vint16mf4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint16mf2_t +test53_vilo_tu (vint16mf2_t vd, vint16mf2_t vs2, vint16mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint16m1_t +test54_vilo_tu (vint16m1_t vd, vint16m1_t vs2, vint16m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint16m2_t +test55_vilo_tu (vint16m2_t vd, vint16m2_t vs2, vint16m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint16m4_t +test56_vilo_tu (vint16m4_t vd, vint16m4_t vs2, vint16m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint16m8_t +test57_vilo_tu (vint16m8_t vd, vint16m8_t vs2, vint16m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint32mf2_t +test58_vilo_tu (vint32mf2_t vd, vint32mf2_t vs2, vint32mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint32m1_t +test59_vilo_tu (vint32m1_t vd, vint32m1_t vs2, vint32m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint32m2_t +test60_vilo_tu (vint32m2_t vd, vint32m2_t vs2, vint32m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint32m4_t +test61_vilo_tu (vint32m4_t vd, vint32m4_t vs2, vint32m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint32m8_t +test62_vilo_tu (vint32m8_t vd, vint32m8_t vs2, vint32m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint64m1_t +test63_vilo_tu (vint64m1_t vd, vint64m1_t vs2, vint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint64m2_t +test64_vilo_tu (vint64m2_t vd, vint64m2_t vs2, vint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint64m4_t +test65_vilo_tu (vint64m4_t vd, vint64m4_t vs2, vint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vint64m8_t +test66_vilo_tu (vint64m8_t vd, vint64m8_t vs2, vint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint8mf8_t +test67_vilo_tu (vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint8mf4_t +test68_vilo_tu (vuint8mf4_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint8mf2_t +test69_vilo_tu (vuint8mf2_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint8m1_t +test70_vilo_tu (vuint8m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint8m2_t +test71_vilo_tu (vuint8m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint8m4_t +test72_vilo_tu (vuint8m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint8m8_t +test73_vilo_tu (vuint8m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint16mf4_t +test74_vilo_tu (vuint16mf4_t vd, vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint16mf2_t +test75_vilo_tu (vuint16mf2_t vd, vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint16m1_t +test76_vilo_tu (vuint16m1_t vd, vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint16m2_t +test77_vilo_tu (vuint16m2_t vd, vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint16m4_t +test78_vilo_tu (vuint16m4_t vd, vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint16m8_t +test79_vilo_tu (vuint16m8_t vd, vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint32mf2_t +test80_vilo_tu (vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint32m1_t +test81_vilo_tu (vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint32m2_t +test82_vilo_tu (vuint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint32m4_t +test83_vilo_tu (vuint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint32m8_t +test84_vilo_tu (vuint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint64m1_t +test85_vilo_tu (vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint64m2_t +test86_vilo_tu (vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint64m4_t +test87_vilo_tu (vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +vuint64m8_t +test88_vilo_tu (vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) +{ + return __riscv_xt_vilo_tu (vd, vs2, vs1, vl); +} + +/* { dg-final { scan-assembler-times "xt\\.vilo\\.vv\t" 88 } } */ -- 2.47.1
