Hi Roger,
The patch LGTM with below changes:
> (define_insn "*movti_internal"
> [(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,v,v ,v
> ,m,?jc,?Yd")
> - (match_operand:TI 1 "general_operand" "riFo,re,C,BC,vm,v,Yd,jc"))]
> + (match_operand:TI 1 "general_operand" "riFo,re,C,BC,vm,v,YD,jc"))]
The pattern is ok, but we also need to change inline_secondary_memory_needed to
allow direct move from SSE to GPR w/o SSE4.1, otherwise LRA still inserts a
spill for that even with the patch.
And the direction must be SSE->GPR since we haven't extend GPR->SSE direction.
So add below code to inline_secondary_memory_needed in the block of
if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
{
...
/* Moves from SSE_REGS to GENERAL_REGS need only SSE2:
*movti_internal splits them into movq + shufpd + movq. */
if (TARGET_64BIT && mode == TImode && SSE_CLASS_P (class1))
return false;
...
}
> In theory, this could
> also check TARGET_INTER_UNIT_MOVES_FROM_VEC (when SSE2 but not SSE4_1)
> but I'm not sure that the possible benefit is worth the added complexity.
No need - *movti_internal's preferred_for_speed already gates alternative
6 on TARGET_INTER_UNIT_MOVES_FROM_VEC.
