LGTM,
Claudiu

On Fri, Sep 11, 2026 at 12:56 PM Michiel Derhaeg <[email protected]> wrote:
>
> From: Michiel Derhaeg <[email protected]>
>
> <voptab>v2si3 advertised V2SImode optabs (mul/div/smin/smax) whenever the
> scalar op existed, but V2SImode is only a supported vector mode under
> TARGET_PLUS_QMACW.
>
> Since r15-5493-g485ab50c204ddb ("Add helpers to test whether an optab
> can be implemented") the middle-end keeps the operation vectorized on
> such cores.  The operands degrade to DImode and it is expanded as a
> double-word scalar op: mul and div silently compute on the packed pair,
> min and max ICE in expand_expr_real_2 for lack of a DImode expansion.
>
> Require TARGET_PLUS_QMACW so the optab matches
> arc_vector_mode_supported_p.
>
> No tests added because this is already covered by existing tests.
>
> Every core without TARGET_PLUS_QMACW, since smin/smax are advertised
> unconditionally, e.g. -mcpu=em, ICEs in expand_expr_real_2 on:
>
>         g++.dg/ext/vector21.C    -std=gnu++{98,20,29}
>         g++.dg/opt/vectcond-1.C  -std=gnu++{98,20,29}
>         g++.dg/pr94920-1.C       -std=c++{98,20,29}
>
> Cores that also have a multiplier or divider but no QMACW (arcem, em4_*,
> hs3*, archs) additionally miscompile the following:
>
>         gcc.c-torture/execute/pr23135.c
>         gcc.c-torture/execute/pr53645.c
>         gcc.c-torture/execute/scal-to-vec2.c
>         gcc.c-torture/execute/simd-1.c
>         gcc.dg/pr88598-4.c
>
>         PR target/126243
>
> gcc/ChangeLog:
>         * config/arc/simdext.md (<voptab>v2si3): Require TARGET_PLUS_QMACW.
>
> Signed-off-by: Michiel Derhaeg <[email protected]>
> ---
> v2: Added test failure info & mention PR
>
>  gcc/config/arc/simdext.md | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
> index 003f2c4e6e6..509ca55d3f2 100644
> --- a/gcc/config/arc/simdext.md
> +++ b/gcc/config/arc/simdext.md
> @@ -2010,7 +2010,7 @@
>    [(set (match_operand:V2SI 0 "register_operand" "=r")
>         (EMUVEC:V2SI (match_operand:V2SI 1 "register_operand" "r")
>                      (match_operand:V2SI 2 "nonmemory_operand" "ri")))]
> -  ""
> +  "TARGET_PLUS_QMACW"
>    "#"
>    "reload_completed"
>    [(const_int 0)]
> --
> 2.54.0
>

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