In addition, disable HSSR code gen for several tests as these cause the
tests to break.
For instance, the peeling tests no longer peel when using hssr,
breaking the test. This prevents other similar spurious failures.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/ffr_1.c: New test.
* gcc.target/aarch64/sve/ffr_2.c: New test.
* gcc.target/aarch64/sve/ffr_3.c: New test.
* gcc.target/aarch64/sve/ffr_4.c: New test.
* gcc.target/aarch64/sve/noeffect11.c: Update to disable HSSR
codegen which breaks the test spuriously.
* gcc.target/aarch64/sve/peel_ind_1.c: Likewise.
* gcc.target/aarch64/sve/peel_ind_11.c: Likewise.
* gcc.target/aarch64/sve/peel_ind_12.c: Likewise.
* gcc.target/aarch64/sve/peel_ind_13.c: Likewise.
* gcc.target/aarch64/sve/peel_ind_14.c: Likewise.
* gcc.target/aarch64/sve/peel_ind_15.c: Likewise.
* gcc.target/aarch64/sve/peel_ind_16.c: Likewise.
* gcc.target/aarch64/sve/peel_ind_17.c: Likewise.
* gcc.target/aarch64/sve/peel_ind_2.c: Likewise.
* gcc.target/aarch64/sve/peel_ind_3.c: Likewise.
* gcc.target/aarch64/sve/peel_ind_4.c: Likewise.
* gcc.target/aarch64/sve/peel_ind_5.c: Likewise.
* gcc.target/aarch64/sve/peel_ind_6.c: Likewise.
* gcc.target/aarch64/sve/peel_ind_7.c: Likewise.
* gcc.target/aarch64/sve/peel_ind_8.c: Likewise.
* gcc.target/aarch64/sve/peel_ind_9.c: Likewise.
* gcc.target/aarch64/sve/peeled.c: Likewise.
* gcc.target/aarch64/sve/peeled1.c: Likewise.
* gcc.target/aarch64/sve/peeled2.c: Likewise.
* gcc.target/aarch64/sve/peeled3.c: Likewise.
* gcc.target/aarch64/sve/pr119351.c: Likewise.
---
gcc/testsuite/gcc.target/aarch64/sve/ffr_1.c | 16 +++++++
gcc/testsuite/gcc.target/aarch64/sve/ffr_2.c | 44 +++++++++++++++++++
gcc/testsuite/gcc.target/aarch64/sve/ffr_3.c | 21 +++++++++
gcc/testsuite/gcc.target/aarch64/sve/ffr_4.c | 21 +++++++++
.../gcc.target/aarch64/sve/noeffect11.c | 2 +-
.../gcc.target/aarch64/sve/peel_ind_1.c | 2 +-
.../gcc.target/aarch64/sve/peel_ind_11.c | 2 +-
.../gcc.target/aarch64/sve/peel_ind_12.c | 2 +-
.../gcc.target/aarch64/sve/peel_ind_13.c | 2 +-
.../gcc.target/aarch64/sve/peel_ind_14.c | 2 +-
.../gcc.target/aarch64/sve/peel_ind_15.c | 2 +-
.../gcc.target/aarch64/sve/peel_ind_16.c | 2 +-
.../gcc.target/aarch64/sve/peel_ind_17.c | 2 +-
.../gcc.target/aarch64/sve/peel_ind_2.c | 2 +-
.../gcc.target/aarch64/sve/peel_ind_3.c | 2 +-
.../gcc.target/aarch64/sve/peel_ind_4.c | 2 +-
.../gcc.target/aarch64/sve/peel_ind_5.c | 2 +-
.../gcc.target/aarch64/sve/peel_ind_6.c | 2 +-
.../gcc.target/aarch64/sve/peel_ind_7.c | 2 +-
.../gcc.target/aarch64/sve/peel_ind_8.c | 2 +-
.../gcc.target/aarch64/sve/peel_ind_9.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/peeled.c | 2 +-
.../gcc.target/aarch64/sve/peeled1.c | 2 +-
.../gcc.target/aarch64/sve/peeled2.c | 2 +-
.../gcc.target/aarch64/sve/peeled3.c | 2 +-
.../gcc.target/aarch64/sve/pr119351.c | 2 +-
26 files changed, 124 insertions(+), 22 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/ffr_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/ffr_2.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/ffr_3.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/ffr_4.c
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/ffr_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/ffr_1.c
new file mode 100644
index 00000000000..361e4ea9c9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/ffr_1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fdump-tree-vect-details --save-temps
--param=vect-hssr-usage=3" } */
+
+#include <stdint.h>
+
+int foo (int *restrict a, int *restrict b, int N) {
+ for (int i = 0; i < N; i++)
+ {
+ if (a[i] == b[i])
+ return 1;
+ }
+ return 0;
+}
+
+/* { dg-final { scan-tree-dump "Will use HSSR" "vect" } } */
+/* { dg-final { scan-assembler-times {\tldff1w\tz[0-9]+\.s, p[0-9]+/z,} 2 } }
*/
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/ffr_2.c
b/gcc/testsuite/gcc.target/aarch64/sve/ffr_2.c
new file mode 100644
index 00000000000..f27dc64a882
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/ffr_2.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fdump-tree-vect-details --save-temps
--param=vect-hssr-usage=3" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+#include <stdint.h>
+
+#define type uint16_t
+
+type call [[gnu::simd, gnu::const]] (type);
+
+void foo(
+ type * const restrict dst1,
+ type * const restrict src1,
+ type * const restrict src1b,
+ type * const restrict src2,
+ unsigned int n)
+{
+
+ for (int i = 0; i < n; i++) {
+ type v1b = call (src1b[i]);
+ type v1 = src1[i];
+ if (v1 == v1b) {break;}
+ type v2 = src2[i];
+ dst1[i] = v1 + v2;
+ }
+}
+
+/* { dg-final { scan-tree-dump "Will use HSSR" "vect" } } */
+
+// Make sure the call does not come between the loads and the rdffr
+// As the call can clobber the HSSR state
+/*
+** foo:
+** ...
+** ldff1h z[0-9]+\.h, p[0-9]/z, \[x[0-9]+\]
+** ldff1h z[0-9]+\.h, p[0-9]/z, \[x[0-9]+\]
+** ...
+** rdffrs p[0-9]+.b, p[0-9]+/z
+** ...
+** b.nlast \.L[0-9]+
+** ...
+** bl _ZGVsMxv_call
+** ...
+*/
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/ffr_3.c
b/gcc/testsuite/gcc.target/aarch64/sve/ffr_3.c
new file mode 100644
index 00000000000..49d31165983
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/ffr_3.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+
+/* { dg-options "-O3 -fdump-tree-vect-details
--param=aarch64-autovec-preference=VNx4QI --param=vect-hssr-usage=3" } */
+// Select VNx4SI specifically to test widening loads
+
+#include <stdint.h>
+
+int foo (char *restrict a, char *restrict b, int N) {
+ for (int i = 0; i < N; i++)
+ {
+ if (a[i] + b[i] == 0)
+ return 1;
+ }
+ return 0;
+}
+
+/* { dg-final { scan-tree-dump "Will use HSSR" "vect" } } */
+/* Check it actually uses the widening loads as desired. */
+/* { dg-final { scan-assembler-times {\tldff1b\tz[0-9]+\.s, p[0-9]+/z,} 2 } }
*/
+/* Check it doesn't try extend the already extended loads. */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.h, p[0-9]+/m,} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/ffr_4.c
b/gcc/testsuite/gcc.target/aarch64/sve/ffr_4.c
new file mode 100644
index 00000000000..189815f1ed1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/ffr_4.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+
+/* { dg-options "-O3 -fdump-tree-vect-details
--param=aarch64-autovec-preference=VNx8QI --param=vect-hssr-usage=3" } */
+// Select VNx8HI specifically to test widening loads
+
+#include <stdint.h>
+
+int foo (char *restrict a, char *restrict b, int N) {
+ for (int i = 0; i < N; i++)
+ {
+ if (a[i] + b[i] == 0)
+ return 1;
+ }
+ return 0;
+}
+
+/* { dg-final { scan-tree-dump "Will use HSSR" "vect" } } */
+/* Check it actually uses the widening loads as desired. */
+/* { dg-final { scan-assembler-times {\tldff1b\tz[0-9]+\.h, p[0-9]+/z,} 2 } }
*/
+/* Check it doesn't try extend the already extended loads. */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.h, p[0-9]+/m,} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/noeffect11.c
b/gcc/testsuite/gcc.target/aarch64/sve/noeffect11.c
index 5c8c3565da6..0f781496fad 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/noeffect11.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/noeffect11.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O3 -march=armv8-a+sve
--param=aarch64-autovec-preference=sve-only -msve-vector-bits=scalable" } */
+/* { dg-options "-O3 -march=armv8-a+sve
--param=aarch64-autovec-preference=sve-only -msve-vector-bits=scalable
--param=vect-hssr-usage=0" } */
/* { dg-final { check-function-bodies "**" "" "" } } */
/*
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_1.c
index e9afc2047e4..ed454669ab2 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_1.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* Pick an arbitrary target for which unaligned accesses are more
expensive. */
-/* { dg-options "-O3 -msve-vector-bits=256 -mtune=thunderx" } */
+/* { dg-options "-O3 -msve-vector-bits=256 -mtune=thunderx
--param=vect-hssr-usage=0" } */
#define N 512
#define START 1
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_11.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_11.c
index 37806adea7b..158a1c22d17 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_11.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_11.c
@@ -1,6 +1,6 @@
/* Peeling for alignment with masking in VLA modes. */
/* { dg-do compile } */
-/* { dg-options "-Ofast -msve-vector-bits=scalable --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
+/* { dg-options "-Ofast -msve-vector-bits=scalable --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details
--param=vect-hssr-usage=0" } */
#define START 3
#define END 510
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_12.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_12.c
index e3ed63afb05..2eaa374cae7 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_12.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_12.c
@@ -1,6 +1,6 @@
/* Peeling for alignment with masking together with versioning in VLA modes.
*/
/* { dg-do compile } */
-/* { dg-options "-Ofast -msve-vector-bits=scalable --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
+/* { dg-options "-Ofast -msve-vector-bits=scalable --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details
--param=vect-hssr-usage=0" } */
#define START 5
#define END 509
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_13.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_13.c
index 730e33ed8f7..e733bd05e06 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_13.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_13.c
@@ -1,6 +1,6 @@
/* Known inbounds DR in VLA modes. */
/* { dg-do compile } */
-/* { dg-options "-Ofast -msve-vector-bits=scalable --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
+/* { dg-options "-Ofast -msve-vector-bits=scalable --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details
--param=vect-hssr-usage=0" } */
#define N 512
#define START 5
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_14.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_14.c
index b2f4650bb2c..6a7a4bafc88 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_14.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_14.c
@@ -1,6 +1,6 @@
/* Fix for PR123089 alignment peeling with vectors and VLS and overflows. */
/* { dg-do compile } */
-/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only
-fdump-tree-vect-details" } */
+/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only
-fdump-tree-vect-details --param=vect-hssr-usage=0" } */
/* { dg-additional-options "-msve-vector-bits=256" { target aarch64_sve256_hw
} } */
/* { dg-additional-options "-msve-vector-bits=128" { target aarch64_sve128_hw
} } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_15.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_15.c
index b2f4650bb2c..6a7a4bafc88 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_15.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_15.c
@@ -1,6 +1,6 @@
/* Fix for PR123089 alignment peeling with vectors and VLS and overflows. */
/* { dg-do compile } */
-/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only
-fdump-tree-vect-details" } */
+/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only
-fdump-tree-vect-details --param=vect-hssr-usage=0" } */
/* { dg-additional-options "-msve-vector-bits=256" { target aarch64_sve256_hw
} } */
/* { dg-additional-options "-msve-vector-bits=128" { target aarch64_sve128_hw
} } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_16.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_16.c
index b2f4650bb2c..6a7a4bafc88 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_16.c
@@ -1,6 +1,6 @@
/* Fix for PR123089 alignment peeling with vectors and VLS and overflows. */
/* { dg-do compile } */
-/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only
-fdump-tree-vect-details" } */
+/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only
-fdump-tree-vect-details --param=vect-hssr-usage=0" } */
/* { dg-additional-options "-msve-vector-bits=256" { target aarch64_sve256_hw
} } */
/* { dg-additional-options "-msve-vector-bits=128" { target aarch64_sve128_hw
} } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_17.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_17.c
index 5395a759c61..08623e8f379 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_17.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_17.c
@@ -1,6 +1,6 @@
/* Fix for PR123089 alignment peeling with vectors and VLS and overflows. */
/* { dg-do compile } */
-/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only
-fdump-tree-vect-details" } */
+/* { dg-options "-Ofast --param aarch64-autovec-preference=sve-only
-fdump-tree-vect-details --param=vect-hssr-usage=0" } */
/* { dg-additional-options "-msve-vector-bits=256" { target aarch64_sve256_hw
} } */
/* { dg-additional-options "-msve-vector-bits=128" { target aarch64_sve128_hw
} } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c
index f07900b2f0a..cb0a1e8cf88 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* Pick an arbitrary target for which unaligned accesses are more
expensive. */
-/* { dg-options "-O3 -msve-vector-bits=256 -mtune=thunderx
-fno-vect-cost-model" } */
+/* { dg-options "-O3 -msve-vector-bits=256 -mtune=thunderx
-fno-vect-cost-model --param=vect-hssr-usage=0" } */
#define N 512
#define START 7
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_3.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_3.c
index 15da5a7e696..5f014e568e1 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_3.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* Pick an arbitrary target for which unaligned accesses are more
expensive. */
-/* { dg-options "-O3 -msve-vector-bits=256 -mtune=thunderx
-fno-vect-cost-model" } */
+/* { dg-options "-O3 -msve-vector-bits=256 -mtune=thunderx
-fno-vect-cost-model --param=vect-hssr-usage=0" } */
#define N 32
#define MAX_START 8
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_4.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_4.c
index 5b5d88ad521..ad9ed058a48 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_4.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* Pick an arbitrary target for which unaligned accesses are more
expensive. */
-/* { dg-options "-Ofast -msve-vector-bits=256 -mtune=thunderx
-fno-vect-cost-model" } */
+/* { dg-options "-Ofast -msve-vector-bits=256 -mtune=thunderx
-fno-vect-cost-model --param=vect-hssr-usage=0" } */
#define START 1
#define END 505
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_5.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_5.c
index 1977bf3af2d..ac448ed1db4 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_5.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_5.c
@@ -1,6 +1,6 @@
/* Fix for PR119351 alignment peeling with vectors and VLS. */
/* { dg-do compile } */
-/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
+/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details
--param=vect-hssr-usage=0" } */
#define N 512
#define START 2
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_6.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_6.c
index 0b40d26ae2a..d725f636117 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_6.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_6.c
@@ -1,6 +1,6 @@
/* Fix for PR119351 alignment peeling with vectors and VLS. */
/* { dg-do compile } */
-/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
+/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details
--param=vect-hssr-usage=0" } */
#define N 512
#define START 1
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_7.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_7.c
index 7a24d689e95..c7da8828313 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_7.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_7.c
@@ -1,6 +1,6 @@
/* Fix for PR119351 alignment peeling with vectors and VLS. */
/* { dg-do compile } */
-/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
+/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details
--param=vect-hssr-usage=0" } */
#define N 512
#define START 1
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_8.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_8.c
index 043348b55d0..58e36d1fcb1 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_8.c
@@ -1,6 +1,6 @@
/* Fix for PR119351 alignment peeling with vectors and VLS. */
/* { dg-do compile } */
-/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
+/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details
--param=vect-hssr-usage=0" } */
#define N 512
#define START 1
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_9.c
b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_9.c
index 136d18c2ea8..a08d4aa5be5 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_9.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_9.c
@@ -1,6 +1,6 @@
/* Fix for PR119351 alignment peeling with vectors and VLS. */
/* { dg-do compile } */
-/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
+/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details
--param=vect-hssr-usage=0" } */
#define N 512
#define START 1
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peeled.c
b/gcc/testsuite/gcc.target/aarch64/sve/peeled.c
index f40ffc8f0bc..60c6c7877b1 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peeled.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peeled.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -mautovec-preference=sve-only -msve-vector-bits=scalable"
} */
+/* { dg-options "-O3 -mautovec-preference=sve-only -msve-vector-bits=scalable
--param=vect-hssr-usage=0" } */
char b[100];
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peeled1.c
b/gcc/testsuite/gcc.target/aarch64/sve/peeled1.c
index 92e5bca44c4..5a5e398ad5d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peeled1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peeled1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -mautovec-preference=sve-only -msve-vector-bits=scalable"
} */
+/* { dg-options "-O3 -mautovec-preference=sve-only -msve-vector-bits=scalable
--param=vect-hssr-usage=0" } */
char b[100];
char e[100];
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peeled2.c
b/gcc/testsuite/gcc.target/aarch64/sve/peeled2.c
index c29dab4b553..4620e9965e1 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peeled2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peeled2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -mautovec-preference=sve-only -msve-vector-bits=scalable"
} */
+/* { dg-options "-O3 -mautovec-preference=sve-only -msve-vector-bits=scalable
--param=vect-hssr-usage=0" } */
char b[100];
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peeled3.c
b/gcc/testsuite/gcc.target/aarch64/sve/peeled3.c
index 8d82828b770..e629b0898d3 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/peeled3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/peeled3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -mautovec-preference=sve-only -msve-vector-bits=scalable
-fdump-tree-vect-details" } */
+/* { dg-options "-O3 -mautovec-preference=sve-only -msve-vector-bits=scalable
-fdump-tree-vect-details --param=vect-hssr-usage=0" } */
int __attribute__ ((noipa))
c (int *restrict x, int *restrict y, int n)
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr119351.c
b/gcc/testsuite/gcc.target/aarch64/sve/pr119351.c
index 1aca6c7de1d..f58c31e52ae 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pr119351.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr119351.c
@@ -1,6 +1,6 @@
/* Fix for PR119351 alignment peeling with vectors and VLS. */
/* { dg-do compile } */
-/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
+/* { dg-options "-Ofast -msve-vector-bits=256 --param
aarch64-autovec-preference=sve-only -fdump-tree-vect-details
--param=vect-hssr-usage=0" } */
/* { dg-final { check-function-bodies "**" "" ""} } */
#define N 512
--
2.43.0
